head 1.1; branch 1.1.1; access ; symbols initial:1.1.1.1 diogenes:1.1.1; locks ; strict; comment @# @; 1.1 date 2008.01.16.20.32.50; author fellnhofer; state Exp; branches 1.1.1.1; next ; commitid 122547a751ef4567; 1.1.1.1 date 2008.01.16.20.32.50; author fellnhofer; state Exp; branches ; next ; commitid 122547a751ef4567; desc @@ 1.1 log @Initial revision @ text @ HpGi}Gieeeieeey'ieeestd_logic_1164ALLy:dmemqy*6N!ema.:R iyqI q+y@@ A'Q2Y#)'@@Av[A.:addr.p-*'v::clk:p.62@@Bi'Q2>FQJ9@@Biv[BiR :dinR p/N!J9@@Y'Q2U]a@@Yv[Yiy:doutiyp0ea:weqIp1ma2P% q}$/home/andi/xilinx/rs232/cpu/dmem.vhdydmemworkdmemworkstandardstdstd_logic_1164IEEE@ 1.1.1.1 log @ @ text @@