head 1.1; branch 1.1.1; access ; symbols initial:1.1.1.1 diogenes:1.1.1; locks ; strict; comment @# @; 1.1 date 2008.01.16.20.32.50; author fellnhofer; state Exp; branches 1.1.1.1; next ; commitid 122547a751ef4567; 1.1.1.1 date 2008.01.16.20.32.50; author fellnhofer; state Exp; branches ; next ; commitid 122547a751ef4567; desc @@ 1.1 log @Initial revision @ text @ HpGŽiù}Gieeeieeey€'ieeestd_logic_1164ALLy:dmemqy*ù6±N!e‘ma.á:™R iyqI ¹q+¡‰y@@ A'Q2Y#)'@@Av˜[A.á:addr.á‰p-*ù'‰v€ë:™:clk:™‰p.6±2ɉ@@Bi'Q2>�FQJ9@@Biv˜[BiR :dinR ‰p/N!J9‰@@YÙ'Q2Uñ]Áa©@@YÙv˜[YÙiy:doutiy‰p0e‘a©‰:weqI‰p1ma2ɉP%Ñ¡ ¹q}‚$/home/andi/xilinx/rs232/cpu/dmem.vhdyédmemworkdmemworkstandardstdstd_logic_1164IEEE@ 1.1.1.1 log @ @ text @@