head     1.1;
branch   1.1.1;
access   ;
symbols  initial:1.1.1.1 diogenes:1.1.1;
locks    ; strict;
comment  @# @;


1.1
date     2008.01.16.19.01.32;  author fellnhofer;  state Exp;
branches 1.1.1.1;
next     ;
commitid        122547a751ef4567;

1.1.1.1
date     2008.01.16.19.01.32;  author fellnhofer;  state Exp;
branches ;
next     ;
commitid        122547a751ef4567;


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1.1
log
@Initial revision
@
text
@vhdl work "/home/andi/xilinx/rs232/types.vhd"
vhdl work "/home/andi/xilinx/rs232/pmem.vhd"
vhdl work "/home/andi/xilinx/rs232/fifo.vhd"
vhdl work "/home/andi/xilinx/rs232/cpu/regfile.vhd"
vhdl work "/home/andi/xilinx/rs232/cpu/cmp.vhd"
vhdl work "/home/andi/xilinx/rs232/cpu/alu.vhd"
vhdl work "/home/andi/xilinx/rs232/cpu/fetch.vhd"
vhdl work "/home/andi/xilinx/rs232/cpu/execute.vhd"
vhdl work "/home/andi/xilinx/rs232/cpu/decode.vhd"
vhdl work "/home/andi/xilinx/rs232/sc_uart.vhd"
vhdl work "/home/andi/xilinx/rs232/cpu/cpu.vhd"
vhdl work "/home/andi/xilinx/rs232/sio.vhd"
@


1.1.1.1
log
@
@
text
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