head     1.1;
branch   1.1.1;
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symbols  initial:1.1.1.1 diogenes:1.1.1;
locks    ; strict;
comment  @# @;


1.1
date     2008.01.28.20.06.16;  author fellnhofer;  state Exp;
branches 1.1.1.1;
next     ;
commitid        122547a751ef4567;

1.1.1.1
date     2008.01.28.20.06.16;  author fellnhofer;  state Exp;
branches ;
next     ;
commitid        122547a751ef4567;


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1.1
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Release 9.2i Trace 
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.

trce -ise /home/andi/xilinx/diogenes/vhdl/rs232.ise -intstyle ise -e 3 -s 4
-xml mysio mysio.ncd -o mysio.twr mysio.pcf -ucf sio.ucf

Design file:              mysio.ncd
Physical constraint file: mysio.pcf
Device,package,speed:     xc3s500e,fg320,-4 (PRODUCTION 1.26 2007-04-13)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.

================================================================================
Timing constraint: NET "gclk_BUFGP/IBUFG" PERIOD = 12 ns HIGH 50%;

 69212 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum period is  11.960ns.
--------------------------------------------------------------------------------


All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock gclk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
gclk           |   11.960|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 69212 paths, 0 nets, and 5856 connections

Design statistics:
   Minimum period:  11.960ns   (Maximum frequency:  83.612MHz)


Analysis completed Mon Jan 28 21:06:16 2008 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 104 MB



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