head 1.1; branch 1.1.1; access ; symbols arelease:1.1.1.1 avendor:1.1.1; locks ; strict; comment @# @; 1.1 date 2008.08.05.19.44.06; author fpga_is_funny; state Exp; branches 1.1.1.1; next ; commitid 5d94898abca4567; 1.1.1.1 date 2008.08.05.19.44.06; author fpga_is_funny; state Exp; branches ; next ; commitid 5d94898abca4567; desc @@ 1.1 log @Initial revision @ text @-- VHDL Entity R65C02_TC.ALU.symbol -- -- Created: -- by - eda.UNKNOWN (ENTWICKL4-XP-PR) -- at - 19:53:11 05.08.2008 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; entity ALU is port( a : in std_logic_vector (7 downto 0); b : in std_logic_vector (7 downto 0); reg_0F_in : in std_logic; reg_3F_in : in std_logic; reg_7F_in : in std_logic; sel_add_sub : in std_logic; sel_d : in std_logic_vector (2 downto 0); d_out : out std_logic_vector (7 downto 0); reg_0F : out std_logic; reg_1F : out std_logic; reg_6F : out std_logic; reg_7F : out std_logic ); -- Declarations end ALU ; -- Jens-D. Gutschmidt Project: R65C02_TC -- scantara2003@@yahoo.de -- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG -- -- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or any later version. -- -- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License along with this program. If not, see . -- -- CVS Revisins History -- -- $Log$ -- -- Title: ALU -- Path: R65C02_TC/ALU/struct -- Edited: by eda on 05 Aug 2008 -- -- VHDL Architecture R65C02_TC.ALU.struct -- -- Created: -- by - eda.UNKNOWN (ENTWICKL4-XP-PR) -- at - 19:53:12 05.08.2008 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; library R65C02_TC; architecture struct of ALU is -- Architecture declarations -- Internal signal declarations signal decode : std_logic_vector(7 downto 0); signal decode_neg : std_logic_vector(7 downto 0); signal din : std_logic; signal din0 : std_logic; signal din1 : std_logic; signal din2 : std_logic; signal din3 : std_logic; signal q_a : std_logic_vector(7 downto 0); signal q_and : std_logic_vector(7 downto 0); signal q_or : std_logic_vector(7 downto 0); signal q_xor : std_logic_vector(7 downto 0); signal reg_0F_in1 : std_logic := '0'; signal sel : std_logic_vector(1 downto 0); signal val_one : std_logic_vector(7 downto 0); signal val_two : std_logic_vector(7 downto 0); signal val_zero : std_logic_vector(7 downto 0); -- Implicit buffer signal declarations signal d_out_internal : std_logic_vector (7 downto 0); -- Component Declarations component ADD_SUB port ( d_in : in std_logic_vector ( 7 downto 0 ) := X"00"; reg_0F_in : in std_logic := '0'; reg_7F_in : in std_logic := '0'; reg_a_in : in std_logic_vector ( 7 downto 0 ) := X"00"; sel : in std_logic_vector ( 1 downto 0 ) := "00"; reg_0F : out std_logic := '0'; reg_6F : out std_logic := '0'; reg_a : out std_logic_vector ( 7 downto 0 ) := X"00"; zw_alu : inout std_logic_vector ( 8 downto 0 ) := '0' & X"00"; zw_alu1 : inout std_logic_vector ( 8 downto 0 ) := '0' & X"00"; zw_alu2 : inout std_logic_vector ( 8 downto 0 ) := '0' & X"00"; zw_alu3 : inout std_logic_vector ( 8 downto 0 ) := '0' & X"00"; zw_alu4 : inout std_logic_vector ( 8 downto 0 ) := '0' & X"00" ); end component; -- Optional embedded configurations -- pragma synthesis_off for all : ADD_SUB use entity R65C02_TC.ADD_SUB; -- pragma synthesis_on begin -- Architecture concurrent statements -- HDL Embedded Text Block 3 eb3 -- eb1 1 val_zero (7 downto 0) <= X"00"; val_one (7 downto 0) <= X"01"; val_two (7 downto 0) <= X"02"; sel(0) <= reg_3F_in AND sel_d(0); sel(1) <= sel_add_sub; -- ModuleWare code(v1.9) for instance 'U_15' of 'decoder1' u_15combo_proc: process (a(2 DOWNTO 0)) begin decode <= (others => '0'); case a(2 DOWNTO 0) is when "000" => decode(0) <= '1'; when "001" => decode(1) <= '1'; when "010" => decode(2) <= '1'; when "011" => decode(3) <= '1'; when "100" => decode(4) <= '1'; when "101" => decode(5) <= '1'; when "110" => decode(6) <= '1'; when "111" => decode(7) <= '1'; when others => decode <= (others => '0'); end case; end process u_15combo_proc; -- ModuleWare code(v1.9) for instance 'U_4' of 'inv' decode_neg <= not(decode); -- ModuleWare code(v1.9) for instance 'U_8' of 'inv' reg_1F <= not(din); -- ModuleWare code(v1.9) for instance 'U_9' of 'inv' reg_7F <= not(din1); -- ModuleWare code(v1.9) for instance 'U_10' of 'inv' din1 <= not(d_out_internal(7)); -- ModuleWare code(v1.9) for instance 'U_14' of 'inv' din3 <= not(sel_d(0)); -- ModuleWare code(v1.9) for instance 'U_5' of 'mux' u_5combo_proc: process(q_and, q_or, q_xor, decode, decode_neg, q_a, val_zero, sel_d) begin case sel_d is when "000" => d_out_internal <= q_and; when "001" => d_out_internal <= q_or; when "010" => d_out_internal <= q_xor; when "011" => d_out_internal <= decode; when "100" => d_out_internal <= decode_neg; when "101" => d_out_internal <= q_a; when "110" => d_out_internal <= q_a; when "111" => d_out_internal <= val_zero; when others => d_out_internal <= (others => 'X'); end case; end process u_5combo_proc; -- ModuleWare code(v1.9) for instance 'U_7' of 'por' din <= d_out_internal(0) or d_out_internal(1) or d_out_internal(2) or d_out_internal(3) or d_out_internal(4) or d_out_internal(5) or d_out_internal(6) or d_out_internal(7); -- ModuleWare code(v1.9) for instance 'U_0' of 'sand' q_and <= a and b; -- ModuleWare code(v1.9) for instance 'U_11' of 'sand' din0 <= sel_d(0) and reg_0F_in; -- ModuleWare code(v1.9) for instance 'U_13' of 'sand' din2 <= din3 and sel_add_sub; -- ModuleWare code(v1.9) for instance 'U_1' of 'sor' q_or <= a or b; -- ModuleWare code(v1.9) for instance 'U_12' of 'sor' reg_0F_in1 <= din0 or din2; -- ModuleWare code(v1.9) for instance 'U_2' of 'sxor' q_xor <= a xor b; -- Instance port mappings. U_6 : ADD_SUB port map ( d_in => b, reg_0F_in => reg_0F_in1, reg_7F_in => reg_7F_in, reg_a_in => a, sel => sel, reg_0F => reg_0F, reg_6F => reg_6F, reg_a => q_a, zw_alu => open, zw_alu1 => open, zw_alu2 => open, zw_alu3 => open, zw_alu4 => open ); -- Implicit buffered output assignments d_out <= d_out_internal; end struct; @ 1.1.1.1 log @loading source files "rtl" and "doc" STATE is BETA. @ text @@