head	1.3;
access;
symbols;
locks; strict;
comment	@# @;


1.3
date	2008.06.23.10.58.21;	author pfulgoni;	state Exp;
branches;
next	1.2;
commitid	35d0485f81c34567;

1.2
date	2008.04.14.13.26.36;	author pfulgoni;	state Exp;
branches;
next	1.1;
commitid	1cb948035b8a4567;

1.1
date	2008.03.03.13.19.19;	author pfulgoni;	state Exp;
branches;
next	;
commitid	7e7847cbfad44567;


desc
@@


1.3
log
@registers optimization, new signal output-ready
@
text
@
--------------------------------------------------------------------------------
-- Designer:      Paolo Fulgoni <pfulgoni@@opencores.org>
--
-- Create Date:   09/14/2007
-- Last Update:   04/14/2008
-- Project Name:  camellia-vhdl
-- Description:   Dual-port SBOX4
--
-- Copyright (C) 2007  Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;


entity SBOX4 is
    port  (
    		clk   : IN  STD_LOGIC;
            addra : IN  STD_LOGIC_VECTOR(0 to 7);
            addrb : IN  STD_LOGIC_VECTOR(0 to 7);
            douta : OUT STD_LOGIC_VECTOR(0 to 7);
            doutb : OUT STD_LOGIC_VECTOR(0 to 7)
            );
end SBOX4;

architecture RTL of SBOX4 is

    component SBOX1 is
        port  (
                clk   : IN  STD_LOGIC;
                addra : IN  STD_LOGIC_VECTOR(0 to 7);
                addrb : IN  STD_LOGIC_VECTOR(0 to 7);
                douta : OUT STD_LOGIC_VECTOR(0 to 7);
                doutb : OUT STD_LOGIC_VECTOR(0 to 7)
                );
    end component;

    -- SBOX1 signals
    signal s1_addra : STD_LOGIC_VECTOR(0 to 7);
    signal s1_addrb : STD_LOGIC_VECTOR(0 to 7);
    signal s1_clk  : STD_LOGIC;
    signal s1_douta : STD_LOGIC_VECTOR(0 to 7);
    signal s1_doutb : STD_LOGIC_VECTOR(0 to 7);

begin

    S1 : SBOX1
        port map(s1_clk, s1_addra, s1_addrb, s1_douta, s1_doutb);

    s1_clk   <= clk;
    s1_addra <= addra(1 to 7) & addra(0);
    s1_addrb <= addrb(1 to 7) & addrb(0);

    douta <= s1_douta;
    doutb <= s1_doutb;

end RTL;
@


1.2
log
@right now sbox infer a block ram.
minor changes.
STILL NOT WORKING!
@
text
@d6 1
a6 1
-- Last Update:   04/09/2008
d66 2
a67 2
    s1_addra <= addra;
    s1_addrb <= addrb;
@


1.1
log
@*** empty log message ***
@
text
@d6 1
a6 1
-- Last Update:   09/22/2007
d33 3
a35 4
            addra : IN STD_LOGIC_VECTOR(0 to 7);
            addrb : IN STD_LOGIC_VECTOR(0 to 7);
            clka  : IN STD_LOGIC;
            clkb  : IN STD_LOGIC;
d37 1
a37 3
            doutb : OUT STD_LOGIC_VECTOR(0 to 7);
            ena   : IN STD_LOGIC;
            enb   : IN STD_LOGIC
d45 3
a47 4
                addra : IN STD_LOGIC_VECTOR(0 to 7);
                addrb : IN STD_LOGIC_VECTOR(0 to 7);
                clka  : IN STD_LOGIC;
                clkb  : IN STD_LOGIC;
d49 1
a49 3
                doutb : OUT STD_LOGIC_VECTOR(0 to 7);
                ena   : IN STD_LOGIC;
                enb   : IN STD_LOGIC
d56 1
a56 2
    signal s1_clka  : STD_LOGIC;
    signal s1_clkb  : STD_LOGIC;
a58 2
    signal s1_ena    : STD_LOGIC;
    signal s1_enb    : STD_LOGIC;
d63 1
a63 1
        port map(s1_addra, s1_addrb, s1_clka, s1_clkb, s1_douta, s1_doutb, s1_ena, s1_enb);
d65 3
a67 6
    s1_addra <= addra(1 to 7) & addra(0);
    s1_addrb <= addrb(1 to 7) & addrb(0);
    s1_clka  <= clka;
    s1_clkb  <= clkb;
    s1_ena   <= ena;
    s1_enb   <= enb;
@