head	1.1;
branch	1.1.1;
access;
symbols
	arelease:1.1.1.4
	avendor:1.1.1;
locks; strict;
comment	@# @;


1.1
date	2002.11.06.15.40.20;	author lepetenokr;	state Exp;
branches
	1.1.1.1;
next	;

1.1.1.1
date	2002.11.06.15.40.20;	author lepetenokr;	state Exp;
branches;
next	1.1.1.2;

1.1.1.2
date	2003.01.03.17.56.53;	author lepetenokr;	state Exp;
branches;
next	1.1.1.3;

1.1.1.3
date	2003.01.19.17.06.24;	author lepetenokr;	state Exp;
branches;
next	1.1.1.4;

1.1.1.4
date	2003.02.20.23.52.10;	author lepetenokr;	state Exp;
branches;
next	;


desc
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1.1
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@Initial revision
@
text
@--**********************************************************************************************
--  Parallel Port Peripheral for the AVR Core
--  Version 0.3 02.11.2002	
--  Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;

use WORK.AVRuCPackage.all;

entity pport is 
	generic(
	        PORTX_Adr : std_logic_vector(IOAdrWidth-1 downto 0);
	        DDRX_Adr  : std_logic_vector(IOAdrWidth-1 downto 0);
			PINX_Adr  : std_logic_vector(IOAdrWidth-1 downto 0)
			);
	port(
	                   -- AVR Control
               ireset     : in std_logic;
               cp2	      : in std_logic;
               adr        : in std_logic_vector(5 downto 0);
               dbus_in    : in std_logic_vector(7 downto 0);
               dbus_out   : out std_logic_vector(7 downto 0);
               iore       : in std_logic;
               iowe       : in std_logic;
               out_en     : out std_logic; 
			            -- External connection
			   pinx       : inout std_logic_vector(7 downto 0));
end pport;

architecture rtl of pport is
signal PORTX_Int : std_logic_vector(7 downto 0) := (others => '0');
signal DDRX  : std_logic_vector(7 downto 0) := (others => '0');

signal PORTX_Wr_En : std_logic := '0';
signal DDRX_Wr_En  : std_logic := '0';

signal PORTX_Rd : std_logic := '0';
signal DDRX_Rd  : std_logic := '0';
signal PINX_Rd  : std_logic := '0';

begin

PORTX_Wr_En <= '1' when (adr=PORTX_Adr and iowe='1')else '0';
DDRX_Wr_En  <= '1' when (adr=DDRX_Adr and iowe='1')else '0';

PORTX_Rd <= '1' when (adr=PORTX_Adr and iore='1')else '0';
DDRX_Rd  <= '1' when (adr=DDRX_Adr and iore='1')else '0';	
PINX_Rd  <= '1' when (adr=PINX_Adr and iore='1')else '0';	

out_en <= PORTX_Rd or DDRX_Rd or PINX_Rd;
	
PORTX_DFF:process(cp2,ireset)
begin
if (ireset='0') then                  -- Reset
 PORTX_Int <= (others => '0'); 
  elsif (cp2='1' and cp2'event) then  -- Clock
  if PORTX_Wr_En='1' then             -- Clock enable
  PORTX_Int <= dbus_in;
  end if;
  end if;
end process;		

DDRX_DFF:process(cp2,ireset)
begin
if (ireset='0') then                  -- Reset
 DDRX <= (others => '0'); 
  elsif (cp2='1' and cp2'event) then  -- Clock
  if DDRX_Wr_En='1' then              -- Clock enable
  DDRX <= dbus_in;
  end if;
  end if;
end process;		

Output_Buffers:for i in pinx'range generate
pinx(i) <= PORTX_Int(i) when DDRX(i)='1' else 'Z';
dbus_out(i) <= (PORTX_Int(i) and PORTX_Rd)or(DDRX(i) and DDRX_Rd)or(pinx(i) and PINX_Rd);
end generate;	

end rtl;
@


1.1.1.1
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1.1.1.2
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@d3 1
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--  Version 0.4 02.01.2003
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			   portx      : out std_logic_vector(7 downto 0);
			   ddrx       : out std_logic_vector(7 downto 0);
			   pinx       : in  std_logic_vector(7 downto 0));
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signal PORTX_Int   : std_logic_vector(portx'range) := (others => '0');
signal DDRX_Int    : std_logic_vector(ddrx'range) := (others => '0');
signal PINX_Resinc : std_logic_vector(pinx'range) := (others => '0');

signal PORTX_Sel : std_logic := '0';
signal DDRX_Sel  : std_logic := '0';
signal PINX_Sel  : std_logic := '0';
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PORTX_Sel <= '1' when adr=PORTX_Adr else '0';
DDRX_Sel  <= '1' when adr=DDRX_Adr else '0';	
PINX_Sel  <= '1' when adr=PINX_Adr else '0';	
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out_en <= (PORTX_Sel or DDRX_Sel or PINX_Sel) and iore;
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  if (adr=PORTX_Adr and iowe='1') then             -- Clock enable
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 DDRX_Int <= (others => '0'); 
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  if (adr=DDRX_Adr and iowe='1') then -- Clock enable
  DDRX_Int <= dbus_in;
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PINX_DFF:process(cp2,ireset)
begin
if (ireset='0') then                  -- Reset
 PINX_Resinc <= (others => '0'); 
  elsif (cp2='1' and cp2'event) then  -- Clock
  PINX_Resinc <= pinx;
  end if;
end process;		

DBusOutMux:for i in pinx'range generate
dbus_out(i) <= (PORTX_Int(i) and PORTX_Sel)or(DDRX_Int(i) and DDRX_Sel)or(PINX_Resinc(i) and PINX_Sel);
a78 4

-- Outputs
portx <= PORTX_Int;     
ddrx  <= DDRX_Int;     
@


1.1.1.3
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--  Version 0.4 19.01.2003
@


1.1.1.4
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@d3 1
a3 1
--  Version 0.5 20.03.2003
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signal PINX_Resync : std_logic_vector(pinx'range) := (others => '0');
signal PINX_InReg  : std_logic_vector(pinx'range) := (others => '0');

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PINXSynchronizer:process(cp2,ireset)
begin
if (ireset='0') then                  -- Reset
 PINX_Resync <= (others => '0'); 
  elsif (cp2='0' and cp2'event) then  -- Clock (falling edge)
  PINX_Resync <= pinx;
  end if;
end process;		

PINXInputReg:process(cp2,ireset)
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 PINX_InReg <= (others => '0'); 
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  PINX_InReg <= PINX_Resync;
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dbus_out(i) <= (PORTX_Int(i) and PORTX_Sel)or(DDRX_Int(i) and DDRX_Sel)or(PINX_InReg(i) and PINX_Sel);
@