head 1.11; access; symbols r0_0_1:1.1.1.1 uiuc:1.1.1; locks; strict; comment @# @; 1.11 date 2005.10.10.22.52.17; author zuofu; state Exp; branches; next 1.10; commitid 572434af0884567; 1.10 date 2005.09.30.16.10.47; author zuofu; state Exp; branches; next 1.9; commitid f9b433d636a4567; 1.9 date 2005.09.23.22.05.55; author zuofu; state Exp; branches; next 1.8; commitid 784c43347c414567; 1.8 date 2005.09.23.21.35.27; author zuofu; state Exp; branches; next 1.7; commitid 6e75433475134567; 1.7 date 2005.09.16.20.24.36; author zuofu; state Exp; branches; next 1.6; commitid 77e6432b2a004567; 1.6 date 2005.09.16.15.46.15; author zuofu; state Exp; branches; next 1.5; commitid 3fb7432ae8c24567; 1.5 date 2005.09.14.23.14.08; author cavanaug; state Exp; branches; next 1.4; commitid 1cd44328aebe4567; 1.4 date 2005.09.14.18.17.15; author zuofu; state Exp; branches; next 1.3; commitid 731b432869294567; 1.3 date 2005.09.14.17.42.29; author zuofu; state Exp; branches; next 1.2; commitid 6ad9432860fd4567; 1.2 date 2005.09.14.15.32.04; author zuofu; state Exp; branches; next 1.1; commitid 4c4c432842714567; 1.1 date 2005.09.11.10.29.49; author zuofu; state Exp; branches 1.1.1.1; next ; commitid 469e4324071a4567; 1.1.1.1 date 2005.09.11.10.29.49; author zuofu; state Exp; branches; next ; commitid 469e4324071a4567; desc @@ 1.11 log @GPU HDL design mostly done, intro is now completely working with XSA-50/100 + PIC microcontroller. Working on schematic and ARM processor support. @ text @--ECE395 GPU: --Top Level HDL --===================================================== --Designed by: --Zuofu Cheng --James Cavanaugh --Eric Sands -- --of the University of Illinois at Urbana Champaign --under the direction of Dr. Lippold Haken --==================================================== -- --Heavily based off of HDL examples provided by XESS Corporation --www.xess.com -- --Based in part on Doug Hodson's work which in turn --was based off of the XSOC from Gray Research LLC. -- -- --release under the GNU General Public License --and kindly hosted by www.opencores.org library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.numeric_std.all; use WORK.common.all; use WORK.xsasdram.all; use WORK.sdram.all; use WORK.vga_pckg.all; use WORK.blitter_pckg.all; entity gpuChip is generic( FREQ : natural := 50_000; -- frequency of operation in KHz PIPE_EN : boolean := true; -- enable fast, pipelined SDRAM operation MULTIPLE_ACTIVE_ROWS: boolean := false; -- if true, allow an active row in each bank CLK_DIV : real := 1.0; -- SDRAM Clock div NROWS : natural := 4096; -- number of rows in the SDRAM NCOLS : natural := 512; -- number of columns in each SDRAM row SADDR_WIDTH : natural := 12; DATA_WIDTH : natural := 16; -- SDRAM databus width ADDR_WIDTH : natural := 24; -- host-side address width VGA_CLK_DIV : natural := 4; -- pixel clock = FREQ / CLK_DIV PIXEL_WIDTH : natural := 8; -- width of a pixel in memory NUM_RGB_BITS : natural := 2; -- #bits in each R,G,B component of a pixel PIXELS_PER_LINE : natural := 320; -- width of image in pixels LINES_PER_FRAME : natural := 240; -- height of image in scanlines FIT_TO_SCREEN : boolean := true; -- adapt video timing to fit image width x PORT_TIME_SLOTS : std_logic_vector(15 downto 0) := "0000111111111111" ); port( pin_clkin : in std_logic; -- main clock input from external clock source pin_ce_n : out std_logic; -- Flash RAM chip-enable pin_pushbtn : in std_logic; -- blitter port connections pin_port_in : in std_logic_vector (7 downto 0); pin_port_addr : in std_logic_vector (3 downto 0); pin_load : in std_logic; pin_start : in std_logic; pin_done : out std_logic; pin_flip_buffer: in std_logic; -- vga port connections pin_red : out std_logic_vector(1 downto 0); pin_green : out std_logic_vector(1 downto 0); pin_blue : out std_logic_vector(1 downto 0); pin_hsync_n : out std_logic; pin_vsync_n : out std_logic; -- SDRAM pin connections pin_sclkfb : in std_logic; -- feedback SDRAM clock with PCB delays pin_sclk : out std_logic; -- clock to SDRAM pin_cke : out std_logic; -- SDRAM clock-enable pin_cs_n : out std_logic; -- SDRAM chip-select pin_ras_n : out std_logic; -- SDRAM RAS pin_cas_n : out std_logic; -- SDRAM CAS pin_we_n : out std_logic; -- SDRAM write-enable pin_ba : out std_logic_vector( 1 downto 0); -- SDRAM bank-address pin_sAddr : out std_logic_vector(11 downto 0); -- SDRAM address bus pin_sData : inout std_logic_vector (16-1 downto 0); -- data bus to SDRAM pin_dqmh : out std_logic; -- SDRAM DQMH pin_dqml : out std_logic -- SDRAM DQML ); end gpuChip; architecture arch of gpuChip is constant YES: std_logic := '1'; constant NO: std_logic := '0'; constant HI: std_logic := '1'; constant LO: std_logic := '0'; type gpuState is ( INIT, -- init LOAD, DRAW, REST ); signal state_r, state_x : gpuState; -- state register and next state --registers signal source_address_x, source_address_r : std_logic_vector (ADDR_WIDTH - 1 downto 0); -- sprite dest register signal target_address_x, target_address_r : std_logic_vector (ADDR_WIDTH -1 downto 0); signal source_lines_x, source_lines_r : std_logic_vector (15 downto 0); signal line_size_x, line_size_r : std_logic_vector (11 downto 0); signal alphaOp_x, alphaOp_r : std_logic; signal front_buffer_x, front_buffer_r : std_logic; signal idle_x, idle_r : std_logic; --signal flip_buf_pend_x, flip_buf_pend_r : std_logic; --internal signals signal sysReset : std_logic; -- system reset signal blit_reset : std_logic; signal reset_blitter : std_logic; -- Blitter signals signal blit_begin : std_logic; signal source_address : std_logic_vector(ADDR_WIDTH-1 downto 0); signal source_lines : std_logic_vector (15 downto 0); signal line_size : std_logic_vector (11 downto 0); signal target_address : std_logic_vector(ADDR_WIDTH-1 downto 0); signal blit_done : std_logic; signal alphaOp : std_logic; signal front_buffer : std_logic; signal port_in : std_logic_vector (7 downto 0); signal port_addr : std_logic_vector (3 downto 0); --Application Side Signals for the DualPort Controller signal rst_i : std_logic; --tied reset signal signal opBegun0, opBegun1 : std_logic; -- read/write operation started indicator signal earlyOpBegun0, earlyOpBegun1 : std_logic; -- read/write operation started indicator signal rdPending0, rdPending1 : std_logic; -- read operation pending in SDRAM pipeline indicator signal done0, done1 : std_logic; -- read/write operation complete indicator signal rdDone0, rdDone1 : std_logic; -- read operation complete indicator signal hAddr0, hAddr1 : std_logic_vector(ADDR_WIDTH-1 downto 0); -- host-side address bus signal hDIn0, hDIn1 : std_logic_vector(DATA_WIDTH-1 downto 0); -- host-side data to SDRAM signal hDOut0, hDOut1 : std_logic_vector(DATA_WIDTH-1 downto 0); -- host-side data from SDRAM signal rd0, rd1 : std_logic; -- host-side read control signal signal wr0, wr1 : std_logic; -- host-side write control signal -- SDRAM host side signals signal sdram_bufclk : std_logic; -- buffered input (non-DLL) clock signal sdram_clk1x : std_logic; -- internal master clock signal signal sdram_clk2x : std_logic; -- doubled clock signal sdram_lock : std_logic; -- SDRAM clock DLL lock indicator signal sdram_rst : std_logic; -- internal reset signal signal sdram_rd : std_logic; -- host-side read control signal signal sdram_wr : std_logic; -- host-side write control signal signal sdram_earlyOpBegun : std_logic; signal sdram_OpBegun : std_logic; signal sdram_rdPending : std_logic; signal sdram_done : std_logic; -- SDRAM operation complete indicator signal sdram_rdDone : std_logic; -- host-side read completed signal signal sdram_hAddr : std_logic_vector(ADDR_WIDTH -1 downto 0); -- host address bus signal sdram_hDIn : std_logic_vector(DATA_WIDTH -1 downto 0); -- host-side data to SDRAM signal sdram_hDOut : std_logic_vector(DATA_WIDTH -1 downto 0); -- host-side data from SDRAM signal sdram_status : std_logic_vector(3 downto 0); -- SDRAM controller status -- VGA related signals signal eof : std_logic; -- end-of-frame signal from VGA controller signal full : std_logic; -- indicates when the VGA pixel buffer is full signal vga_address : unsigned(ADDR_WIDTH-1 downto 0); -- SDRAM address counter signal pixels : std_logic_vector(DATA_WIDTH-1 downto 0); signal rst_n : std_logic; --VGA reset (active low) signal drawframe : std_logic; -- flag to indicate whether we are drawing current frame -------------------------------------------------------------------------------------------------------------- -- Beginning of Submodules -- All instances of submodules and signals associated with them -- are declared within. Signals not directly associated with -- submodules are declared elsewhere. -- -------------------------------------------------------------------------------------------------------------- begin ------------------------------------------------------------------------ -- Instantiate the dualport module ------------------------------------------------------------------------ u1 : dualport generic map( PIPE_EN => PIPE_EN, PORT_TIME_SLOTS => PORT_TIME_SLOTS, DATA_WIDTH => DATA_WIDTH, HADDR_WIDTH => ADDR_WIDTH ) port map( clk => sdram_clk1x, -- Memory Port 0 connections rst0 => rst_i, rd0 => rd0, wr0 => wr0, rdPending0 => rdPending0, opBegun0 => opBegun0, earlyOpBegun0 => earlyOpBegun0, rdDone0 => rdDone0, done0 => done0, hAddr0 => hAddr0, hDIn0 => hDIn0, hDOut0 => hDOut0, status0 => open, -- Memory Port 1 connections rst1 => rst_i, rd1 => rd1, wr1 => wr1, rdPending1 => rdPending1, opBegun1 => opBegun1, earlyOpBegun1 => earlyOpBegun1, rdDone1 => rdDone1, done1 => done1, hAddr1 => hAddr1, hDIn1 => hDIn1, hDOut1 => hDOut1, status1 => open, -- connections to the SDRAM controller rst => sdram_rst, rd => sdram_rd, wr => sdram_wr, rdPending => sdram_rdPending, opBegun => sdram_opBegun, earlyOpBegun => sdram_earlyOpBegun, rdDone => sdram_rdDone, done => sdram_done, hAddr => sdram_hAddr, hDIn => sdram_hDIn, hDOut => sdram_hDOut, status => sdram_status ); ------------------------------------------------------------------------ -- Instantiate the SDRAM controller that connects to the dualport -- module and interfaces to the external SDRAM chip. ------------------------------------------------------------------------ u2 : xsaSDRAMCntl generic map( FREQ => FREQ, CLK_DIV => CLK_DIV, PIPE_EN => PIPE_EN, MULTIPLE_ACTIVE_ROWS => MULTIPLE_ACTIVE_ROWS, DATA_WIDTH => DATA_WIDTH, NROWS => NROWS, NCOLS => NCOLS, HADDR_WIDTH => ADDR_WIDTH, SADDR_WIDTH => SADDR_WIDTH ) port map( --Dual Port Controller (Host) Side clk => pin_clkin, -- master clock from external clock source (unbuffered) bufclk => sdram_bufclk, -- buffered master clock output clk1x => sdram_clk1x, -- synchronized master clock (accounts for delays to external SDRAM) clk2x => sdram_clk2x, -- synchronized doubled master clock lock => sdram_lock, -- DLL lock indicator rst => sdram_rst, -- reset rd => sdram_rd, -- host-side SDRAM read control from dualport wr => sdram_wr, -- host-side SDRAM write control from dualport earlyOpBegun => sdram_earlyOpBegun, -- early indicator that memory operation has begun opBegun => sdram_opBegun, -- indicates memory read/write has begun rdPending => sdram_rdPending, -- read operation to SDRAM is in progress done => sdram_done, -- indicates SDRAM memory read or write operation is done rdDone => sdram_rdDone, -- indicates SDRAM memory read operation is done hAddr => sdram_hAddr, -- host-side address from dualport to SDRAM hDIn => sdram_hDIn, -- test data pattern from dualport to SDRAM hDOut => sdram_hDOut, -- SDRAM data output to dualport status => sdram_status, -- SDRAM controller state (for diagnostics) --SDRAM (External) Side sclkfb => pin_sclkfb, -- clock feedback with added external PCB delays sclk => pin_sclk, -- synchronized clock to external SDRAM cke => pin_cke, -- SDRAM clock enable cs_n => pin_cs_n, -- SDRAM chip-select ras_n => pin_ras_n, -- SDRAM RAS cas_n => pin_cas_n, -- SDRAM CAS we_n => pin_we_n, -- SDRAM write-enable ba => pin_ba, -- SDRAM bank address sAddr => pin_sAddr, -- SDRAM address sData => pin_sData, -- SDRAM databus dqmh => pin_dqmh, -- SDRAM DQMH dqml => pin_dqml -- SDRAM DQML ); ------------------------------------------------------------------------------------------------------------ -- Instance of VGA driver, this unit generates the video signals from VRAM ------------------------------------------------------------------------------------------------------------ u3 : vga generic map ( FREQ => FREQ, CLK_DIV => VGA_CLK_DIV, PIXEL_WIDTH => PIXEL_WIDTH, PIXELS_PER_LINE => PIXELS_PER_LINE, LINES_PER_FRAME => LINES_PER_FRAME, NUM_RGB_BITS => NUM_RGB_BITS, FIT_TO_SCREEN => FIT_TO_SCREEN ) port map ( rst => rst_i, clk => sdram_clk1x, -- use the resync'ed master clock so VGA generator is in sync with SDRAM wr => rdDone0, -- write to pixel buffer when the data read from SDRAM is available pixel_data_in => pixels, -- pixel data from SDRAM full => full, -- indicates when the pixel buffer is full eof => eof, -- indicates when the VGA generator has finished a video frame r => pin_red, -- RGB components (output) g => pin_green, b => pin_blue, hsync_n => pin_hsync_n, -- horizontal sync vsync_n => pin_vsync_n, -- vertical sync blank => open ); ------------------------------------------------------------------------------------------------------------ -- instance of main blitter ------------------------------------------------------------------------------------------------------------ u4: Blitter generic map( FREQ => FREQ, PIPE_EN => PIPE_EN, DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH ) port map ( clk =>sdram_clk1x, rst =>blit_reset, rd =>rd1, wr =>wr1, opBegun =>opBegun1, earlyopBegun =>earlyOpBegun1, done =>done1, rddone =>rddone1, rdPending =>rdPending1, Addr =>hAddr1, DIn =>hDIn1, DOut =>hDOut1, blit_begin =>blit_begin, source_address =>source_address, source_lines =>source_lines, target_address =>target_address, line_size =>line_size, alphaOp =>alphaOp, blit_done =>blit_done, front_buffer =>front_buffer ); -------------------------------------------------------------------------------------------------------------- -- End of Submodules -------------------------------------------------------------------------------------------------------------- -- Begin Top Level Module -- connect internal signals rst_i <= sysReset; pin_ce_n <= '1'; -- disable Flash RAM rd0 <= ((not full) and drawframe); -- negate the full signal for use in controlling the SDRAM read operation hDIn0 <= "0000000000000000"; -- don't need to write to port 0 (VGA Port) wr0 <= '0'; hAddr0 <= std_logic_vector(vga_address); blit_reset <= rst_i or reset_blitter; -- Port0 is reserved for VGA pixels <= hDOut0 when drawframe = '1' else "0000000000000000"; port_in <= pin_port_in; port_addr <= pin_port_addr; pin_done <= idle_r; source_address <= source_address_r; line_size <= line_size_r; target_address <= target_address_r; source_lines <= source_lines_r; alphaOp <= alphaOp_r; front_buffer <= YES;--front_buffer_r; comb:process(state_r, port_in, port_addr, pin_start) begin blit_begin <= NO; --default operations reset_blitter <= NO; state_x <= state_r; --default register values source_address_x <= source_address_r; target_address_x <= target_address_r; source_lines_x <= source_lines_r; line_size_x <= line_size_r; alphaOp_x <= alphaOp_r; front_buffer_x <= front_buffer_r; idle_x <= idle_r; case state_r is when INIT => idle_x <= YES; reset_blitter <= YES; state_x <= LOAD; when LOAD => if (pin_load = YES) then case port_addr is when "0000" => source_address_x(23 downto 16) <= port_in; when "0001" => source_address_x(15 downto 8) <= port_in; when "0010" => source_address_x(7 downto 0) <= port_in; when "0011" => target_address_x(23 downto 16) <= port_in; when "0100" => target_address_x(15 downto 8) <= port_in; when "0101" => target_address_x(7 downto 0) <= port_in; when "0110" => source_lines_x (15 downto 8) <= port_in; when "0111" => source_lines_x (7 downto 0) <= port_in; when "1000" => line_size_x (11 downto 8) <= port_in(3 downto 0); when "1001" => line_size_x (7 downto 0) <= port_in; when "1010" => alphaOp_x <= port_in(0); when others => end case; end if; if (pin_start = YES) then idle_x <= NO; state_x <= DRAW; end if; when DRAW => blit_begin <= YES; if (blit_done = YES) then reset_blitter <= YES; idle_x <= YES; state_x <= REST; end if; when REST => reset_blitter <= YES; state_x <= LOAD; end case; end process; -- update the SDRAM address counter process(sdram_clk1x) begin if rising_edge(sdram_clk1x) then --VGA Related Stuff if eof = YES then drawframe <= not drawframe; -- draw every other frame -- reset the address at the end of a video frame depending on which buffer is the front if (front_buffer = YES) then vga_address <= x"000000"; else vga_address <= x"000000"; --temporary end if; elsif (earlyOpBegun0 = YES) then vga_address <= vga_address + 1; -- go to the next address once the read of the current address has begun end if; --reset stuff if (sysReset = YES) then state_r <= INIT; end if; state_r <= state_x; source_address_r <= source_address_x; target_address_r <= target_address_x; source_lines_r <= source_lines_x; line_size_r <= line_size_x; alphaOp_r <= alphaOp_x; front_buffer_r <= front_buffer_x; idle_r <= idle_x; end if; end process; --process reset circuitry process(sdram_bufclk) begin if (rising_edge(sdram_bufclk)) then if sdram_lock='0' then sysReset <= '1'; -- keep in reset until DLLs start up else --sysReset <= '0'; sysReset <= not pin_pushbtn; -- push button will reset end if; end if; end process; end arch;@ 1.10 log @Blitter now mostly works! @ text @d39 1 a39 1 MULTIPLE_ACTIVE_ROWS: boolean := true; -- if true, allow an active row in each bank d45 1 a45 1 ADDR_WIDTH : natural := 23; -- host-side address width d60 9 d101 4 a104 7 INIT_BKG, DRAW_BKG, BLIT_REST, INIT_SPRITE, DRAW_SPRITE, UPDATE ); d109 1 a109 4 signal plane0_dest_r, plane0_dest_x : std_logic_vector (ADDR_WIDTH - 1 downto 0); -- sprite dest register signal plane0_ypos_r, plane0_ypos_x : std_logic_vector (11 downto 0); signal delay_r, delay_x : std_logic_vector (19 downto 0); --20 bit counter for delay signal source_address_x, source_address_r : std_logic_vector (ADDR_WIDTH -1 downto 0); d111 1 a112 1 signal source_lines_x, source_lines_r : std_logic_vector (15 downto 0); d115 2 d133 3 d376 4 d385 1 d388 1 a388 1 comb:process(state_r, delay_r, plane0_dest_r) a393 1 delay_x <= delay_r + 1; a394 1 line_size_x <= line_size_r; d397 1 a398 2 plane0_dest_x <= plane0_dest_r; plane0_ypos_x <= plane0_ypos_r; d400 1 d404 1 a404 1 blit_begin <= NO; d406 19 a424 14 state_x <= INIT_BKG; plane0_dest_x <= x"000060"; plane0_ypos_x <= x"000"; front_buffer_x <= YES; when INIT_BKG => --flip buffers source_address_x <= x"012C00"; line_size_x <= x"0A0"; target_address_x <= x"000000"; source_lines_x <= x"00EF"; alphaOp_x <= NO; blit_begin <= YES; state_x <= DRAW_BKG; d426 6 a431 1 when DRAW_BKG => a432 1 d435 2 a436 1 state_x <= BLIT_REST; d439 1 a439 7 when BLIT_REST => source_address_x <= x"01EBE5"; line_size_x <= x"024"; target_address_x <= plane0_dest_r; source_lines_x <= x"004E"; alphaOp_x <= YES; d441 1 a441 4 state_x <= INIT_SPRITE; when INIT_SPRITE => blit_begin <= YES; a442 22 state_x <= DRAW_SPRITE; when DRAW_SPRITE => blit_begin <= YES; if (blit_done = YES) then reset_blitter <= YES; state_x <= UPDATE; end if; when UPDATE => reset_blitter <= YES; if (delay_r = x"FFFFF") then plane0_dest_x <= plane0_dest_r + x"000140"; plane0_ypos_x <= plane0_ypos_r + x"001"; if (plane0_ypos_r = x"050") then plane0_dest_x <= x"000060"; plane0_ypos_x <= x"000"; end if; state_x <= INIT_BKG; end if; d455 7 a461 6 -- reset the address at the end of a video frame depending on which buffer is the front if (front_buffer = YES) then vga_address <= x"000000"; else vga_address <= x"009600"; end if; d463 1 a463 1 vga_address <= vga_address + 1; -- go to the next address once the read of the current address has begun a471 1 delay_r <= delay_x; a472 1 line_size_r <= line_size_x; d475 1 d477 3 a479 4 plane0_dest_r <= plane0_dest_x; plane0_ypos_r <= plane0_ypos_x; front_buffer_r <= front_buffer_x; @ 1.9 log @fixed up a lot of code, logic for GPU Core is still broken... @ text @d32 1 a32 1 use WORK.gpu_core_pckg.all; d52 1 a52 1 PORT_TIME_SLOTS : std_logic_vector(15 downto 0) := "0000111100001111" d59 1 a59 1 a66 6 -- SRAM Cache connections --pin_cData : inout std_logic_vector(15 downto 0); -- data bus to Cache --pin_cAddr : out std_logic_vector(14 downto 0); -- Cache address bus --pin_cwrite : out std_logic; --pin_cread : out std_logic; d90 23 a113 1 signal sysClk : std_logic; -- system clock d115 2 d118 5 a122 2 signal start_read : std_logic; signal source_address : std_logic_vector(ADDR_WIDTH-1 downto 0); d124 4 a127 2 signal end_address : std_logic_vector(ADDR_WIDTH-1 downto 0); d217 2 a218 1 -- connections to the SDRAM controller d286 1 a286 1 -- instance of vga a314 1 d316 1 a316 1 -- instance of fill-unit d319 1 a319 20 -- u4: fillunit -- generic map( -- FREQ => FREQ, -- DATA_WIDTH => DATA_WIDTH, -- HADDR_WIDTH => ADDR_WIDTH -- ) -- port map( -- clk => sdram_clk1x, -- master clock -- reset => sysReset, -- reset for this entity -- rd1 => rd1, -- initiate read operation -- wr1 => wr1, -- initiate write operation -- opBegun => opBegun1, --operation recieved -- done1 => done1, -- read or write operation is done -- hAddr1 => hAddr1, -- address to SDRAM -- hDIn1 => hDIn1, -- data to dualport to SDRAM -- hDOut1 => hDOut1 -- data from dualport to SDRAM -- ); -- u5: gpu_core d322 3 a324 2 DATA_WIDTH => DATA_WIDTH, HADDR_WIDTH => ADDR_WIDTH d327 13 a339 9 clk =>sdram_clk1x, rst =>sysReset, rd1 =>rd1, wr1 =>wr1, opBegun1 =>opBegun1, done1 =>done1, rddone1 =>rddone1, rdPending1 =>rdPending1, start_read =>start_read, d341 1 d343 4 a346 8 end_address =>end_address, hAddr1 =>hAddr1, hDIn1 =>hDIn1, hDOut1 =>hDOut1 --CacheDIn =>pin_cData, --CacheAddr =>pin_cAddr, --cread =>pin_cread, --cwrite =>pin_cwrite d354 1 a354 1 -- connect internal signals d357 3 a359 2 rd0 <= ((not full) and drawframe); -- negate the full signal for use in controlling the SDRAM read operation hDIn0 <= "0000000000000000"; -- don't need to write to port 0 (VGA Port) d362 2 d366 8 d375 80 a454 1 pixels <= hDOut0 when drawframe = '1' else "0000000000000000"; d460 3 a462 1 if eof = YES then d464 9 a472 5 vga_address <= "00000000000000000000000"; -- reset the address at the end of a video frame elsif earlyOpBegun0 = YES then vga_address <= vga_address + 1; -- go to the next address once the read of the current address has begun elsif drawframe = '0' then vga_address <= vga_address + 1; --if we're not drawing a frame, keep incrementing the address d474 18 a491 1 end if; a505 2 @ 1.8 log @fixed small bug in interlacing logic @ text @d68 4 a71 4 pin_cData : inout std_logic_vector(15 downto 0); -- data bus to Cache pin_cAddr : out std_logic_vector(14 downto 0); -- Cache address bus pin_cwrite : out std_logic; pin_cread : out std_logic; d100 5 d322 19 a340 14 clk =>sdram_clk1x, rst =>sysReset, rd1 =>rd1, wr1 =>wr1, opBegun =>opBegun1, done1 =>done1, rddone1 =>rddone1, hAddr1 =>hAddr1, hDIn1 =>hDIn1, hDOut1 =>hDOut1, CacheDIn =>pin_cData, CacheAddr =>pin_cAddr, cread =>pin_cread, cwrite =>pin_cwrite @ 1.7 log @fixed main vhdl @ text @d348 1 a348 1 pixels <= hDOut0 when drawframe = '1' else "00000000"; @ 1.6 log @added (broken) GPUCore @ text @a31 1 <<<<<<< gpuchip.vhd a32 3 ======= use WORK.fillunit_pckg.all; >>>>>>> 1.5 @ 1.5 log @added skeleton blitter block - still need buffer swaps @ text @d32 3 d36 1 d71 6 d290 1 d295 21 a315 2 u4: fillunit generic map( d320 16 a335 14 port map( clk => sdram_clk1x, -- master clock reset => sysReset, -- reset for this entity rd1 => rd1, -- initiate read operation wr1 => wr1, -- initiate write operation opBegun => opBegun1, --operation recieved done1 => done1, -- read or write operation is done hAddr1 => hAddr1, -- address to SDRAM hDIn1 => hDIn1, -- data to dualport to SDRAM hDOut1 => hDOut1 -- data from dualport to SDRAM ); d346 1 a346 1 hDIn0 <= "0000000000000000000000"; -- don't need to write to port 0 (VGA Port) @ 1.4 log @changed it to draw every other frame. Reduces load on memory @ text @d32 1 d52 1 a52 1 PORT_TIME_SLOTS : std_logic_vector(15 downto 0) := "0000000000000000" d250 4 a254 3 ------------------------------------------------------------------------ -- Instantiate the VGA module ------------------------------------------------------------------------ d279 26 @ 1.3 log @color works fully @ text @a91 1 d129 1 d131 2 d267 1 a267 1 pixel_data_in => hDOut0, -- pixel data from SDRAM d284 3 a286 3 pin_ce_n <= '1'; -- disable Flash RAM rd0 <= not full; -- negate the full signal for use in controlling the SDRAM read operation hDIn0 <= "0000000000000000000000"; -- don't need to write to port 0 (VGA Port) d290 3 a292 1 -- Port0 is reserved for VGA d299 2 a300 1 vga_address <= "00000000000000000000000"; -- reset the address at the end of a video frame d303 3 a305 1 end if; @ 1.2 log @made stuff work on XSA-100 again @ text @d45 1 a45 1 VGA_CLK_DIV : natural := 2; -- pixel clock = FREQ / CLK_DIV d48 2 a49 2 PIXELS_PER_LINE : natural := 640; -- width of image in pixels LINES_PER_FRAME : natural := 480; -- height of image in scanlines @ 1.1 log @Initial revision @ text @d12 4 d19 1 d31 1 a31 1 a36 1 CLK_DIV : real := 1.0; -- divisor for FREQ (can only be 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0) d39 1 d43 8 a50 1 a88 16 constant DATA_WIDTH: natural := 16; constant ADDR_WIDTH: natural := 23; -- memory state management variables type VGAStateType is ( VGA_IDLE, -- finished just waiting for a request VGA_READ0, -- Buffer states which may or may not all be executed VGA_READ1, VGA_READ2, VGA_READ3 --VGA_READ4, --VGA_READ5, --VGA_READ6, --VGA_READ7 ); d90 2 a91 5 signal VGAState_r, VGAState_nxt: VGAStateType; signal hAddr_r, hAddr_nxt : std_logic_vector (ADDR_WIDTH-1 downto 0); -- host address bus signal sysClk : std_logic; -- system clock signal sysReset : std_logic; -- system reset a92 2 signal int_clk_by2 : std_logic; --intermediate clock (divide by 2) signal int_clk_by4 : std_logic; --intermediate clock (divide by 4) d95 1 a95 1 signal rst_i :std_logic; --tied reset signal d106 1 d108 23 a130 39 signal sdram_bufclk : std_logic; -- buffered input (non-DLL) clock signal sdram_clk1x : std_logic; -- internal master clock signal signal sdram_clk2x : std_logic; -- doubled clock signal sdram_lock : std_logic; -- SDRAM clock DLL lock indicator signal sdram_rst : std_logic; -- internal reset signal signal sdram_rd : std_logic; -- host-side read control signal signal sdram_wr : std_logic; -- host-side write control signal signal sdram_earlyOpBegun : std_logic; signal sdram_OpBegun : std_logic; signal sdram_rdPending : std_logic; signal sdram_done : std_logic; -- SDRAM operation complete indicator signal sdram_rdDone : std_logic; -- host-side read completed signal signal sdram_hAddr : std_logic_vector(ADDR_WIDTH -1 downto 0); -- host address bus signal sdram_hDIn : std_logic_vector(DATA_WIDTH -1 downto 0); -- host-side data to SDRAM signal sdram_hDOut : std_logic_vector(DATA_WIDTH -1 downto 0); -- host-side data from SDRAM signal sdram_status : std_logic_vector(3 downto 0); -- SDRAM controller status -- vga signals signal vga_clk : std_logic; -- global clock signal vga_vack : std_logic; -- video data DMA acknowledge signal vga_pixels_in : std_logic_vector(15 downto 0); -- video data in signal vga_vreq : std_logic; -- video data DMA request signal vga_vreset : std_logic; -- video data reset DMA counter request --Need to reiterate the VGA component as it is written in Verilog component vga port( clk: in std_logic; -- global clock rst: in std_logic; -- global async reset vack: in std_logic; -- video data DMA acknowledge pixels_in: in std_logic_vector(15 downto 0); -- video data in vreq: out std_logic; -- video data DMA request vreset: out std_logic; -- video data reset DMA counter request hsync_n: out std_logic; -- active low horz sync vsync_n: out std_logic; -- active low vert sync r: out std_logic_vector(1 downto 0); -- red g: out std_logic_vector(1 downto 0); -- green b: out std_logic_vector(1 downto 0) -- blue ); end component; d251 24 a274 17 -- Instance Module u3: vga port map( clk => vga_clk, rst => sysReset, vack => vga_vack, pixels_in => vga_pixels_in, vreq => vga_vreq, vreset => vga_vreset, hsync_n => pin_hsync_n, vsync_n => pin_vsync_n, r => pin_red, g => pin_green, b => pin_blue ); d279 2 a280 2 sysClk <= sdram_clk1x; -- use SDRAM_CLK1X as the system clock d282 19 a300 1 pin_ce_n <= '1'; -- disable Flash RAM d302 1 a302 113 -- cascaded clock dividers process(sysClk) begin if (rising_edge(sysClk)) then if (int_clk_by2 = HI) then int_clk_by2 <= LO; else int_clk_by2 <= HI; end if; end if; end process; process(int_clk_by2) begin if (rising_edge(int_clk_by2)) then if (vga_clk = HI) then vga_clk <= LO; else vga_clk <= HI; end if; end if; end process; -- -- -- process(int_clk_by4) -- begin -- if (rising_edge(int_clk_by4)) then -- if (vga_clk = HI) then -- vga_clk <= LO; -- else -- vga_clk <= HI; -- end if; -- end if; -- end process; -- -- connect internal registers to external busses -- Port1 is reserved for VGA hAddr0 <= hAddr_r; -- memory address bus driven by memory address register vga_pixels_in <= hDOut0; -- memory controller state machine -- "process" the change in status of various signals process(sysReset, VGAState_r, done0, vga_vreq, vga_vreset) begin -- have we been reset? if (sysReset = YES) then VGAState_nxt <= VGA_IDLE; hAddr_nxt <= "00000000000000000000000"; rd0 <= NO; vga_vack <= NO; else rd0 <= NO; -- default no memory read wr0 <= NO; -- default no memory write vga_vack <= NO; -- default no ack of new data to vga circuit VGAState_nxt <= VGAState_r; hAddr_nxt <= hAddr_r; -- next address is the same as current address if (vga_vreset = YES) then -- reset address? hAddr_nxt <= "00000000000000000000000"; end if; case VGAState_r is -- memory idle, just waiting around for a request when VGA_IDLE => if (vga_vreq = YES) then vga_vack <= NO; VGAState_nxt <= VGA_READ0; -- move to read state end if; -- read from memory when VGA_READ0 => rd0 <= YES; -- keep asserting read signal if (done0 = YES) then vga_vack <= YES; VGAState_nxt <= VGA_READ1; end if; when VGA_READ1 => rd0 <= YES; vga_vack <= YES; VGAState_nxt <= VGA_READ2; when VGA_READ2 => rd0 <= YES; vga_vack <= YES; VGAState_nxt <= VGA_READ3; when VGA_READ3 => rd0 <= YES; vga_vack <= YES; hAddr_nxt <= hAddr_r + 1; -- increment address counter VGAState_nxt <= VGA_IDLE; -- whole state machine is synchronized to -- VGA_clk end case; end if; end process; process(sysClk, sysReset) begin if (sysReset=YES) then VGAState_r <= VGA_IDLE; hAddr_r <= "00000000000000000000000"; elsif (rising_edge(sysClk)) then VGAState_r <= VGAState_nxt; hAddr_r <= hAddr_nxt; end if; end process; -- synchronous reset. internal reset flag is set active by config. bitstream -- and then gets reset after DLL clocks start. d314 1 @ 1.1.1.1 log @First Checkin! Using the XESS dual ported RAM controller and the original XSOC (retromicro) VGA driver. Also included a whole bunch of misc stuff.... @ text @@