Wishbone Monitor Controller Palette RAM

Description

Wishbone Monitor Controller Palette RAM is a small piece of dual-ported memory. One of the interfaces is a Wishbone compatible interface with the WishboneTK extensions. This interface is write-only. Any read operations attempted on the port would result in an error (ERR_O goes active). The other port is an asyncronous read-only port. For that port an enable signal is (BLANK) provided. If that signal is active all output bits are driven to 0. Otherwise the output will be the data stored in the memory location identified by the address provided. This type of memory is ideal for palette memory in a monitor controller.

Wishbone datasheet

DescriptionSpecification
General Description Monitor controller palette RAM.
Supported cycles Slave read/write
Slave block read/write
Slave rmw
Data port size Configurable
Data port granularity Bus size
Data port maximum operand size Bus size
Data transfer ordering n/a
Data transfer sequencing n/a
Supported signal list and cross reference to equivalent Wishbone signals
Signal nameWishbone equiv.
CLK_I CLK_I
RST_I RST_I
CYC_I CYC_I
STB_I STB_I
WE_I WE_I
ACK_O ACK_O
ERR_O ERR_O
ADR_I(..) ADR_I()
DAT_I(..) DAT_I()
DAT_O(..) DAT_O()

Parameter description

Parameter nameDescription
v_dat_width True-color pixel output width
v_adr_width Palettized pixel input width
cpu_dat_width CPU data width
cpu_adr_width CPU address width

Signal description

Signal nameDescription
Signals to connect to the pixel memory master
CYC_I Wishbone cycle signal. High value frames blocks of access
STB_I Wishbone strobe signal. High value indicates cycle to this particular device
WE_I Wishbone write enable signal. High indicates data flowing from master to slave
ACK_O Wishbone acknowledge signal. High indicates that slave finished operation sucessfully
ACK_OI WhisboneTK acknowledge chain input signal
ERR_O Wishbone error signal. High indicates that slave cannot complete the last cycle in the block.
ERR_OI WhisboneTK error chain input signal
ADR_I(cpu_adr_width-1..0) Wishbone address bus signals
DAT_I(cpu_dat_width-1..0) Wishbone data bus input (to slave direction) signals
DAT_O(cpu_dat_width-1..0) Wishbone data bus output (to master direction) signals
DAT_OI(cpu_dat_width-1..0) WhisboneTK data bus chain input signal
Non Wishbone signals
BLANK Blanking input signal. If active (high) output is forced to all 0s
V_DAT_I(v_adr_width-1 DOWNTO 0)Palettized data input
V_DAT_O(v_dat_width-1 DOWNTO 0)True-color data output

Author & Maintainer

Andras Tantos