WisboneTK

Test package

Description

The WishboneTK test package contains some procedures that can become useful when it comes to testing. These facilities might not sythetize and that's not their purpose. The procedures contained in this package can read, write and check various values to/from Wishbone slave devices. The procedures handle all handshaking required between master and slave devices. Currently the following procedures are available:

wr_chk_val
wr_val
rd_val
chk_val

wr_chk_val

The procedure issues a write cycle using the wires passed to the function to the address and with the data specified. Than it issues a read cycle to the same address and compares the value with the data specified. It the two values are not the same an assert (severity ERROR) is generated.

The procedure cannot handle ganularity other than the width of the bus. It also cannot hadle ERR and RTY handshake signals. Later versions probably will add this functionality.

Paramters

Name	Direction	Specification
CLK_I	IN	Wishbone clock signal
ADR_I	OUT	Wishbone address bus
DAT_O	IN	Wishbone data bus slave->master direction
DAT_I	OUT	Wishbone data bus master->slave direction
WE_I	OUT	Wishbone write enable signal
CYC_I	OUT	Wishbone active bus-cycle signal
STB_I	OUT	Wishbone strobe signal
ACK_O	IN	Wishbone acknowledge signal
ADDR	IN	Address to write to / read from
DATA	IN	Data to be written / checked against

wr_val

The procedure issues a write cycle using the wires passed to the function to the address and with the data specified.

The procedure cannot handle ganularity other than the width of the bus. It also cannot hadle ERR and RTY handshake signals. Later versions probably will add this functionality.

Paramters

Name	Direction	Specification
CLK_I	IN	Wishbone clock signal
ADR_I	OUT	Wishbone address bus
DAT_O	IN	Wishbone data bus slave->master direction
DAT_I	OUT	Wishbone data bus master->slave direction
WE_I	OUT	Wishbone write enable signal
CYC_I	OUT	Wishbone active bus-cycle signal
STB_I	OUT	Wishbone strobe signal
ACK_O	IN	Wishbone acknowledge signal
ADDR	IN	Address to write to
DATA	IN	Data to be written

rd_val

The procedure issues a read cycle to the address specified. It copies the value read from the Wishbone bus to the data paramter.

The procedure cannot handle ganularity other than the width of the bus. It also cannot hadle ERR and RTY handshake signals. Later versions probably will add this functionality.

Paramters

Name	Direction	Specification
CLK_I	IN	Wishbone clock signal
ADR_I	OUT	Wishbone address bus
DAT_O	IN	Wishbone data bus slave->master direction
DAT_I	OUT	Wishbone data bus master->slave direction
WE_I	OUT	Wishbone write enable signal
CYC_I	OUT	Wishbone active bus-cycle signal
STB_I	OUT	Wishbone strobe signal
ACK_O	IN	Wishbone acknowledge signal
ADDR	IN	Address to read from
DATA	OUT	Returns data read from the Wishbone bus

chk_val

The procedure issues a read cycle to the address specified and compares the value read from the bus with the data specified. It the two values are not the same an assert (severity ERROR) is generated.

The procedure cannot handle ganularity other than the width of the bus. It also cannot hadle ERR and RTY handshake signals. Later versions probably will add this functionality.

Paramters

Name	Direction	Specification
CLK_I	IN	Wishbone clock signal
ADR_I	OUT	Wishbone address bus
DAT_O	IN	Wishbone data bus slave->master direction
DAT_I	OUT	Wishbone data bus master->slave direction
WE_I	OUT	Wishbone write enable signal
CYC_I	OUT	Wishbone active bus-cycle signal
STB_I	OUT	Wishbone strobe signal
ACK_O	IN	Wishbone acknowledge signal
ADDR	IN	Address to read from
DATA	IN	Data to be checked against

Author & Maintainer

Andras Tantos