| Signal name | Description |
|---|
| S_CYC_O | Wishbone cycle signal. High value frames blocks of access |
| S_STB_O | Wishbone strobe signal. High value indicates cycle to this particular device |
| S_WE_O | Wishbone write enable signal. High indicates data flowing from master to slave |
| S_ACK_I | Wishbone acknowledge signal. High indicates that slave finished operation sucessfully |
| S_RTY_I | Wishbone retry signal. High indicates that slave requests retry of the last cycle in the block. |
| S_ERR_I | Wishbone error signal. High indicates that slave cannot complete the last cycle in the block. |
| S_ADR_O(addr_width-2..0) | Wishbone address bus signals |
| S_SEL_O(width/8-1..0) | Wishbone byte-selection signals |
| S_DAT_I(width-1..0) | Wishbone data bus input (to slave direction) signals |
| S_DAT_O(width-1..0) | Wishbone data bus output (to master direction) signals |
| Aysncronous interfce signals |
|---|
| A_DATA(width-1..0) | Bidirectional data bus signals |
| A_ADDR(addr_width-1..0) | Address bus output signals |
| A_RDN | Active low read signal |
| A_WRN | Active low write signal |
| A_CEN | Active low chip-select signal |
| A_BYEN(addr_width/8-1..0) | Active-low byte-enable signals |
| A_WAITN | Active low wait signal |