5. Routes time slots to/from HDLC controller via the backend interface and software support or to/from memory.
6. Supports read for all or partial TDM slots from the ST-bus.
7. Supports write for all or partial TDM slots to ST-bus.
8. Supports two serial lines one input and one output.Mli>9. It supports N×64 mode (i.e. it supports sampling (or writing) to N consecutive time slots)
10. Supports two serial lines one input and one output.
11. Can be connected to other ST-Bus compatible devices via serial or star configurations.
11. If no data is available for transmission it sends all ones.
11. Backend interface uses the Wishbone bus interface which can be connected directly to the system or via FIFO buffer.
12. Optional External FIFO buffer, configuration and status registers.
13. The core will be made of two levels of hierarchies, the basic functionality and the Optional interfaces and buffers which makes it easy to add extra serial lines by duplicating the TDM controllers in parallel.
14. ISDN (2B+D) support can be supported by adding three parallel HDLC controllers on the first three time slots.
15. For complete specifications refer to spec document
