     | | | | | | |
   _________________
  -|               |-
  -|               |-
  -|               |-
  -|    CYPRESS    |-
  -|               |-
  -|               |-   Warp VHDL Synthesis Compiler: Version 4 IR x66
  -|               |-   Copyright (C) 1991, 1992, 1993,
   |_______________|                  1994, 1995, 1996 Cypress Semiconductor
     | | | | | | |

======================================================================
Compiling:  robo_arm.vhd
Options:    -q -o2 -ygs -fO -fP -v10 -yb -yp -dc341 -pCY7C341B-15HC robo_arm.vhd
======================================================================

C:\WARP\BIN\VHDLFE.EXE V4 IR x66:  VHDL parser
Fri Jan 26 15:41:26 2001

Library 'work' => directory 'lc341'
Library 'ieee' => directory 'C:\warp\lib\ieee\work'
Using 'C:\warp\lib\ieee\work\stdlogic.vif'.
Using 'C:\warp\lib\common\stdlogic\mod_gen.vif'.
robo_arm.vhd (line 23, col 19):  Note: Substituting module 'warp_add_1s1c_ss' for '+'.
Library 'ieee' => directory 'C:\warp\lib\ieee\work'
Library 'ieee' => directory 'C:\warp\lib\ieee\work'
Library 'ieee' => directory 'C:\warp\lib\ieee\work'
robo_arm.vhd (line 140, col 23):  Note: Substituting module 'warp_add_1s1c_ss' for '+'.
Library 'ieee' => directory 'C:\warp\lib\ieee\work'
robo_arm.vhd (line 167, col 19):  Note: Substituting module 'warp_cmp_1s1c_ss' for '='.
robo_arm.vhd (line 169, col 22):  Note: Substituting module 'warp_cmp_1s1c_ss' for '='.
robo_arm.vhd (line 171, col 22):  Note: Substituting module 'warp_cmp_1s1c_ss' for '='.
robo_arm.vhd (line 173, col 22):  Note: Substituting module 'warp_cmp_1s1c_ss' for '='.
robo_arm.vhd (line 175, col 22):  Note: Substituting module 'warp_cmp_1s1c_ss' for '='.
robo_arm.vhd (line 177, col 22):  Note: Substituting module 'warp_cmp_1s1c_ss' for '='.
robo_arm.vhd (line 179, col 22):  Note: Substituting module 'warp_cmp_1s1c_ss' for '='.
robo_arm.vhd (line 181, col 22):  Note: Substituting module 'warp_cmp_1s1c_ss' for '='.
robo_arm.vhd (line 186, col 19):  Note: Substituting module 'warp_cmp_1s1c_ss' for '='.
robo_arm.vhd (line 188, col 22):  Note: Substituting module 'warp_cmp_1s1c_ss' for '='.
robo_arm.vhd (line 190, col 22):  Note: Substituting module 'warp_cmp_1s1c_ss' for '='.
robo_arm.vhd (line 192, col 22):  Note: Substituting module 'warp_cmp_1s1c_ss' for '='.
robo_arm.vhd (line 194, col 22):  Note: Substituting module 'warp_cmp_1s1c_ss' for '='.
robo_arm.vhd (line 196, col 22):  Note: Substituting module 'warp_cmp_1s1c_ss' for '='.
robo_arm.vhd (line 198, col 22):  Note: Substituting module 'warp_cmp_1s1c_ss' for '='.
robo_arm.vhd (line 200, col 22):  Note: Substituting module 'warp_cmp_1s1c_ss' for '='.
Library 'ieee' => directory 'C:\warp\lib\ieee\work'
Library 'ieee' => directory 'C:\warp\lib\ieee\work'
Library 'ieee' => directory 'C:\warp\lib\ieee\work'

C:\WARP\BIN\VHDLFE.EXE:  No errors.


C:\WARP\BIN\TOVIF.EXE V4 IR x66:  High-level synthesis
Fri Jan 26 15:41:27 2001

Using 'C:\warp\lib\common\stdlogic\mod_mth.vif'.
Using 'C:\warp\lib\common\work\mod_cnst.vif'.

C:\WARP\BIN\TOVIF.EXE:  No errors.


C:\WARP\BIN\TOPLD.EXE V4 IR x66:  Synthesis and optimization
Fri Jan 26 15:41:31 2001

Using 'C:\warp\lib\lc340\stdlogic\c340.vif'.

----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------



------------------------------------------------------
Alias Detection
------------------------------------------------------

------------------------------------------------------
Aliased 0 equations, 43 wires.
------------------------------------------------------

----------------------------------------------------------
Circuit simplification
----------------------------------------------------------

----------------------------------------------------------
Circuit simplification results:

	Expanded 26 signals.
	Turned 0 signals into soft nodes.
	Maximum expansion cost was set at 10.
----------------------------------------------------------
Created 103 PLD nodes.

C:\WARP\BIN\TOPLD.EXE:  No errors.

----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    17/JUL/96    [v3.22 ] 4 IR x66

DESIGN HEADER INFORMATION  (15:41:35)

Input File(s): robo_arm.pla
Device       : c341
Package      : CY7C341B-15HC
ReportFile   : robo_arm.rpt

Program Controls:
                 None.

Signal Requests:
    GROUP DT-OPT ALL
    GROUP USEPOL ALL

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    17/JUL/96    [v3.22 ] 4 IR x66

OPTIMIZATION OPTIONS       (15:41:35)

Messages:
  Information: Process virtual 'data_out_h_0' ... expanded.
  Information: Process virtual 'data_out_h_1' ... expanded.
  Information: Process virtual 'data_out_h_2' ... expanded.
  Information: Process virtual 'data_out_h_3' ... expanded.
  Information: Process virtual 't2_dout_h_0' ... expanded.
  Information: Process virtual 't2_dout_h_1' ... expanded.
  Information: Process virtual 't2_dout_h_2' ... expanded.
  Information: Process virtual 'data_out_0' ... expanded.
  Information: Process virtual 'data_out_1' ... expanded.
  Information: Process virtual 'data_out_2' ... expanded.
  Information: Process virtual 'data_out_3' ... expanded.
  Information: Process virtual 't1_dout_0' ... expanded.
  Information: Process virtual 't1_dout_1' ... expanded.
  Information: Process virtual 't2_y_h_0D' ... expanded.
  Information: Process virtual 't2_y_h_1D' ... expanded.
  Information: Process virtual 't2_y_h_2D' ... expanded.
  Information: Process virtual 't2_y_h_3D' ... expanded.
  Information: Process virtual 't2_u_h1_count_h_0D' ... expanded.
  Information: Process virtual 't2_u_h1_count_h_1D' ... expanded.
  Information: Process virtual 't2_u_h1_count_h_2D' ... expanded.
  Information: Process virtual 't1_y_0D' ... expanded.
  Information: Process virtual 't1_y_1D' ... expanded.
  Information: Process virtual 't1_y_2D' ... expanded.
  Information: Process virtual 't1_y_3D' ... expanded.
  Information: Process virtual 't1_u1_count_0D' ... expanded.
  Information: Process virtual 't1_u1_count_1D' ... expanded.
  Information: Process virtual 't2_y_h_0' ... converted to NODE.
  Information: Process virtual 't2_y_h_1' ... converted to NODE.
  Information: Process virtual 't2_y_h_2' ... converted to NODE.
  Information: Process virtual 't2_y_h_3' ... converted to NODE.
  Information: Process virtual 't2_u_h1_count_h_0' ... converted to NODE.
  Information: Process virtual 't2_u_h1_count_h_1' ... converted to NODE.
  Information: Process virtual 't2_u_h1_count_h_2' ... converted to NODE.
  Information: Process virtual 't1_y_0' ... converted to NODE.
  Information: Process virtual 't1_y_1' ... converted to NODE.
  Information: Process virtual 't1_y_2' ... converted to NODE.
  Information: Process virtual 't1_y_3' ... converted to NODE.
  Information: Process virtual 't1_u1_count_0' ... converted to NODE.
  Information: Process virtual 't1_u1_count_1' ... converted to NODE.
  Information: Generating both D & T register equations for signal t2_y_h_0.D
  Information: Expanding XOR equation found on signal t2_y_h_0.T
  Information: Expanding XOR equation found on signal t2_y_h_0.Tbar
  Information: Generating both D & T register equations for signal t2_y_h_1.D
  Information: Expanding XOR equation found on signal t2_y_h_1.T
  Information: Expanding XOR equation found on signal t2_y_h_1.Tbar
  Information: Generating both D & T register equations for signal t2_y_h_2.D
  Information: Expanding XOR equation found on signal t2_y_h_2.T
  Information: Expanding XOR equation found on signal t2_y_h_2.Tbar
  Information: Generating both D & T register equations for signal t2_y_h_3.D
  Information: Expanding XOR equation found on signal t2_y_h_3.T
  Information: Expanding XOR equation found on signal t2_y_h_3.Tbar
  Information: Generating both D & T register equations for signal t2_u_h1_count_h_0.D
  Information: Expanding XOR equation found on signal t2_u_h1_count_h_0.T
  Information: Expanding XOR equation found on signal t2_u_h1_count_h_0.Tbar
  Information: Generating both D & T register equations for signal t2_u_h1_count_h_1.D
  Information: Expanding XOR equation found on signal t2_u_h1_count_h_1.T
  Information: Expanding XOR equation found on signal t2_u_h1_count_h_1.Tbar
  Information: Generating both D & T register equations for signal t2_u_h1_count_h_2.D
  Information: Expanding XOR equation found on signal t2_u_h1_count_h_2.T
  Information: Expanding XOR equation found on signal t2_u_h1_count_h_2.Tbar
  Information: Generating both D & T register equations for signal t1_y_0.D
  Information: Expanding XOR equation found on signal t1_y_0.T
  Information: Expanding XOR equation found on signal t1_y_0.Tbar
  Information: Generating both D & T register equations for signal t1_y_1.D
  Information: Expanding XOR equation found on signal t1_y_1.T
  Information: Expanding XOR equation found on signal t1_y_1.Tbar
  Information: Generating both D & T register equations for signal t1_y_2.D
  Information: Expanding XOR equation found on signal t1_y_2.T
  Information: Expanding XOR equation found on signal t1_y_2.Tbar
  Information: Generating both D & T register equations for signal t1_y_3.D
  Information: Expanding XOR equation found on signal t1_y_3.T
  Information: Expanding XOR equation found on signal t1_y_3.Tbar
  Information: Generating both D & T register equations for signal t1_u1_count_0.D
  Information: Expanding XOR equation found on signal t1_u1_count_0.T
  Information: Expanding XOR equation found on signal t1_u1_count_0.Tbar
  Information: Generating both D & T register equations for signal t1_u1_count_1.D
  Information: Expanding XOR equation found on signal t1_u1_count_1.T
  Information: Expanding XOR equation found on signal t1_u1_count_1.Tbar
  Information: Optimizing logic without changing polarity for signals:
         t2_y_h_0.T t2_y_h_1.T t2_y_h_2.T t2_y_h_3.T t2_u_h1_count_h_0.T
         t2_u_h1_count_h_1.T t2_u_h1_count_h_2.T t1_y_0.T t1_y_1.T t1_y_2.T
         t1_y_3.T t1_u1_count_0.T t1_u1_count_1.T

  Information: Optimizing logic and selecting Active High output for signals:
         t2_y_h_0.Tbar t2_y_h_0.C t2_y_h_1.Tbar t2_y_h_1.C t2_y_h_2.Tbar
         t2_y_h_2.C t2_y_h_3.Tbar t2_y_h_3.C t2_u_h1_count_h_0.Tbar
         t2_u_h1_count_h_0.C t2_u_h1_count_h_1.Tbar t2_u_h1_count_h_1.C
         t2_u_h1_count_h_2.Tbar t2_u_h1_count_h_2.C t1_y_0.Tbar t1_y_0.C
         t1_y_1.Tbar t1_y_1.C t1_y_2.Tbar t1_y_2.C t1_y_3.Tbar t1_y_3.C
         t1_u1_count_0.Tbar t1_u1_count_0.C t1_u1_count_1.Tbar t1_u1_count_1.C

  Information: Optimizing logic using best output polarity for signals:
         t2_y_h_0.D t2_y_h_1.D t2_y_h_2.D t2_y_h_3.D t2_u_h1_count_h_0.D
         t2_u_h1_count_h_1.D t2_u_h1_count_h_2.D t1_y_0.D t1_y_1.D t1_y_2.D
         t1_y_3.D t1_u1_count_0.D t1_u1_count_1.D arm_in_0 arm_in_1 arm_in_2
         arm_in_3



Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       MINOPT.EXE     17/JUL/96    [v3.22 ] 4 IR x66

LOGIC MINIMIZATION         (15:41:36)

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    17/JUL/96    [v3.22 ] 4 IR x66

OPTIMIZATION OPTIONS       (15:41:38)

Messages:
  Information: Synthesizing XOR logic for signal t1_u1_count_1.D.
  Information: Selecting T register equation as minimal for signal t1_u1_count_1
  Information: Converting register type T -> D found on signal t1_u1_count_1
  Information: Synthesizing XOR logic for signal t1_u1_count_0.D.
  Information: Selecting T register equation as minimal for signal t1_u1_count_0
  Information: Converting register type T -> D found on signal t1_u1_count_0
  Information: Synthesizing XOR logic for signal t1_y_3.D.
  Information: Selecting D register equation as minimal for signal t1_y_3
  Information: Synthesizing XOR logic for signal t1_y_2.D.
  Information: Selecting D register equation as minimal for signal t1_y_2
  Information: Synthesizing XOR logic for signal t1_y_1.D.
  Information: Selecting D register equation as minimal for signal t1_y_1
  Information: Synthesizing XOR logic for signal t1_y_0.D.
  Information: Selecting D register equation as minimal for signal t1_y_0
  Information: Synthesizing XOR logic for signal t2_u_h1_count_h_2.D.
  Information: Selecting T register equation as minimal for signal t2_u_h1_count_h_2
  Information: Converting register type T -> D found on signal t2_u_h1_count_h_2
  Information: Synthesizing XOR logic for signal t2_u_h1_count_h_1.D.
  Information: Selecting T register equation as minimal for signal t2_u_h1_count_h_1
  Information: Converting register type T -> D found on signal t2_u_h1_count_h_1
  Information: Synthesizing XOR logic for signal t2_u_h1_count_h_0.D.
  Information: Selecting T register equation as minimal for signal t2_u_h1_count_h_0
  Information: Converting register type T -> D found on signal t2_u_h1_count_h_0
  Information: Synthesizing XOR logic for signal t2_y_h_3.D.
  Information: Selecting D register equation as minimal for signal t2_y_h_3
  Information: Synthesizing XOR logic for signal t2_y_h_2.D.
  Information: Selecting D register equation as minimal for signal t2_y_h_2
  Information: Synthesizing XOR logic for signal t2_y_h_1.D.
  Information: Selecting D register equation as minimal for signal t2_y_h_1
  Information: Synthesizing XOR logic for signal t2_y_h_0.D.
  Information: Selecting D register equation as minimal for signal t2_y_h_0


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        MAX2JED.EXE    17/JUL/96    [v3.22 ] 4 IR x66

DESIGN EQUATIONS           (15:41:39)


    arm_in_3 =
          t2_y_h_3.Q * /step_sel 
        + step_sel * t1_y_3.Q 

    arm_in_2 =
          t2_y_h_2.Q * /step_sel 
        + step_sel * t1_y_2.Q 

    arm_in_1 =
          t2_y_h_1.Q * /step_sel 
        + step_sel * t1_y_1.Q 

    arm_in_0 =
          t2_y_h_0.Q * /step_sel 
        + step_sel * t1_y_0.Q 

    t1_u1_count_1.D.X2 =
          t1_u1_count_1.Q 

    t1_u1_count_1.D.X1 =
          step_sel * t1_u1_count_0.Q * /stop 

    t1_u1_count_1.C =
          clk 

    t1_u1_count_0.D.X2 =
          t1_u1_count_0.Q 

    t1_u1_count_0.D.X1 =
          step_sel * /stop 

    t1_u1_count_0.C =
          clk 

    t1_y_3.D.X2 =
          /dir_sel * /t1_u1_count_1.Q * /t1_u1_count_0.Q 

    t1_y_3.D.X1 =
          dir_sel * t1_u1_count_1.Q 
        + t1_u1_count_1.Q * t1_u1_count_0.Q 

    t1_y_3.C =
          clk 

    t1_y_2.D.X2 =
          dir_sel * t1_u1_count_1.Q * /t1_u1_count_0.Q 

    t1_y_2.D.X1 =
          /dir_sel * /t1_u1_count_1.Q 
        + /t1_u1_count_1.Q * t1_u1_count_0.Q 

    t1_y_2.C =
          clk 

    t1_y_1.D.X2 =
          /dir_sel * t1_u1_count_1.Q * /t1_u1_count_0.Q 

    t1_y_1.D.X1 =
          dir_sel * /t1_u1_count_1.Q 
        + /t1_u1_count_1.Q * t1_u1_count_0.Q 

    t1_y_1.C =
          clk 

    t1_y_0.D.X2 =
          dir_sel * /t1_u1_count_1.Q * /t1_u1_count_0.Q 

    t1_y_0.D.X1 =
          /dir_sel * t1_u1_count_1.Q 
        + t1_u1_count_1.Q * t1_u1_count_0.Q 

    t1_y_0.C =
          clk 

    t2_u_h1_count_h_2.D.X2 =
          t2_u_h1_count_h_2.Q 

    t2_u_h1_count_h_2.D.X1 =
          t2_u_h1_count_h_1.Q * t2_u_h1_count_h_0.Q * /step_sel * /stop 

    t2_u_h1_count_h_2.C =
          clk 

    t2_u_h1_count_h_1.D.X2 =
          t2_u_h1_count_h_1.Q 

    t2_u_h1_count_h_1.D.X1 =
          t2_u_h1_count_h_0.Q * /step_sel * /stop 

    t2_u_h1_count_h_1.C =
          clk 

    t2_u_h1_count_h_0.D.X2 =
          t2_u_h1_count_h_0.Q 

    t2_u_h1_count_h_0.D.X1 =
          /step_sel * /stop 

    t2_u_h1_count_h_0.C =
          clk 

    t2_y_h_3.D.X2 =
          /t2_u_h1_count_h_2.Q * /t2_u_h1_count_h_1.Q * 
          /t2_u_h1_count_h_0.Q * /dir_sel 

    t2_y_h_3.D.X1 =
          t2_u_h1_count_h_2.Q * /t2_u_h1_count_h_0.Q * dir_sel 
        + t2_u_h1_count_h_2.Q * /t2_u_h1_count_h_1.Q * dir_sel 
        + t2_u_h1_count_h_2.Q * t2_u_h1_count_h_1.Q * /dir_sel 

    t2_y_h_3.C =
          clk 

    t2_y_h_2.D.X2 =
          t2_u_h1_count_h_2.Q * /t2_u_h1_count_h_1.Q * 
          /t2_u_h1_count_h_0.Q * dir_sel 

    t2_y_h_2.D.X1 =
          /t2_u_h1_count_h_2.Q * /t2_u_h1_count_h_0.Q * /dir_sel 
        + /t2_u_h1_count_h_2.Q * /t2_u_h1_count_h_1.Q * /dir_sel 
        + /t2_u_h1_count_h_2.Q * t2_u_h1_count_h_1.Q * dir_sel 

    t2_y_h_2.C =
          clk 

    t2_y_h_1.D.X2 =
          t2_u_h1_count_h_2.Q * /t2_u_h1_count_h_1.Q * 
          /t2_u_h1_count_h_0.Q * /dir_sel 

    t2_y_h_1.D.X1 =
          /t2_u_h1_count_h_2.Q * /t2_u_h1_count_h_0.Q * dir_sel 
        + /t2_u_h1_count_h_2.Q * /t2_u_h1_count_h_1.Q * dir_sel 
        + /t2_u_h1_count_h_2.Q * t2_u_h1_count_h_1.Q * /dir_sel 

    t2_y_h_1.C =
          clk 

    t2_y_h_0.D.X2 =
          /t2_u_h1_count_h_2.Q * /t2_u_h1_count_h_1.Q * 
          /t2_u_h1_count_h_0.Q * dir_sel 

    t2_y_h_0.D.X1 =
          t2_u_h1_count_h_2.Q * /t2_u_h1_count_h_0.Q * /dir_sel 
        + t2_u_h1_count_h_2.Q * /t2_u_h1_count_h_1.Q * /dir_sel 
        + t2_u_h1_count_h_2.Q * t2_u_h1_count_h_1.Q * dir_sel 

    t2_y_h_0.C =
          clk 


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        MAX2JED.EXE    17/JUL/96    [v3.22 ] 4 IR x66

DESIGN RULE CHECK          (15:41:39)

Messages:
                 None.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        MAX2JED.EXE    17/JUL/96    [v3.22 ] 4 IR x66

PARTITION LOGIC            (15:41:39)

Messages:
  Information: Initializing Logic Array Block (LAB) structures.
  Warning: Revision (V3.22) of data file C:\warp\bin\c34x.fit
           is not being used.
  Information: Processing Global Clock Pin.
  Information: Assigning fixed logic to LABs.
  Information: Checking expander usage for pre-placed signals.
  Information: Separating expander logic.
  Information: Forming input seeds.
  Information: Validating LAB's with pre-placed signals.
  Information: Locating best global input signals.
  Information: Separating output logic set to GND/VCC.
  Information: Assigning initializing equations to empty LABs.
  Information: Separating output node logic.
  Information: Assigning floating outputs to LABs.
  Information: Compacting LAB interconnect.
  ..+..+..........


Summary:
                 Error Count = 0      Warning Count = 1

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        MAX2JED.EXE    17/JUL/96    [v3.22 ] 4 IR x66

DESIGN SIGNAL PLACEMENT    (15:41:40)

Messages:
  Information: Fitting signals to LAB 1.
  Information: Fitting signals to LAB 2.
  Information: Fitting signals to LAB 3.
  Information: Fitting signals to LAB 4.
  Information: Fitting signals to LAB 5.
  Information: Fitting signals to LAB 6.
  Information: Fitting signals to LAB 7.
  Information: Fitting signals to LAB 8.
  Information: Fitting signals to LAB 9.
  Information: Fitting signals to LAB 10.
  Information: Fitting signals to LAB 11.
  Information: Fitting signals to LAB 12.


Summary:
                 Error Count = 0      Warning Count = 1

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        MAX2JED.EXE    17/JUL/96    [v3.22 ] 4 IR x66

LAB 1 SIGNAL PLACEMENT  (15:41:41)

Messages:


                                  LAB 1
                 __________________________________________
       not used *|41|                  t2_u_h1_coun.. =|11|* not used       
       not used *|42|                                 +|  |+                
       not used *|43|                                 +|  |+                
           stop =|44|                                  |  |                 
       step_sel =|83|                  t2_u_h1_coun.. =|10|* not used       
        dir_sel =|84|                                 +|  |+                
            clk =| 1|                                 +|  |+                
       not used *| 2|                                  |  |                 
                 |  |= >t2_u_h1_cou..        t2_y_h_3 =| 9|* not used       
                 |  |> not used:226                   +|  |+                
                 |  |> not used:227                   +|  |+                
                 |  |> not used:228                    |  |                 
                 |  |> not used:229          t2_y_h_2 =| 8|* not used       
                 |  |> not used:230                   +|  |+                
                 |  |> not used:231                   +|  |+                
                 |  |> not used:232                    |  |                 
                 |  |> not used:233          t2_y_h_1 =| 7|* not used       
                 |  |> not used:234                   +|  |+                
                 |  |> not used:235                   +|  |+                
                 |  |> not used:236                    |  |                 
                 |  |> not used:237          t2_y_h_0 =| 6|* not used       
                 |  |> not used:238                   +|  |+                
                 |  |> not used:239                   +|  |+                
                 |  |> not used:240                    |  |                 
                 |  |> not used:241       not used:91 *| 5|* not used       
                 |  |> not used:242                   +|  |+                
                 |  |> not used:243                   +|  |+                
                 |  |> not used:244                    |  |                 
                 |  |> not used:245       not used:92 *| 4|* not used       
                 |  |> not used:246                   +|  |+                
                 |  |> not used:247                   +|  |+                
                 |  |> not used:248                    |  |                 
                 __________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | Dedicated Inputs   |    3  |    7  |
                 | Clock/Inputs       |    1  |    1  |
                 | I/O Macrocells     |    0  |    8  |
                 | Buried Macrocells  |    6  |    8  |
                 | Expander Terms     |    0  |   32  |
                 | PIA Input Connects |    1  |   24  |
                 ______________________________________
                                          11  /   80   = 13  %


----------------------------------------------------------------------------
PLD Compiler Software:        MAX2JED.EXE    17/JUL/96    [v3.22 ] 4 IR x66

LAB 2 SIGNAL PLACEMENT  (15:41:41)

Messages:


                                  LAB 2
                 __________________________________________
       not used *|41|                     not used:94 *|12|* not used       
       not used *|42|                                 +|  |+                
       not used *|43|                                 +|  |+                
           stop =|44|                     not used:95 *|13|* not used       
       step_sel =|83|                                 +|  |+                
        dir_sel =|84|                                 +|  |+                
            clk =| 1|                     not used:96 *|14|* not used       
       not used *| 2|                                 +|  |+                
                 |  |                                 +|  |+                
                 |  |                     not used:97 *|15|* not used       
                 |  |                                 +|  |+                
                 |  |                                 +|  |+                
                 |  |> not used:249       not used:98 *|  |                 
                 |  |> not used:250                   +|  |                 
                 |  |> not used:251                   +|  |                 
                 |  |> not used:252       not used:99 *|  |                 
                 |  |> not used:253                   +|  |                 
                 |  |> not used:254                   +|  |                 
                 |  |> not used:255      not used:100 *|  |                 
                 |  |> not used:256                   +|  |                 
                 |  |> not used:257                   +|  |                 
                 |  |> not used:258      not used:101 *|  |                 
                 |  |> not used:259                   +|  |                 
                 |  |> not used:260                   +|  |                 
                 |  |> not used:261      not used:102 *|  |                 
                 |  |> not used:262                   +|  |                 
                 |  |> not used:263                   +|  |                 
                 |  |> not used:264      not used:103 *|  |                 
                 |  |> not used:265                   +|  |                 
                 |  |> not used:266                   +|  |                 
                 |  |> not used:267      not used:104 *|  |                 
                 |  |> not used:268                   +|  |                 
                 |  |> not used:269                   +|  |                 
                 |  |> not used:270      not used:105 *|  |                 
                 |  |> not used:271                   +|  |                 
                 |  |> not used:272                   +|  |                 
                 __________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | Dedicated Inputs   |    3  |    7  |
                 | Clock/Inputs       |    1  |    1  |
                 | I/O Macrocells     |    0  |    4  |
                 | Buried Macrocells  |    0  |   12  |
                 | Expander Terms     |    0  |   32  |
                 | PIA Input Connects |    0  |   24  |
                 ______________________________________
                                           4  /   80   = 5   %


----------------------------------------------------------------------------
PLD Compiler Software:        MAX2JED.EXE    17/JUL/96    [v3.22 ] 4 IR x66

LAB 3 SIGNAL PLACEMENT  (15:41:41)

Messages:


                                  LAB 3
                 __________________________________________
       not used *|41|                    not used:107 *|21|* not used       
       not used *|42|                                 +|  |+                
       not used *|43|                                 +|  |+                
           stop =|44|                    not used:108 *|20|* not used       
       step_sel =|83|                                 +|  |+                
        dir_sel =|84|                                 +|  |+                
            clk =| 1|                    not used:109 *|17|* not used       
       not used *| 2|                                 +|  |+                
                 |  |                                 +|  |+                
                 |  |                    not used:110 *|16|= arm_in_3       
                 |  |                                 +|  |+                
                 |  |                                 +|  |+                
                 |  |= >t2_y_h_3         not used:111 *|  |                 
                 |  |= >t1_y_3                        +|  |                 
                 |  |> not used:275                   +|  |                 
                 |  |> not used:276      not used:112 *|  |                 
                 |  |> not used:277                   +|  |                 
                 |  |> not used:278                   +|  |                 
                 |  |> not used:279      not used:113 *|  |                 
                 |  |> not used:280                   +|  |                 
                 |  |> not used:281                   +|  |                 
                 |  |> not used:282      not used:114 *|  |                 
                 |  |> not used:283                   +|  |                 
                 |  |> not used:284                   +|  |                 
                 |  |> not used:285      not used:115 *|  |                 
                 |  |> not used:286                   +|  |                 
                 |  |> not used:287                   +|  |                 
                 |  |> not used:288      not used:116 *|  |                 
                 |  |> not used:289                   +|  |                 
                 |  |> not used:290                   +|  |                 
                 |  |> not used:291      not used:117 *|  |                 
                 |  |> not used:292                   +|  |                 
                 |  |> not used:293                   +|  |                 
                 |  |> not used:294      not used:118 *|  |                 
                 |  |> not used:295                   +|  |                 
                 |  |> not used:296                   +|  |                 
                 __________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | Dedicated Inputs   |    3  |    7  |
                 | Clock/Inputs       |    1  |    1  |
                 | I/O Macrocells     |    1  |    4  |
                 | Buried Macrocells  |    0  |   12  |
                 | Expander Terms     |    0  |   32  |
                 | PIA Input Connects |    2  |   24  |
                 ______________________________________
                                           7  /   80   = 8   %


----------------------------------------------------------------------------
PLD Compiler Software:        MAX2JED.EXE    17/JUL/96    [v3.22 ] 4 IR x66

LAB 4 SIGNAL PLACEMENT  (15:41:41)

Messages:


                                  LAB 4
                 __________________________________________
       not used *|41|                    not used:120 *|22|= arm_in_2       
       not used *|42|                                 +|  |+                
       not used *|43|                                 +|  |+                
           stop =|44|                    not used:121 *|23|* not used       
       step_sel =|83|                                 +|  |+                
        dir_sel =|84|                                 +|  |+                
            clk =| 1|                    not used:122 *|25|* not used       
       not used *| 2|                                 +|  |+                
                 |  |                                 +|  |+                
                 |  |                    not used:123 *|26|* not used       
                 |  |                                 +|  |+                
                 |  |                                 +|  |+                
                 |  |= >t2_y_h_2         not used:124 *|  |                 
                 |  |= >t1_y_2                        +|  |                 
                 |  |> not used:299                   +|  |                 
                 |  |> not used:300      not used:125 *|  |                 
                 |  |> not used:301                   +|  |                 
                 |  |> not used:302                   +|  |                 
                 |  |> not used:303      not used:126 *|  |                 
                 |  |> not used:304                   +|  |                 
                 |  |> not used:305                   +|  |                 
                 |  |> not used:306      not used:127 *|  |                 
                 |  |> not used:307                   +|  |                 
                 |  |> not used:308                   +|  |                 
                 |  |> not used:309      not used:128 *|  |                 
                 |  |> not used:310                   +|  |                 
                 |  |> not used:311                   +|  |                 
                 |  |> not used:312      not used:129 *|  |                 
                 |  |> not used:313                   +|  |                 
                 |  |> not used:314                   +|  |                 
                 |  |> not used:315      not used:130 *|  |                 
                 |  |> not used:316                   +|  |                 
                 |  |> not used:317                   +|  |                 
                 |  |> not used:318      not used:131 *|  |                 
                 |  |> not used:319                   +|  |                 
                 |  |> not used:320                   +|  |                 
                 __________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | Dedicated Inputs   |    3  |    7  |
                 | Clock/Inputs       |    1  |    1  |
                 | I/O Macrocells     |    1  |    4  |
                 | Buried Macrocells  |    0  |   12  |
                 | Expander Terms     |    0  |   32  |
                 | PIA Input Connects |    2  |   24  |
                 ______________________________________
                                           7  /   80   = 8   %


----------------------------------------------------------------------------
PLD Compiler Software:        MAX2JED.EXE    17/JUL/96    [v3.22 ] 4 IR x66

LAB 5 SIGNAL PLACEMENT  (15:41:41)

Messages:


                                  LAB 5
                 __________________________________________
       not used *|41|                    not used:133 *|30|* not used       
       not used *|42|                                 +|  |+                
       not used *|43|                                 +|  |+                
           stop =|44|                    not used:134 *|29|* not used       
       step_sel =|83|                                 +|  |+                
        dir_sel =|84|                                 +|  |+                
            clk =| 1|                    not used:135 *|28|* not used       
       not used *| 2|                                 +|  |+                
                 |  |                                 +|  |+                
                 |  |                    not used:136 *|27|= arm_in_1       
                 |  |                                 +|  |+                
                 |  |                                 +|  |+                
                 |  |= >t2_y_h_1         not used:137 *|  |                 
                 |  |= >t1_y_1                        +|  |                 
                 |  |> not used:323                   +|  |                 
                 |  |> not used:324      not used:138 *|  |                 
                 |  |> not used:325                   +|  |                 
                 |  |> not used:326                   +|  |                 
                 |  |> not used:327      not used:139 *|  |                 
                 |  |> not used:328                   +|  |                 
                 |  |> not used:329                   +|  |                 
                 |  |> not used:330      not used:140 *|  |                 
                 |  |> not used:331                   +|  |                 
                 |  |> not used:332                   +|  |                 
                 |  |> not used:333      not used:141 *|  |                 
                 |  |> not used:334                   +|  |                 
                 |  |> not used:335                   +|  |                 
                 |  |> not used:336      not used:142 *|  |                 
                 |  |> not used:337                   +|  |                 
                 |  |> not used:338                   +|  |                 
                 |  |> not used:339      not used:143 *|  |                 
                 |  |> not used:340                   +|  |                 
                 |  |> not used:341                   +|  |                 
                 |  |> not used:342      not used:144 *|  |                 
                 |  |> not used:343                   +|  |                 
                 |  |> not used:344                   +|  |                 
                 __________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | Dedicated Inputs   |    3  |    7  |
                 | Clock/Inputs       |    1  |    1  |
                 | I/O Macrocells     |    1  |    4  |
                 | Buried Macrocells  |    0  |   12  |
                 | Expander Terms     |    0  |   32  |
                 | PIA Input Connects |    2  |   24  |
                 ______________________________________
                                           7  /   80   = 8   %


----------------------------------------------------------------------------
PLD Compiler Software:        MAX2JED.EXE    17/JUL/96    [v3.22 ] 4 IR x66

LAB 6 SIGNAL PLACEMENT  (15:41:41)

Messages:


                                  LAB 6
                 __________________________________________
       not used *|41|                    not used:146 *|31|= arm_in_0       
       not used *|42|                                 +|  |+                
       not used *|43|                                 +|  |+                
           stop =|44|                                  |  |                 
       step_sel =|83|                    not used:147 *|32|* not used       
        dir_sel =|84|                                 +|  |+                
            clk =| 1|                                 +|  |+                
       not used *| 2|                                  |  |                 
                 |  |= >t2_y_h_0         not used:148 *|33|* not used       
                 |  |= >t1_y_0                        +|  |+                
                 |  |> not used:347                   +|  |+                
                 |  |> not used:348                    |  |                 
                 |  |> not used:349      not used:149 *|34|* not used       
                 |  |> not used:350                   +|  |+                
                 |  |> not used:351                   +|  |+                
                 |  |> not used:352                    |  |                 
                 |  |> not used:353      not used:150 *|35|* not used       
                 |  |> not used:354                   +|  |+                
                 |  |> not used:355                   +|  |+                
                 |  |> not used:356                    |  |                 
                 |  |> not used:357      not used:151 *|36|* not used       
                 |  |> not used:358                   +|  |+                
                 |  |> not used:359                   +|  |+                
                 |  |> not used:360                    |  |                 
                 |  |> not used:361      not used:152 *|37|* not used       
                 |  |> not used:362                   +|  |+                
                 |  |> not used:363                   +|  |+                
                 |  |> not used:364                    |  |                 
                 |  |> not used:365      not used:153 *|38|* not used       
                 |  |> not used:366                   +|  |+                
                 |  |> not used:367                   +|  |+                
                 |  |> not used:368                    |  |                 
                 __________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | Dedicated Inputs   |    3  |    7  |
                 | Clock/Inputs       |    1  |    1  |
                 | I/O Macrocells     |    1  |    8  |
                 | Buried Macrocells  |    0  |    8  |
                 | Expander Terms     |    0  |   32  |
                 | PIA Input Connects |    2  |   24  |
                 ______________________________________
                                           7  /   80   = 8   %


----------------------------------------------------------------------------
PLD Compiler Software:        MAX2JED.EXE    17/JUL/96    [v3.22 ] 4 IR x66

LAB 7 SIGNAL PLACEMENT  (15:41:41)

Messages:


                                  LAB 7
                 __________________________________________
       not used *|41|                   t1_u1_count_0 =|53|* not used       
       not used *|42|                                 +|  |+                
       not used *|43|                                 +|  |+                
           stop =|44|                                  |  |                 
       step_sel =|83|                    not used:156 *|52|* not used       
        dir_sel =|84|                                 +|  |+                
            clk =| 1|                                 +|  |+                
       not used *| 2|                                  |  |                 
                 |  |> not used:369      not used:157 *|51|* not used       
                 |  |> not used:370                   +|  |+                
                 |  |> not used:371                   +|  |+                
                 |  |> not used:372                    |  |                 
                 |  |> not used:373      not used:158 *|50|* not used       
                 |  |> not used:374                   +|  |+                
                 |  |> not used:375                   +|  |+                
                 |  |> not used:376                    |  |                 
                 |  |> not used:377      not used:159 *|49|* not used       
                 |  |> not used:378                   +|  |+                
                 |  |> not used:379                   +|  |+                
                 |  |> not used:380                    |  |                 
                 |  |> not used:381      not used:160 *|48|* not used       
                 |  |> not used:382                   +|  |+                
                 |  |> not used:383                   +|  |+                
                 |  |> not used:384                    |  |                 
                 |  |> not used:385      not used:161 *|47|* not used       
                 |  |> not used:386                   +|  |+                
                 |  |> not used:387                   +|  |+                
                 |  |> not used:388                    |  |                 
                 |  |> not used:389      not used:162 *|46|* not used       
                 |  |> not used:390                   +|  |+                
                 |  |> not used:391                   +|  |+                
                 |  |> not used:392                    |  |                 
                 __________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | Dedicated Inputs   |    3  |    7  |
                 | Clock/Inputs       |    1  |    1  |
                 | I/O Macrocells     |    0  |    8  |
                 | Buried Macrocells  |    1  |    8  |
                 | Expander Terms     |    0  |   32  |
                 | PIA Input Connects |    0  |   24  |
                 ______________________________________
                                           5  /   80   = 6   %


----------------------------------------------------------------------------
PLD Compiler Software:        MAX2JED.EXE    17/JUL/96    [v3.22 ] 4 IR x66

LAB 8 SIGNAL PLACEMENT  (15:41:41)

Messages:


                                  LAB 8
                 __________________________________________
       not used *|41|                  t2_u_h1_coun.. =|54|* not used       
       not used *|42|                                 +|  |+                
       not used *|43|                                 +|  |+                
           stop =|44|                    not used:165 *|55|* not used       
       step_sel =|83|                                 +|  |+                
        dir_sel =|84|                                 +|  |+                
            clk =| 1|                    not used:166 *|56|* not used       
       not used *| 2|                                 +|  |+                
                 |  |                                 +|  |+                
                 |  |                    not used:167 *|57|* not used       
                 |  |                                 +|  |+                
                 |  |                                 +|  |+                
                 |  |> not used:393      not used:168 *|  |                 
                 |  |> not used:394                   +|  |                 
                 |  |> not used:395                   +|  |                 
                 |  |> not used:396      not used:169 *|  |                 
                 |  |> not used:397                   +|  |                 
                 |  |> not used:398                   +|  |                 
                 |  |> not used:399      not used:170 *|  |                 
                 |  |> not used:400                   +|  |                 
                 |  |> not used:401                   +|  |                 
                 |  |> not used:402      not used:171 *|  |                 
                 |  |> not used:403                   +|  |                 
                 |  |> not used:404                   +|  |                 
                 |  |> not used:405      not used:172 *|  |                 
                 |  |> not used:406                   +|  |                 
                 |  |> not used:407                   +|  |                 
                 |  |> not used:408      not used:173 *|  |                 
                 |  |> not used:409                   +|  |                 
                 |  |> not used:410                   +|  |                 
                 |  |> not used:411      not used:174 *|  |                 
                 |  |> not used:412                   +|  |                 
                 |  |> not used:413                   +|  |                 
                 |  |> not used:414      not used:175 *|  |                 
                 |  |> not used:415                   +|  |                 
                 |  |> not used:416                   +|  |                 
                 __________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | Dedicated Inputs   |    3  |    7  |
                 | Clock/Inputs       |    1  |    1  |
                 | I/O Macrocells     |    0  |    4  |
                 | Buried Macrocells  |    1  |   12  |
                 | Expander Terms     |    0  |   32  |
                 | PIA Input Connects |    0  |   24  |
                 ______________________________________
                                           5  /   80   = 6   %


----------------------------------------------------------------------------
PLD Compiler Software:        MAX2JED.EXE    17/JUL/96    [v3.22 ] 4 IR x66

LAB 9 SIGNAL PLACEMENT  (15:41:41)

Messages:


                                  LAB 9
                 __________________________________________
       not used *|41|                    not used:177 *|63|* not used       
       not used *|42|                                 +|  |+                
       not used *|43|                                 +|  |+                
           stop =|44|                    not used:178 *|62|* not used       
       step_sel =|83|                                 +|  |+                
        dir_sel =|84|                                 +|  |+                
            clk =| 1|                    not used:179 *|59|* not used       
       not used *| 2|                                 +|  |+                
                 |  |                                 +|  |+                
                 |  |                    not used:180 *|58|* not used       
                 |  |                                 +|  |+                
                 |  |                                 +|  |+                
                 |  |> not used:417      not used:181 *|  |                 
                 |  |> not used:418                   +|  |                 
                 |  |> not used:419                   +|  |                 
                 |  |> not used:420      not used:182 *|  |                 
                 |  |> not used:421                   +|  |                 
                 |  |> not used:422                   +|  |                 
                 |  |> not used:423      not used:183 *|  |                 
                 |  |> not used:424                   +|  |                 
                 |  |> not used:425                   +|  |                 
                 |  |> not used:426      not used:184 *|  |                 
                 |  |> not used:427                   +|  |                 
                 |  |> not used:428                   +|  |                 
                 |  |> not used:429      not used:185 *|  |                 
                 |  |> not used:430                   +|  |                 
                 |  |> not used:431                   +|  |                 
                 |  |> not used:432      not used:186 *|  |                 
                 |  |> not used:433                   +|  |                 
                 |  |> not used:434                   +|  |                 
                 |  |> not used:435      not used:187 *|  |                 
                 |  |> not used:436                   +|  |                 
                 |  |> not used:437                   +|  |                 
                 |  |> not used:438      not used:188 *|  |                 
                 |  |> not used:439                   +|  |                 
                 |  |> not used:440                   +|  |                 
                 __________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | Dedicated Inputs   |    3  |    7  |
                 | Clock/Inputs       |    1  |    1  |
                 | I/O Macrocells     |    0  |    4  |
                 | Buried Macrocells  |    0  |   12  |
                 | Expander Terms     |    0  |   32  |
                 | PIA Input Connects |    0  |   24  |
                 ______________________________________
                                           4  /   80   = 5   %


----------------------------------------------------------------------------
PLD Compiler Software:        MAX2JED.EXE    17/JUL/96    [v3.22 ] 4 IR x66

LAB 10 SIGNAL PLACEMENT  (15:41:41)

Messages:


                                 LAB 10
                 __________________________________________
       not used *|41|                    not used:190 *|64|* not used       
       not used *|42|                                 +|  |+                
       not used *|43|                                 +|  |+                
           stop =|44|                    not used:191 *|65|* not used       
       step_sel =|83|                                 +|  |+                
        dir_sel =|84|                                 +|  |+                
            clk =| 1|                    not used:192 *|67|* not used       
       not used *| 2|                                 +|  |+                
                 |  |                                 +|  |+                
                 |  |                    not used:193 *|68|* not used       
                 |  |                                 +|  |+                
                 |  |                                 +|  |+                
                 |  |> not used:441      not used:194 *|  |                 
                 |  |> not used:442                   +|  |                 
                 |  |> not used:443                   +|  |                 
                 |  |> not used:444      not used:195 *|  |                 
                 |  |> not used:445                   +|  |                 
                 |  |> not used:446                   +|  |                 
                 |  |> not used:447      not used:196 *|  |                 
                 |  |> not used:448                   +|  |                 
                 |  |> not used:449                   +|  |                 
                 |  |> not used:450      not used:197 *|  |                 
                 |  |> not used:451                   +|  |                 
                 |  |> not used:452                   +|  |                 
                 |  |> not used:453      not used:198 *|  |                 
                 |  |> not used:454                   +|  |                 
                 |  |> not used:455                   +|  |                 
                 |  |> not used:456      not used:199 *|  |                 
                 |  |> not used:457                   +|  |                 
                 |  |> not used:458                   +|  |                 
                 |  |> not used:459      not used:200 *|  |                 
                 |  |> not used:460                   +|  |                 
                 |  |> not used:461                   +|  |                 
                 |  |> not used:462      not used:201 *|  |                 
                 |  |> not used:463                   +|  |                 
                 |  |> not used:464                   +|  |                 
                 __________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | Dedicated Inputs   |    3  |    7  |
                 | Clock/Inputs       |    1  |    1  |
                 | I/O Macrocells     |    0  |    4  |
                 | Buried Macrocells  |    0  |   12  |
                 | Expander Terms     |    0  |   32  |
                 | PIA Input Connects |    0  |   24  |
                 ______________________________________
                                           4  /   80   = 5   %


----------------------------------------------------------------------------
PLD Compiler Software:        MAX2JED.EXE    17/JUL/96    [v3.22 ] 4 IR x66

LAB 11 SIGNAL PLACEMENT  (15:41:41)

Messages:


                                 LAB 11
                 __________________________________________
       not used *|41|                    not used:203 *|72|* not used       
       not used *|42|                                 +|  |+                
       not used *|43|                                 +|  |+                
           stop =|44|                    not used:204 *|71|* not used       
       step_sel =|83|                                 +|  |+                
        dir_sel =|84|                                 +|  |+                
            clk =| 1|                    not used:205 *|70|* not used       
       not used *| 2|                                 +|  |+                
                 |  |                                 +|  |+                
                 |  |                    not used:206 *|69|* not used       
                 |  |                                 +|  |+                
                 |  |                                 +|  |+                
                 |  |> not used:465      not used:207 *|  |                 
                 |  |> not used:466                   +|  |                 
                 |  |> not used:467                   +|  |                 
                 |  |> not used:468      not used:208 *|  |                 
                 |  |> not used:469                   +|  |                 
                 |  |> not used:470                   +|  |                 
                 |  |> not used:471      not used:209 *|  |                 
                 |  |> not used:472                   +|  |                 
                 |  |> not used:473                   +|  |                 
                 |  |> not used:474      not used:210 *|  |                 
                 |  |> not used:475                   +|  |                 
                 |  |> not used:476                   +|  |                 
                 |  |> not used:477      not used:211 *|  |                 
                 |  |> not used:478                   +|  |                 
                 |  |> not used:479                   +|  |                 
                 |  |> not used:480      not used:212 *|  |                 
                 |  |> not used:481                   +|  |                 
                 |  |> not used:482                   +|  |                 
                 |  |> not used:483      not used:213 *|  |                 
                 |  |> not used:484                   +|  |                 
                 |  |> not used:485                   +|  |                 
                 |  |> not used:486      not used:214 *|  |                 
                 |  |> not used:487                   +|  |                 
                 |  |> not used:488                   +|  |                 
                 __________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | Dedicated Inputs   |    3  |    7  |
                 | Clock/Inputs       |    1  |    1  |
                 | I/O Macrocells     |    0  |    4  |
                 | Buried Macrocells  |    0  |   12  |
                 | Expander Terms     |    0  |   32  |
                 | PIA Input Connects |    0  |   24  |
                 ______________________________________
                                           4  /   80   = 5   %


----------------------------------------------------------------------------
PLD Compiler Software:        MAX2JED.EXE    17/JUL/96    [v3.22 ] 4 IR x66

LAB 12 SIGNAL PLACEMENT  (15:41:41)

Messages:


                                 LAB 12
                 __________________________________________
       not used *|41|                          t1_y_2 =|73|* not used       
       not used *|42|                                 +|  |+                
       not used *|43|                                 +|  |+                
           stop =|44|                                  |  |                 
       step_sel =|83|                          t1_y_3 =|74|* not used       
        dir_sel =|84|                                 +|  |+                
            clk =| 1|                                 +|  |+                
       not used *| 2|                                  |  |                 
                 |  |= >t1_u1_count_0   t1_u1_count_1 =|75|* not used       
                 |  |> not used:490                   +|  |+                
                 |  |> not used:491                   +|  |+                
                 |  |> not used:492                    |  |                 
                 |  |> not used:493            t1_y_1 =|76|* not used       
                 |  |> not used:494                   +|  |+                
                 |  |> not used:495                   +|  |+                
                 |  |> not used:496                    |  |                 
                 |  |> not used:497            t1_y_0 =|77|* not used       
                 |  |> not used:498                   +|  |+                
                 |  |> not used:499                   +|  |+                
                 |  |> not used:500                    |  |                 
                 |  |> not used:501      not used:221 *|78|* not used       
                 |  |> not used:502                   +|  |+                
                 |  |> not used:503                   +|  |+                
                 |  |> not used:504                    |  |                 
                 |  |> not used:505      not used:222 *|79|* not used       
                 |  |> not used:506                   +|  |+                
                 |  |> not used:507                   +|  |+                
                 |  |> not used:508                    |  |                 
                 |  |> not used:509      not used:223 *|80|* not used       
                 |  |> not used:510                   +|  |+                
                 |  |> not used:511                   +|  |+                
                 |  |> not used:512                    |  |                 
                 __________________________________________


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | Dedicated Inputs   |    3  |    7  |
                 | Clock/Inputs       |    1  |    1  |
                 | I/O Macrocells     |    0  |    8  |
                 | Buried Macrocells  |    5  |    8  |
                 | Expander Terms     |    0  |   32  |
                 | PIA Input Connects |    1  |   24  |
                 ______________________________________
                                          10  /   80   = 12  %


----------------------------------------------------------------------------
PLD Compiler Software:        MAX2JED.EXE    17/JUL/96    [v3.22 ] 4 IR x66

DESIGN SIGNAL PLACEMENT    (15:41:41)

Messages:
  Information: PIN Signal Placement Table.
                  1  :  clk
                  2  :  Not Used
                  3  :  Not Used
                  4  :  Not Used
                  5  :  Not Used
                  6  :  Not Used
                  7  :  Not Used
                  8  :  Not Used
                  9  :  Not Used
                 10  :  Not Used
                 11  :  Not Used
                 12  :  Not Used
                 13  :  Not Used
                 14  :  Not Used
                 15  :  Not Used
                 16  :  arm_in_3
                 17  :  Not Used
                 18  :  Not Used
                 19  :  Not Used
                 20  :  Not Used
                 21  :  Not Used
                 22  :  arm_in_2
                 23  :  Not Used
                 24  :  Not Used
                 25  :  Not Used
                 26  :  Not Used
                 27  :  arm_in_1
                 28  :  Not Used
                 29  :  Not Used
                 30  :  Not Used
                 31  :  arm_in_0
                 32  :  Not Used
                 33  :  Not Used
                 34  :  Not Used
                 35  :  Not Used
                 36  :  Not Used
                 37  :  Not Used
                 38  :  Not Used
                 39  :  Not Used
                 40  :  Not Used
                 41  :  Not Used
                 42  :  Not Used
                 43  :  Not Used
                 44  :  stop
                 45  :  Not Used
                 46  :  Not Used
                 47  :  Not Used
                 48  :  Not Used
                 49  :  Not Used
                 50  :  Not Used
                 51  :  Not Used
                 52  :  Not Used
                 53  :  Not Used
                 54  :  Not Used
                 55  :  Not Used
                 56  :  Not Used
                 57  :  Not Used
                 58  :  Not Used
                 59  :  Not Used
                 60  :  Not Used
                 61  :  Not Used
                 62  :  Not Used
                 63  :  Not Used
                 64  :  Not Used
                 65  :  Not Used
                 66  :  Not Used
                 67  :  Not Used
                 68  :  Not Used
                 69  :  Not Used
                 70  :  Not Used
                 71  :  Not Used
                 72  :  Not Used
                 73  :  Not Used
                 74  :  Not Used
                 75  :  Not Used
                 76  :  Not Used
                 77  :  Not Used
                 78  :  Not Used
                 79  :  Not Used
                 80  :  Not Used
                 81  :  Not Used
                 82  :  Not Used
                 83  :  step_sel
                 84  :  dir_sel


  Information: NODE Signal Placement Table.
                 85  :  t2_u_h1_count_h_1
                 86  :  t2_u_h1_count_h_2
                 87  :  t2_y_h_3
                 88  :  t2_y_h_2
                 89  :  t2_y_h_1
                 90  :  t2_y_h_0
                155  :  t1_u1_count_0
                164  :  t2_u_h1_count_h_0
                216  :  t1_y_2
                217  :  t1_y_3
                218  :  t1_u1_count_1
                219  :  t1_y_1
                220  :  t1_y_0


  Information: Output Logic Product Term Utilization.

                  Node#  Output Signal Name  Used   Max
                 ________________________________________
                 |  4  |  Unused          |   0  |   3  |
                 |  5  |  Unused          |   0  |   3  |
                 |  6  |  Unused          |   0  |   3  |
                 |  7  |  Unused          |   0  |   3  |
                 |  8  |  Unused          |   0  |   3  |
                 |  9  |  Unused          |   0  |   3  |
                 | 10  |  Unused          |   0  |   3  |
                 | 11  |  Unused          |   0  |   3  |
                 | 12  |  Unused          |   0  |   3  |
                 | 13  |  Unused          |   0  |   3  |
                 | 14  |  Unused          |   0  |   3  |
                 | 15  |  Unused          |   0  |   3  |
                 | 16  |  arm_in_3        |   2  |   3  |
                 | 17  |  Unused          |   0  |   3  |
                 | 20  |  Unused          |   0  |   3  |
                 | 21  |  Unused          |   0  |   3  |
                 | 22  |  arm_in_2        |   2  |   3  |
                 | 23  |  Unused          |   0  |   3  |
                 | 25  |  Unused          |   0  |   3  |
                 | 26  |  Unused          |   0  |   3  |
                 | 27  |  arm_in_1        |   2  |   3  |
                 | 28  |  Unused          |   0  |   3  |
                 | 29  |  Unused          |   0  |   3  |
                 | 30  |  Unused          |   0  |   3  |
                 | 31  |  arm_in_0        |   2  |   3  |
                 | 32  |  Unused          |   0  |   3  |
                 | 33  |  Unused          |   0  |   3  |
                 | 34  |  Unused          |   0  |   3  |
                 | 35  |  Unused          |   0  |   3  |
                 | 36  |  Unused          |   0  |   3  |
                 | 37  |  Unused          |   0  |   3  |
                 | 38  |  Unused          |   0  |   3  |
                 | 46  |  Unused          |   0  |   3  |
                 | 47  |  Unused          |   0  |   3  |
                 | 48  |  Unused          |   0  |   3  |
                 | 49  |  Unused          |   0  |   3  |
                 | 50  |  Unused          |   0  |   3  |
                 | 51  |  Unused          |   0  |   3  |
                 | 52  |  Unused          |   0  |   3  |
                 | 53  |  Unused          |   0  |   3  |
                 | 54  |  Unused          |   0  |   3  |
                 | 55  |  Unused          |   0  |   3  |
                 | 56  |  Unused          |   0  |   3  |
                 | 57  |  Unused          |   0  |   3  |
                 | 58  |  Unused          |   0  |   3  |
                 | 59  |  Unused          |   0  |   3  |
                 | 62  |  Unused          |   0  |   3  |
                 | 63  |  Unused          |   0  |   3  |
                 | 64  |  Unused          |   0  |   3  |
                 | 65  |  Unused          |   0  |   3  |
                 | 67  |  Unused          |   0  |   3  |
                 | 68  |  Unused          |   0  |   3  |
                 | 69  |  Unused          |   0  |   3  |
                 | 70  |  Unused          |   0  |   3  |
                 | 71  |  Unused          |   0  |   3  |
                 | 72  |  Unused          |   0  |   3  |
                 | 73  |  Unused          |   0  |   3  |
                 | 74  |  Unused          |   0  |   3  |
                 | 75  |  Unused          |   0  |   3  |
                 | 76  |  Unused          |   0  |   3  |
                 | 77  |  Unused          |   0  |   3  |
                 | 78  |  Unused          |   0  |   3  |
                 | 79  |  Unused          |   0  |   3  |
                 | 80  |  Unused          |   0  |   3  |
                 | 85  |  t2_u_h1_coun..  |   1  |   3  |
                 | 86  |  t2_u_h1_coun..  |   1  |   3  |
                 | 87  |  t2_y_h_3        |   3  |   3  |
                 | 88  |  t2_y_h_2        |   3  |   3  |
                 | 89  |  t2_y_h_1        |   3  |   3  |
                 | 90  |  t2_y_h_0        |   3  |   3  |
                 | 91  |  Unused          |   0  |   3  |
                 | 92  |  Unused          |   0  |   3  |
                 | 93  |  Unused          |   0  |   1  |
                 | 94  |  Unused          |   0  |   3  |
                 | 95  |  Unused          |   0  |   3  |
                 | 96  |  Unused          |   0  |   3  |
                 | 97  |  Unused          |   0  |   3  |
                 | 98  |  Unused          |   0  |   3  |
                 | 99  |  Unused          |   0  |   3  |
                 |100  |  Unused          |   0  |   3  |
                 |101  |  Unused          |   0  |   3  |
                 |102  |  Unused          |   0  |   3  |
                 |103  |  Unused          |   0  |   3  |
                 |104  |  Unused          |   0  |   3  |
                 |105  |  Unused          |   0  |   3  |
                 |106  |  Unused          |   0  |   1  |
                 |107  |  Unused          |   0  |   3  |
                 |108  |  Unused          |   0  |   3  |
                 |109  |  Unused          |   0  |   3  |
                 |110  |  Unused          |   0  |   3  |
                 |111  |  Unused          |   0  |   3  |
                 |112  |  Unused          |   0  |   3  |
                 |113  |  Unused          |   0  |   3  |
                 |114  |  Unused          |   0  |   3  |
                 |115  |  Unused          |   0  |   3  |
                 |116  |  Unused          |   0  |   3  |
                 |117  |  Unused          |   0  |   3  |
                 |118  |  Unused          |   0  |   3  |
                 |119  |  Unused          |   0  |   1  |
                 |120  |  Unused          |   0  |   3  |
                 |121  |  Unused          |   0  |   3  |
                 |122  |  Unused          |   0  |   3  |
                 |123  |  Unused          |   0  |   3  |
                 |124  |  Unused          |   0  |   3  |
                 |125  |  Unused          |   0  |   3  |
                 |126  |  Unused          |   0  |   3  |
                 |127  |  Unused          |   0  |   3  |
                 |128  |  Unused          |   0  |   3  |
                 |129  |  Unused          |   0  |   3  |
                 |130  |  Unused          |   0  |   3  |
                 |131  |  Unused          |   0  |   3  |
                 |132  |  Unused          |   0  |   1  |
                 |133  |  Unused          |   0  |   3  |
                 |134  |  Unused          |   0  |   3  |
                 |135  |  Unused          |   0  |   3  |
                 |136  |  Unused          |   0  |   3  |
                 |137  |  Unused          |   0  |   3  |
                 |138  |  Unused          |   0  |   3  |
                 |139  |  Unused          |   0  |   3  |
                 |140  |  Unused          |   0  |   3  |
                 |141  |  Unused          |   0  |   3  |
                 |142  |  Unused          |   0  |   3  |
                 |143  |  Unused          |   0  |   3  |
                 |144  |  Unused          |   0  |   3  |
                 |145  |  Unused          |   0  |   1  |
                 |146  |  Unused          |   0  |   3  |
                 |147  |  Unused          |   0  |   3  |
                 |148  |  Unused          |   0  |   3  |
                 |149  |  Unused          |   0  |   3  |
                 |150  |  Unused          |   0  |   3  |
                 |151  |  Unused          |   0  |   3  |
                 |152  |  Unused          |   0  |   3  |
                 |153  |  Unused          |   0  |   3  |
                 |154  |  Unused          |   0  |   1  |
                 |155  |  t1_u1_count_0   |   1  |   3  |
                 |156  |  Unused          |   0  |   3  |
                 |157  |  Unused          |   0  |   3  |
                 |158  |  Unused          |   0  |   3  |
                 |159  |  Unused          |   0  |   3  |
                 |160  |  Unused          |   0  |   3  |
                 |161  |  Unused          |   0  |   3  |
                 |162  |  Unused          |   0  |   3  |
                 |163  |  Unused          |   0  |   1  |
                 |164  |  t2_u_h1_coun..  |   1  |   3  |
                 |165  |  Unused          |   0  |   3  |
                 |166  |  Unused          |   0  |   3  |
                 |167  |  Unused          |   0  |   3  |
                 |168  |  Unused          |   0  |   3  |
                 |169  |  Unused          |   0  |   3  |
                 |170  |  Unused          |   0  |   3  |
                 |171  |  Unused          |   0  |   3  |
                 |172  |  Unused          |   0  |   3  |
                 |173  |  Unused          |   0  |   3  |
                 |174  |  Unused          |   0  |   3  |
                 |175  |  Unused          |   0  |   3  |
                 |176  |  Unused          |   0  |   1  |
                 |177  |  Unused          |   0  |   3  |
                 |178  |  Unused          |   0  |   3  |
                 |179  |  Unused          |   0  |   3  |
                 |180  |  Unused          |   0  |   3  |
                 |181  |  Unused          |   0  |   3  |
                 |182  |  Unused          |   0  |   3  |
                 |183  |  Unused          |   0  |   3  |
                 |184  |  Unused          |   0  |   3  |
                 |185  |  Unused          |   0  |   3  |
                 |186  |  Unused          |   0  |   3  |
                 |187  |  Unused          |   0  |   3  |
                 |188  |  Unused          |   0  |   3  |
                 |189  |  Unused          |   0  |   1  |
                 |190  |  Unused          |   0  |   3  |
                 |191  |  Unused          |   0  |   3  |
                 |192  |  Unused          |   0  |   3  |
                 |193  |  Unused          |   0  |   3  |
                 |194  |  Unused          |   0  |   3  |
                 |195  |  Unused          |   0  |   3  |
                 |196  |  Unused          |   0  |   3  |
                 |197  |  Unused          |   0  |   3  |
                 |198  |  Unused          |   0  |   3  |
                 |199  |  Unused          |   0  |   3  |
                 |200  |  Unused          |   0  |   3  |
                 |201  |  Unused          |   0  |   3  |
                 |202  |  Unused          |   0  |   1  |
                 |203  |  Unused          |   0  |   3  |
                 |204  |  Unused          |   0  |   3  |
                 |205  |  Unused          |   0  |   3  |
                 |206  |  Unused          |   0  |   3  |
                 |207  |  Unused          |   0  |   3  |
                 |208  |  Unused          |   0  |   3  |
                 |209  |  Unused          |   0  |   3  |
                 |210  |  Unused          |   0  |   3  |
                 |211  |  Unused          |   0  |   3  |
                 |212  |  Unused          |   0  |   3  |
                 |213  |  Unused          |   0  |   3  |
                 |214  |  Unused          |   0  |   3  |
                 |215  |  Unused          |   0  |   1  |
                 |216  |  t1_y_2          |   2  |   3  |
                 |217  |  t1_y_3          |   2  |   3  |
                 |218  |  t1_u1_count_1   |   1  |   3  |
                 |219  |  t1_y_1          |   2  |   3  |
                 |220  |  t1_y_0          |   2  |   3  |
                 |221  |  Unused          |   0  |   3  |
                 |222  |  Unused          |   0  |   3  |
                 |223  |  Unused          |   0  |   3  |
                 |224  |  Unused          |   0  |   1  |
                 ________________________________________
                                             33  / 588   = 5   %


  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | Dedicated Inputs   |    3  |    7  |
                 | Clock/Inputs       |    1  |    1  |
                 | I/O Macrocells     |    4  |   64  |
                 | Buried Macrocells  |   13  |  128  |
                 | Expander Terms     |    0  |  384  |
                 | PIA Input Connects |   10  |  288  |
                 ______________________________________
                                          31  /  872   = 3   %


----------------------------------------------------------------------------
PLD Compiler Software:        MAX2JED.EXE    17/JUL/96    [v3.22 ] 4 IR x66

TIMING PATH ANALYSIS       (15:41:41) using Package: CY7C341B-15HC

Messages:

----------------------------------------------------------------------------
Signal Name | Delay Type  |   tmax   | Path Description
----------------------------------------------------------------------------
pn::arm_in_3[ 16 ]
ip::t2_y_h_3.Q
              tmaxCOMB_PIN    23.0 ns  tFD+tPIA+tLAD+tCOMB+tOD
----------------------------------------------------------------------------
pn::arm_in_2[ 22 ]
ip::t2_y_h_2.Q
              tmaxCOMB_PIN    23.0 ns  tFD+tPIA+tLAD+tCOMB+tOD
----------------------------------------------------------------------------
pn::arm_in_1[ 27 ]
ip::t2_y_h_1.Q
              tmaxCOMB_PIN    23.0 ns  tFD+tPIA+tLAD+tCOMB+tOD
----------------------------------------------------------------------------
pn::arm_in_0[ 31 ]
ip::t2_y_h_0.Q
              tmaxCOMB_PIN    23.0 ns  tFD+tPIA+tLAD+tCOMB+tOD
----------------------------------------------------------------------------
ff::t2_u_h1_count_h_1.D[ 85 ]
ip::step_sel
              tmaxDFF_SU      15.0 ns  tIN+tLAD+tSU
ip::t2_u_h1_count_h_0.Q
              tmaxDFF_Q2Q     24.0 ns  tRD+tFD+tPIA+tLAD+tSU
ip::clk
              tmaxCLK         3.0 ns   tIN+tICS
----------------------------------------------------------------------------
ff::t2_u_h1_count_h_2.D[ 86 ]
ip::step_sel
              tmaxDFF_SU      15.0 ns  tIN+tLAD+tSU
ip::t2_u_h1_count_h_0.Q
              tmaxDFF_Q2Q     24.0 ns  tRD+tFD+tPIA+tLAD+tSU
ip::clk
              tmaxCLK         3.0 ns   tIN+tICS
----------------------------------------------------------------------------
ff::t2_y_h_3.D[ 87 ]
ip::dir_sel
              tmaxDFF_SU      15.0 ns  tIN+tLAD+tSU
ip::t2_u_h1_count_h_0.Q
              tmaxDFF_Q2Q     24.0 ns  tRD+tFD+tPIA+tLAD+tSU
ip::clk
              tmaxCLK         3.0 ns   tIN+tICS
----------------------------------------------------------------------------
ff::t2_y_h_2.D[ 88 ]
ip::dir_sel
              tmaxDFF_SU      15.0 ns  tIN+tLAD+tSU
ip::t2_u_h1_count_h_0.Q
              tmaxDFF_Q2Q     24.0 ns  tRD+tFD+tPIA+tLAD+tSU
ip::clk
              tmaxCLK         3.0 ns   tIN+tICS
----------------------------------------------------------------------------
ff::t2_y_h_1.D[ 89 ]
ip::dir_sel
              tmaxDFF_SU      15.0 ns  tIN+tLAD+tSU
ip::t2_u_h1_count_h_0.Q
              tmaxDFF_Q2Q     24.0 ns  tRD+tFD+tPIA+tLAD+tSU
ip::clk
              tmaxCLK         3.0 ns   tIN+tICS
----------------------------------------------------------------------------
ff::t2_y_h_0.D[ 90 ]
ip::dir_sel
              tmaxDFF_SU      15.0 ns  tIN+tLAD+tSU
ip::t2_u_h1_count_h_0.Q
              tmaxDFF_Q2Q     24.0 ns  tRD+tFD+tPIA+tLAD+tSU
ip::clk
              tmaxCLK         3.0 ns   tIN+tICS
----------------------------------------------------------------------------
ff::t1_u1_count_0.D[ 155 ]
ip::step_sel
              tmaxDFF_SU      15.0 ns  tIN+tLAD+tSU
ip::t1_u1_count_0.Q
              tmaxDFF_Q2Q     14.0 ns  tRD+tFD+tLAD+tSU
ip::clk
              tmaxCLK         3.0 ns   tIN+tICS
----------------------------------------------------------------------------
ff::t2_u_h1_count_h_0.D[ 164 ]
ip::step_sel
              tmaxDFF_SU      15.0 ns  tIN+tLAD+tSU
ip::t2_u_h1_count_h_0.Q
              tmaxDFF_Q2Q     14.0 ns  tRD+tFD+tLAD+tSU
ip::clk
              tmaxCLK         3.0 ns   tIN+tICS
----------------------------------------------------------------------------
ff::t1_y_2.D[ 216 ]
ip::dir_sel
              tmaxDFF_SU      15.0 ns  tIN+tLAD+tSU
ip::t1_u1_count_0.Q
              tmaxDFF_Q2Q     24.0 ns  tRD+tFD+tPIA+tLAD+tSU
ip::clk
              tmaxCLK         3.0 ns   tIN+tICS
----------------------------------------------------------------------------
ff::t1_y_3.D[ 217 ]
ip::dir_sel
              tmaxDFF_SU      15.0 ns  tIN+tLAD+tSU
ip::t1_u1_count_0.Q
              tmaxDFF_Q2Q     24.0 ns  tRD+tFD+tPIA+tLAD+tSU
ip::clk
              tmaxCLK         3.0 ns   tIN+tICS
----------------------------------------------------------------------------
ff::t1_u1_count_1.D[ 218 ]
ip::step_sel
              tmaxDFF_SU      15.0 ns  tIN+tLAD+tSU
ip::t1_u1_count_0.Q
              tmaxDFF_Q2Q     24.0 ns  tRD+tFD+tPIA+tLAD+tSU
ip::clk
              tmaxCLK         3.0 ns   tIN+tICS
----------------------------------------------------------------------------
ff::t1_y_1.D[ 219 ]
ip::dir_sel
              tmaxDFF_SU      15.0 ns  tIN+tLAD+tSU
ip::t1_u1_count_0.Q
              tmaxDFF_Q2Q     24.0 ns  tRD+tFD+tPIA+tLAD+tSU
ip::clk
              tmaxCLK         3.0 ns   tIN+tICS
----------------------------------------------------------------------------
ff::t1_y_0.D[ 220 ]
ip::dir_sel
              tmaxDFF_SU      15.0 ns  tIN+tLAD+tSU
ip::t1_u1_count_0.Q
              tmaxDFF_Q2Q     24.0 ns  tRD+tFD+tPIA+tLAD+tSU
ip::clk
              tmaxCLK         3.0 ns   tIN+tICS
----------------------------------------------------------------------------

Worst Case Path Summary
-----------------------

Worst case COMB,   tmax = 20.0 ns for arm_in_3
Worst case PIN->D, tmax = 15.0 ns for t2_u_h1_count_h_1.D.X1
Worst case Q->Q,   tmax = 24.0 ns for t2_u_h1_count_h_1.D.X1
Worst case CLK->Q, tmax = 3.0 ns for t2_u_h1_count_h_1.C



Summary:
                 Error Count = 0      Warning Count = 1

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        MAX2JED.EXE    17/JUL/96    [v3.22 ] 4 IR x66

JEDEC ASSEMBLE             (15:41:41)

Messages:
  Warning: Revision (V3.22) of data file C:\warp\bin\c34x.phy
           is not being used.
  Information: Processing JEDEC for LAB 1.
  Information: Processing JEDEC for LAB 2.
  Information: Processing JEDEC for LAB 3.
  Information: Processing JEDEC for LAB 4.
  Information: Processing JEDEC for LAB 5.
  Information: Processing JEDEC for LAB 6.
  Information: Processing JEDEC for LAB 7.
  Information: Processing JEDEC for LAB 8.
  Information: Processing JEDEC for LAB 9.
  Information: Processing JEDEC for LAB 10.
  Information: Processing JEDEC for LAB 11.
  Information: Processing JEDEC for LAB 12.
  Information: Processing JEDEC for Switch Matrix PLA.
  Information: JEDEC output file 'robo_arm.jed' created.


Summary:
                 Error Count = 0      Warning Count = 2

Completed Successfully at 15:41:42
