             hw-uart-ns16550 (libuart.la :: uart_component_library)

Synopsis:

   The PC16550D contains independent serial input and output ports that
   perform byte-at-a-time I/O. The 16550 is distinguished from its
   predecessor, the 16450, by two 16-byte FIFOs. The FIFOs allow the CPU to
   buffer data to reduce the frequency of interrupts. The 16550 also supports
   model-control functions DMA hand-shaking, and have a loop-back mode for
   testing.

     ----------------------------------------------------------------------

Functionality:

  Modelling:

   The Uart model is somewhat abstracted from its hardware counterpart:

     * The Sin and Sout pins carry a character at a time, including the
       parity bit, if enabled. Normally, a character is 7-bits wide, so the
       model transmits and receives one byte at a time. However, the chip
       supports character widths of 5 to 8 bits, so up to 9 bits (8 data +
       parity) may be transmitted. Stop bits are not modeled. If the
       sio-framing? attribute is off, then only the raw data bits are passed
       on the pins. The in-fifo-length attribute may be used to simulate an
       arbitrarily large input FIFO. The out-fifo-length attribute is the
       converse, though is just a placebo since there is no output FIFO
       processing at all.

     * The preceding point suggests that the model uses an infinite baud
       rate, since all the bits in a character are transmitted in a single
       event. This means that:

          * The timing pins (XIN, XOUT, RCLK, BAUDOUT) are not simulated.
          * Break functionality cannot be modeled.
          * Framing errors cannot occur.
          * The Divisor Latch is modeled but its values are ignored.
          * To handle Character Timeouts, the UART model relies on callbacks
            from the scheduler.

   +-------------------------------------------------+
   |                 SID Conventions                 |
   |-------------------------------------------------|
   |   functional | supported  | -                   |
   |--------------+------------+---------------------|
   | save/restore | supported  | -                   |
   |--------------+------------+---------------------|
   |    reentrant | not        | -                   |
   |              | supported  |                     |
   |--------------+------------+---------------------|
   |  target view | supported  | Pins and registers  |
   |      manager |            | are both accessible |
   |              |            | from the Target     |
   |              |            | View Manager        |
   +-------------------------------------------------+

     ----------------------------------------------------------------------

Environment:

   Related components
     * Besides the CPU bus, the UART typically connects to both a serial
       source and a serial sink component. The sink/source may be combined,
       as with a modem component. More advanced designs will use the
       TxRDY/RxRDY pins to communicate with a DMA controller.

       If the UART is run using interrupts (versus polling) it should also be
       connected to the scheduler so that transmit/receive timeouts are
       handled correctly.

       Because the UART will be programmed to use a specific line discipline,
       you must take care to match this discipline in both the sink and
       source.

     * The following configuration file segment shows how to connect the UART
       to a keyboard and console for interrupt-driven operation:

       # components involved - cpu and bus are assumed
       new hw-uart-ns16550 uart
       new hw-keyboard keyboard
       new hw-console console
       new sid-sched-sim target-sched
       set target-sched num-clients 2
       # connect uart to bus at memory-mapped address 0x800000
       connect-bus bus [0x800000-0x800008,4,1] uart Bus
       # pin connections
       connect-pin uart INTR -> cpu intr
       connect-pin uart Sout -> console SIN
       connect-pin keyboard SOUT -> uart Sin
       connect-pin target-sched 0-event -> uart rx-timeout-event
       connect-pin target-sched 1-event -> uart tx-timeout-event
       # use 7-bits even-parity as the line discipline
       set console line-disc "bits=7 parity=even"
       set keyboard line-disc "bits=7 parity=even"
        

     ----------------------------------------------------------------------

Component Reference:

  Component: hw-uart-ns16550

   +-------------------------------------------------+
   |                      pins                       |
   |-------------------------------------------------|
   | name  | direction | legalvalues |   behaviors   |
   |-------+-----------+-------------+---------------|
   | Sin   | in        | data +      | serial input  |
   |       |           | parity      |               |
   |-------+-----------+-------------+---------------|
   | Sout  | out       | data +      | serial output |
   |       |           | parity      |               |
   |-------+-----------+-------------+---------------|
   | INTR  | out       | 0,1         | active high   |
   |       |           |             | interrupt pin |
   |-------+-----------+-------------+---------------|
   |       |           |             | active low    |
   | TxRdy | out       | 0,1         | transmitter   |
   |       |           |             | ready (dma    |
   |       |           |             | control)      |
   |-------+-----------+-------------+---------------|
   |       |           |             | active low    |
   | RxRdy | out       | 0,1         | receiver      |
   |       |           |             | ready (dma    |
   |       |           |             | control)      |
   |-------+-----------+-------------+---------------|
   |       |           |             | active low    |
   | RTS   | out       | 0,1         | request to    |
   |       |           |             | send (modem   |
   |       |           |             | control)      |
   |-------+-----------+-------------+---------------|
   |       |           |             | active low    |
   | DTR   | out       | 0,1         | data transmit |
   |       |           |             | ready (modem  |
   |       |           |             | control)      |
   |-------+-----------+-------------+---------------|
   |       |           |             | active low    |
   | OUT1  | out       | 0,1         | user output   |
   |       |           |             | (modem        |
   |       |           |             | control)      |
   |-------+-----------+-------------+---------------|
   |       |           |             | active low    |
   | OUT2  | out       | 0,1         | user output   |
   |       |           |             | (modem        |
   |       |           |             | control)      |
   |-------+-----------+-------------+---------------|
   |       |           |             | active low    |
   | CTS   | in        | 0,1         | clear to send |
   |       |           |             | (modem        |
   |       |           |             | control)      |
   |-------+-----------+-------------+---------------|
   |       |           |             | active low    |
   | DSR   | in        | 0,1         | data set      |
   |       |           |             | ready (modem  |
   |       |           |             | control)      |
   |-------+-----------+-------------+---------------|
   |       |           |             | active low    |
   |       |           |             | ring          |
   | RI    | in        | 0,1         | indicator     |
   |       |           |             | (modem        |
   |       |           |             | control       |
   |-------+-----------+-------------+---------------|
   |       |           |             | active low    |
   | DCD   | in        | 0,1         | data carrier  |
   |       |           |             | detect (modem |
   |       |           |             | control)      |
   |-------+-----------+-------------+---------------|
   | Reset | in        | any         | master reset  |
   +-------------------------------------------------+

   +-------------------------------------------------+
   |                      buses                      |
   |-------------------------------------------------|
   | name | addresses |     accesses     | behaviors |
   |------+-----------+------------------+-----------|
   | Bus  | 0x0-0x7   | read/write,      | access to |
   |      |           | bytes only       | registers |
   +-------------------------------------------------+

   +-------------------------------------------------+
   |                   attributes                    |
   |-------------------------------------------------|
   | name  |category| legal  |default|  behaviors   ||
   |       |        | values | value |              ||
   |-------+--------+--------+-------+--------------||
   |timeout|write   |positive|10     |sets the time ||
   |       |        |integers|       |to wait       ||
   +-------------------------------------------------+

     ----------------------------------------------------------------------

References:

   National Semiconductor PC16550 data sheet, dated June 1995. This page has
   links to the data sheet and application notes (in PDF)
