2025-02-15  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/98028
	* vr-values.cc (check_for_binary_op_overflow): Try to use a known
	relationship betwen op0/op1 to statically determine overflow state.

2025-02-15  Robin Dapp  <rdapp.gcc@gmail.com>

	* config/riscv/autovec-opt.md
	(*single_widen_first_<any_widen_binop:optab><any_extend:su><mode>):
	New combine "bridge" pattern.

2025-02-15  Keith Packard  <keithp@keithp.com>

	* config/rx/rx.md (rx_cmpstrn): Correctly handle len=0 case.

2025-02-15  David Malcolm  <dmalcolm@redhat.com>

	* libsarifreplay.cc (sarif_replayer::handle_result_obj): Call
	handle_fix_object if we see a single-element "fixes" array.
	(sarif_replayer::handle_fix_object): New.
	(sarif_replayer::handle_artifact_change_object): New.

2025-02-15  David Malcolm  <dmalcolm@redhat.com>

	* libsarifreplay.cc (should_add_rule_p): New.
	(sarif_replayer::handle_result_obj): Use it to filter out rules
	that don't make sense.

2025-02-15  David Malcolm  <dmalcolm@redhat.com>

	* libsarifreplay.cc (sarif_replayer::handle_result_obj): Treat any
	relatedLocations without messages as secondary ranges within the
	diagnostic.  Doing so requires stashing the notes until after
	the diagnostic has been finished, so that relatedLocations can be
	walked in one pass.

2025-02-15  David Malcolm  <dmalcolm@redhat.com>

	PR sarif-replay/118881
	* doc/libgdiagnostics/topics/physical-locations.rst: Add
	diagnostic_physical_location_get_file.
	* libgdiagnostics++.h (physical_location::get_file): New wrapper.
	(diagnostic::add_location): Likewise.
	* libgdiagnostics.cc (diagnostic_manager::get_file_by_name): New.
	(diagnostic_physical_location::get_file): New.
	(diagnostic_physical_location_get_file): New.
	* libgdiagnostics.h (diagnostic_physical_location_get_file): New.
	* libgdiagnostics.map (diagnostic_physical_location_get_file): New.
	* libsarifreplay.cc (class annotation): New.
	(add_any_annotations): New.
	(sarif_replayer::handle_result_obj): Collect vectors of
	annotations in the calls to handle_location_object and apply them
	to "err" and to "note" as appropriate.
	(sarif_replayer::handle_thread_flow_location_object): Pass nullptr
	for annotations.
	(sarif_replayer::handle_location_object): Handle §3.28.6
	"annotations" property, using it to populate a new
	"out_annotations" param.

2025-02-15  Thomas Schwinge  <thomas@codesourcery.com>

	* config/nvptx/nvptx.cc (nvptx_record_needed_fndecl): Tag as
	'static'.

2025-02-15  Jin Ma  <jinma@linux.alibaba.com>

	PR target/118872
	* config/riscv/riscv.cc (riscv_fntype_abi): Strengthen the logic
	of the check to avoid missing the error report.

2025-02-14  Georg-Johann Lay  <avr@gjlay.de>

	PR target/118878
	* config/avr/avr.cc (avr_out_plus_1): Don't ICE on result of
	paradoxical reg's register allocation.

2025-02-14  Thomas Schwinge  <tschwinge@baylibre.com>

	PR target/94282
	PR target/113331
	* common/config/gcn/gcn-common.cc (gcn_except_unwind_info): 'return UI_TARGET;'.
	* config/gcn/gcn.cc (gcn_asm_init_sections): New function.
	(TARGET_ASM_INIT_SECTIONS): '#define'.

2025-02-14  Thomas Schwinge  <tschwinge@baylibre.com>

	PR target/86660
	* common/config/nvptx/nvptx-common.cc (nvptx_except_unwind_info):
	'return UI_TARGET;'.
	* config/nvptx/nvptx.cc (nvptx_assemble_integer): Handle
	'exception_section'.
	(nvptx_output_section_asm_op, nvptx_asm_init_sections): New
	functions.
	(TARGET_ASM_INIT_SECTIONS): '#define'.
	* config/nvptx/nvptx.h (TEXT_SECTION_ASM_OP, DATA_SECTION_ASM_OP):
	Don't '#define'.
	(ASM_OUTPUT_DWARF_DELTA): '#define'.

2025-02-14  Thomas Schwinge  <tschwinge@baylibre.com>

	* config/nvptx/nvptx.cc (init_frag): New 'bool active' member.
	(output_init_frag, nvptx_assemble_value, nvptx_assemble_integer)
	(nvptx_output_skip, nvptx_assemble_decl_begin)
	(nvptx_assemble_decl_end): Sanity-check its state.

2025-02-14  Thomas Schwinge  <tschwinge@baylibre.com>

	* config/nvptx/nvptx.cc (nvptx_output_skip): Clarify case of
	no or incomplete initializer.

2025-02-14  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/118852
	* tree-vect-slp.cc (vect_analyze_slp): For early-break
	forced-live IVs make sure we create an appropriate
	entry into the SLP graph.

2025-02-14  Jakub Jelinek  <jakub@redhat.com>

	PR debug/118790
	* tree.cc (struct gt_value_expr_mark_data): New type.
	(gt_value_expr_mark_2): Don't call ggc_set_mark, instead check
	ggc_marked_p.  Treat data as gt_value_expr_mark_data * with pset
	in it rather than address of the pset itself and push to be marked
	VAR_DECLs into to_mark vec.
	(gt_value_expr_mark_1): Change argument from hash_set<tree> *
	to gt_value_expr_mark_data * and find pset in it.
	(gt_value_expr_mark): Pass to traverse_noresize address of
	gt_value_expr_mark_data object rather than hash_table<tree> and
	for all entries in the to_mark vector after the traversal call
	gt_ggc_mx.

2025-02-14  Lulu Cheng  <chenglulu@loongson.cn>

	* config/loongarch/genopts/loongarch.opt.in: Add
	option '-maddr-reg-reg-cost='.
	* config/loongarch/loongarch-def.cc
	(loongarch_rtx_cost_data::loongarch_rtx_cost_data): Initialize
	addr_reg_reg_cost to 3.
	* config/loongarch/loongarch-opts.cc
	(loongarch_target_option_override): If '-maddr-reg-reg-cost='
	is not used, set it to the initial value.
	* config/loongarch/loongarch-tune.h
	(struct loongarch_rtx_cost_data): Add the member
	addr_reg_reg_cost and its assignment function to the structure
	loongarch_rtx_cost_data.
	* config/loongarch/loongarch.cc (loongarch_address_insns):
	Use la_addr_reg_reg_cost to set the cost of ADDRESS_REG_REG.
	* config/loongarch/loongarch.opt: Regenerate.
	* config/loongarch/loongarch.opt.urls: Regenerate.
	* doc/invoke.texi: Add description of '-maddr-reg-reg-cost='.

2025-02-14  Lulu Cheng  <chenglulu@loongson.cn>

	PR target/118843
	* config/loongarch/loongarch-c.cc
	(loongarch_update_cpp_builtins): Fix macro definition issues.

2025-02-14  Lulu Cheng  <chenglulu@loongson.cn>

	PR target/118828
	* config/loongarch/loongarch-c.cc (loongarch_pragma_target_parse):
	Update the predefined macros.

2025-02-14  Lulu Cheng  <chenglulu@loongson.cn>

	* config/loongarch/loongarch-c.cc (builtin_undef): New macro.
	(loongarch_cpu_cpp_builtins): Split to loongarch_update_cpp_builtins
	and loongarch_define_unconditional_macros.
	(loongarch_def_or_undef): New functions.
	(loongarch_define_unconditional_macros): Likewise.
	(loongarch_update_cpp_builtins): Likewise.

2025-02-14  Lulu Cheng  <chenglulu@loongson.cn>

	* config/loongarch/loongarch-target-attr.cc
	(loongarch_pragma_target_parse): Move to ...
	(loongarch_register_pragmas): Move to ...
	* config/loongarch/loongarch-c.cc
	(loongarch_pragma_target_parse): ... here.
	(loongarch_register_pragmas): ... here.
	* config/loongarch/loongarch-protos.h
	(loongarch_process_target_attr): Function Declaration.

2025-02-14  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/90579
	* tree-ssa-forwprop.cc (simplify_bitfield_ref): Move to
	match.pd.
	(pass_forwprop::execute): Adjust.
	* match.pd (bit_field_ref (vec_perm ...)): New pattern
	modeled after simplify_bitfield_ref.
	* tree-vect-loop.cc (vect_expand_fold_left): Fold the
	element extract stmt, combining it with the vector def.

2025-02-13  Robin Dapp  <rdapp.gcc@gmail.com>

	PR target/118832
	* config/riscv/riscv-v.cc (expand_const_vector):  Expand as
	vlmax insn during lra.

2025-02-13  Marek Polacek  <polacek@redhat.com>

	PR driver/117739
	* doc/invoke.texi: Tweak wording for -Whardened.
	* gcc.cc (driver_handle_option): If -z lazy or -z norelro was
	specified, don't enable linker hardening.
	(process_command): Don't check warn_hardened.

2025-02-13  Ed Catmur  <ed@catmur.uk>
	    Jason Merrill  <jason@redhat.com>

	PR c++/70536
	* dwarf2out.cc (gen_formal_parameter_pack_die): Add name attr.

2025-02-13  Jakub Jelinek  <jakub@redhat.com>

	PR debug/118790
	* gengtype.cc (write_roots): Remove cache variable, instead break from
	the loop on match and test o for NULL.  If the cache option has
	non-empty string argument, call the specified function with v->name
	as argument before calling gt_cleare_cache on it.
	* tree.cc (gt_value_expr_mark_2, gt_value_expr_mark_1,
	gt_value_expr_mark): New functions.
	(value_expr_for_decl): Use GTY ((cache ("gt_value_expr_mark"))) rather
	than just GTY ((cache)).
	* doc/gty.texi (cache): Document optional argument of cache option.

2025-02-13  Christophe Lyon  <christophe.lyon@linaro.org>

	PR target/114522
	* config/arm/arm-builtins.cc (arm_fold_aes_op): New function.
	(arm_general_gimple_fold_builtin): New function.
	* config/arm/arm-builtins.h (arm_general_gimple_fold_builtin): New
	prototype.
	* config/arm/arm.cc (arm_gimple_fold_builtin): Call
	arm_general_gimple_fold_builtin as needed.

2025-02-13  Jakub Jelinek  <jakub@redhat.com>

	PR c++/118822
	PR c++/118833
	* tree-iterator.h (tsi_split_stmt_list): Declare.
	* tree-iterator.cc (tsi_split_stmt_list): New function.

2025-02-13  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>

	* configure.ac (gcc_cv_ld_eh_frame_ciev3): Remove.
	* configure, config.in: Regenerate.
	* config/sol2.cc (solaris_override_options): Remove.
	* config/sol2.h (SUBTARGET_OVERRIDE_OPTIONS): Remove.
	* config/sol2-protos.h (solaris_override_options): Remove.

2025-02-13  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>

	* doc/install.texi (Specific, *-*-solaris2*): Updates for newer
	Solaris 11.4 SRUs and binutils 2.44.

2025-02-13  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>

	PR target/118835
	* config/s390/s390.cc (s390_valid_shift_count): Reject shift
	count operands which do not trivially fit the scheme of
	address operands.

2025-02-13  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/118817
	* tree-ssa-sccvn.cc (vn_nary_simplify): Do not process
	CONSTRUCTOR NARY or update from CONSTRUCTOR simplified
	gimple_match_op.

2025-02-12  Andrew Pinski  <quic_apinski@quicinc.com>

	PR rtl-optimization/102150
	* loop-invariant.cc (find_invariant_insn): Treat inline-asm similar to
	trapping instruction and only move them if always executed.

2025-02-12  Andrew Pinski  <quic_apinski@quicinc.com>

	PR rtl-optimization/102150
	* ifcvt.cc (cheap_bb_rtx_cost_p): Return false if the insn
	has an inline-asm in it.

2025-02-12  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/avr.opt.urls: Add -mcall-main.

2025-02-12  Georg-Johann Lay  <avr@gjlay.de>

	PR target/118806
	* config/avr/avr.opt (-mcall-main): New option and...
	(avropt_call_main): ...variable.
	* config/avr/avr.cc (avr_no_call_main_p): New variable.
	(avr_insert_attributes) [-mno-call-main, main]: Add attributes
	noreturn and section(".init9") to main.  Set avr_no_call_main_p.
	(avr_file_end) [avr_no_call_main_p]: Define symbol __call_main.
	* doc/invoke.texi (AVR Options) <-mno-call-main>: Document.
	<-mnodevicelib>: Extend explanation.

2025-02-12  Alex Coplan  <alex.coplan@arm.com>

	PR tree-optimization/117790
	* tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
	Set profile counts for {main,alt}_loop_exit_block.

2025-02-12  Vineet Gupta  <vineetg@rivosinc.com>

	* config/riscv/vector.md: vncvt substitute vnsrl.
	vnsrl with x0 replace with immediate 0.
	vneg substitute vrsub.

2025-02-12  Jin Ma  <jinma@linux.alibaba.com>

	PR target/118601
	* config/riscv/riscv-string.cc (expand_block_move): Check with new
	constraint 'vl' instead of 'K'.
	(expand_vec_setmem): Likewise.
	(expand_vec_cmpmem): Likewise.
	* config/riscv/riscv-v.cc (force_vector_length_operand): Likewise.
	(expand_load_store): Likewise.
	(expand_strided_load): Likewise.
	(expand_strided_store): Likewise.
	(expand_lanes_load_store): Likewise.

2025-02-12  Sandra Loosemore  <sloosemore@baylibre.com>

	* doc/install.texi: Add missing comma after @xref to fix warning.

2025-02-12  Sandra Loosemore  <sloosemore@baylibre.com>

	* doc/extend.texi: Fix a bunch of typos and other writing bugs.
	* doc/invoke.texi: Likewise.

2025-02-12  Sandra Loosemore  <sloosemore@baylibre.com>

	* Makefile.in (TEXI_GCCINT_FILES): Remove interface.texi.
	* doc/gccint.texi (Top): Remove menu entry for the "interface" node,
	and include of interface.texi.
	* doc/interface.texi: Delete.

2025-02-12  Yangyu Chen  <cyy@cyyself.name>

	* config/riscv/riscv-feature-bits.h (RISCV_VENDOR_FEATURE_BITS_LENGTH): Drop.
	(struct riscv_vendor_feature_bits): Drop.

2025-02-11  Jeff Law  <jlaw@ventanamicro.com>

	PR target/115478
	* config/aarch64/iterators.md (any_or_plus): New code iterator.
	* config/aarch64/aarch64.md (extr<mode>5_insn): Use any_or_plus.
	(extr<mode>5_insn_alt, extrsi5_insn_uxtw): Likewise.
	(extrsi5_insn_uxtw_alt, extrsi5_insn_di): Likewise.

2025-02-11  Jason Merrill  <jason@redhat.com>

	PR c++/188574
	* doc/invoke.texi: Adjust -frange-for-ext-temps documentation.

2025-02-11  Andrew Carlotti  <andrew.carlotti@arm.com>

	* config/aarch64/aarch64-option-extensions.def
	(SSVE_FP8FMA): Adjust formatting.
	(FP8DOT4): Replace FP8FMA dependency with FP8.
	(SSVE_FP8DOT4): Replace SSVE_FP8FMA dependency with SME2+FP8.
	(FP8DOT2): Replace FP8DOT4 dependency with FP8.
	(SSVE_FP8DOT2): Replace SSVE_FP8DOT4 dependency with SME2+FP8.

2025-02-11  Sandra Loosemore  <sloosemore@baylibre.com>

	* omp-general.cc (omp_check_context_selector): Change
	metadirective_p argument to a 3-way flag.  Add extra check for
	OMP_CTX_BEGIN_DECLARE_VARIANT.
	* omp-general.h (enum omp_ctx_directive): New.
	(omp_check_context_selector): Adjust declaration.

2025-02-11  Sandra Loosemore  <sloosemore@baylibre.com>

	* omp-general.cc (omp_context_selector_props_compare): Handle
	arbitrary expressions in the "user" and "device_num" selectors.
	(omp_context_selector_set_compare): Detect mismatch when one
	selector specifies a score and the other doesn't.

2025-02-11  Martin Jambor  <mjambor@suse.cz>

	PR lto/118125
	* ipa-fnsummary.cc (redirect_to_unreachable): Add checking assert
	that the builtin_unreachable decl has attribute cold.

2025-02-11  David Malcolm  <dmalcolm@redhat.com>

	PR sarif-replay/118792
	* libsarifreplay.cc (sarif_replayer::handle_region_object): Fix
	off-by-one in handling of endColumn property so that the code
	matches the comment and the SARIF spec (§3.30.8).

2025-02-11  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/118817
	* tree-ssa-pre.cc (fully_constant_expression): Fold into
	the single caller.
	(phi_translate_1): Refactor folded in fully_constant_expression.
	* tree-ssa-sccvn.cc (vn_nary_simplify): Update the NARY with
	the simplified expression.

2025-02-11  H.J. Lu  <hjl.tools@gmail.com>

	PR target/118825
	* config/i386/i386.h (ASM_OUTPUT_SYMBOL_REF): Replace x with
	SYM.

2025-02-11  YunQiang Su  <syq@debian.org>

	* config.gcc: Add mips*64*-linux-muslabi64 triple support.

2025-02-11  Jie Mei  <jie.mei@oss.cipunited.com>
	    Xi Ruoyao  <xry111@xry111.site>

	* config/mips/i6400.md (i6400_fpu_minmax): Include
	fclass type.
	(i6400_fpu_fadd): Include frint type.
	* config/mips/mips.cc (AVAIL_NON_MIPS16): Add an entry
	for __builtin_mipsr6_xxx.
	(MIPSR6_BUILTIN_PURE): Same as above.
	(CODE_FOR_mipsr6_min_a_s, CODE_FOR_mipsr6_min_a_d)
	(CODE_FOR_mipsr6_max_a_s, CODE_FOR_mipsr6_max_a_d)
	(CODE_FOR_mipsr6_class_s, CODE_FOR_mipsr6_class_d):
	New code_aliasing macros.
	(mips_builtins): Add mips32r6 min_a_s, min_a_d, max_a_s,
	max_a_d, class_s, class_d builtins.
	* config/mips/mips.h (ISA_HAS_FRINT): Define a new macro.
	(ISA_HAS_FCLASS): Same as above.
	* config/mips/mips.md (UNSPEC_FRINT): New unspec.
	(UNSPEC_FCLASS): Same as above.
	(type): Add frint and fclass.
	(fmin_a_<mode>): Generates MINA.fmt instructions.
	(fmax_a_<mode>): Generates MAXA.fmt instructions.
	(rint<mode>2): Generates RINT.fmt instructions.
	(fclass_<mode>): Generates CLASS.fmt instructions.
	* config/mips/p6600.md (p6600_fpu_fadd): Include
	frint type.
	(p6600_fpu_fabs): Include fclass type.

2025-02-11  Haochen Jiang  <haochen.jiang@intel.com>

	PR target/118813
	* config/i386/avx512bwintrin.h: Fix wrong __OPTIMIZE__
	wrap.

2025-02-10  Tobias Burnus  <tburnus@baylibre.com>

	* config/gcn/mkoffload.cc (enum elf_arch_code): Add
	EF_AMDGPU_MACH_AMDGCN_NONE.
	(elf_arch): Use enum elf_arch_code as type.
	(tool_cleanup): Silence warning by removing tailing '.' from error.
	(get_arch_name): Return enum elf_arch_code.
	(check_for_missing_lib): New; print fatal error if the multilib
	is not available but it is for the associate generic ISA.
	(main): Call it.

2025-02-10  Tobias Burnus  <tburnus@baylibre.com>

	* doc/install.texi (GCN): Update section about multilibs and
	required LLVM version.

2025-02-10  Martin Jambor  <mjambor@suse.cz>

	PR ipa/118097
	* ipa-cp.cc (ipa_get_jf_arith_result): Adjust comment.
	(ipa_get_jf_pass_through_result): Removed.
	(ipa_value_from_jfunc): Use directly ipa_get_jf_arith_result, do
	not specify operation type but make sure we check and possibly
	convert the result.
	(get_val_across_arith_op): Remove the last parameter, always pass
	NULL_TREE to ipa_get_jf_arith_result in its last argument.
	(propagate_vals_across_arith_jfunc): Do not pass res_type to
	get_val_across_arith_op.
	(propagate_vals_across_pass_through): Add checking assert that
	parm_type is not NULL.

2025-02-10  Jakub Jelinek  <jakub@redhat.com>

	PR target/118623
	* config/i386/i386.md (*bt<mode>): Represent bt as
	compare:CCC of const0_rtx and zero_extract rather than
	zero_extract and const0_rtx.
	(*bt<SWI48:mode>_mask): Likewise.
	(*jcc_bt<mode>): Likewise.  Use LTU and GEU as flags test
	instead of EQ and NE.
	(*jcc_bt<mode>_mask): Likewise.
	(*jcc_bt<SWI48:mode>_mask_1): Likewise.
	(Help combine recognize bt followed by cmov splitter): Likewise.
	(*bt<mode>_setcqi): Likewise.
	(*bt<mode>_setncqi): Likewise.
	(*bt<mode>_setnc<mode>): Likewise.
	(*bt<mode>_setncqi_2): Likewise.
	(*bt<mode>_setc<mode>_mask): Likewise.

2025-02-09  Dario Gjorgjevski  <dario.gjorgjevski@gmail.com>

	PR middle-end/117263
	* genautomata.cc (output_statistics): Avoid set but unnused warnings
	when compiling with NDEBUG.

2025-02-09  Jeff Law  <jlaw@ventanamicro.com>

	PR target/118146
	* config/riscv/riscv.cc (riscv_legitimize_move): Handle subreg
	of vector source better to avoid ICE.

2025-02-08  Georg-Johann Lay  <avr@gjlay.de>

	PR target/118764
	* doc/invoke.texi (AVR Options): Fix typos.

2025-02-08  Thomas Schwinge  <tschwinge@baylibre.com>

	* config/gcn/gcn.md (exception_receiver): 'define_expand'.
	* config/nvptx/nvptx.md (exception_receiver): Likewise.

2025-02-08  Thomas Schwinge  <tschwinge@baylibre.com>

	* doc/sourcebuild.texi (Effective-Target Keywords): Clarify that
	effective-target 'exceptions' and 'exceptions_enabled' are
	orthogonal.

2025-02-08  Jakub Jelinek  <jakub@redhat.com>

	PR target/118776
	* config/i386/sse.md (<code><mode>3_mask): Use VI1248_AVX512VLBW
	iterator rather than VI48_AVX512VL.
	(<mask_codefor><code><mode>3<mask_name>): Rename to ...
	(*avx512bw_<code><mode>3<mask_name>): ... this.  Use
	nonimmediate_operand rather than register_operand predicate and %v
	rather than v constraint for operand 1 and adjust condition to reject
	MEMs in both operand 1 and 2.

2025-02-07  Andrew Pinski  <quic_apinski@quicinc.com>

	PR target/114522
	* config/aarch64/aarch64-builtins.cc (aarch64_fold_aes_op): New function.
	(aarch64_general_gimple_fold_builtin): Call aarch64_fold_aes_op for crypto_aese
	and crypto_aesd.

2025-02-07  Andi Kleen  <ak@gcc.gnu.org>

	PR preprocessor/118168
	* input.cc (file_cache::m_line_recent,
	m_line_recent_first, m_line_recent_last): Add.
	(file_cache_slot::evict): Clear new fields.
	(file_cache_slot::create): Clear new fields.
	(file_cache_slot::file_cache_slot): Initialize new fields.
	(file_cache_slot::~file_cache_slot): Release m_line_recent.
	(file_cache_slot::get_next_line): Maintain ring buffer of lines
	in m_line_recent.
	(file_cache_slot::read_line_num): Use m_line_recent to look up
	recent lines quickly.

2025-02-07  Richard Earnshaw  <rearnsha@arm.com>

	PR target/118089
	* config/arm/arm.cc (arm_emit_multi_reg_pop): Restructure.
	Don't emit LDR on thumb2 when POP can be used for smaller code.
	Don't add a CFA adjust note when SP is popped off the stack.

2025-02-07  Richard Earnshaw  <rearnsha@arm.com>

	PR target/118089
	* config/arm/arm.cc (arm_emit_multi_reg_pop): Add a CFA adjust
	note to single-register POP instructions.

2025-02-07  Jeff Law  <jlaw@ventanamicro.com>

	PR rtl-optimization/116244
	* ira-build.cc (create_insn_allocnos): Do not restrict the check for
	subreg uses to allocno creation time.  Do it for all uses.

2025-02-07  Richard Biener  <rguenther@suse.de>

	PR jit/118780
	* system.h: Check INCLUDE_DLFCN_H for including dlfcn.h instead
	of ENABLE_PLUGIN.
	* plugin.cc: Define INCLUDE_DLFCN_H.

2025-02-07  Pan Li  <pan2.li@intel.com>

	PR target/118103
	* config/riscv/riscv.cc (riscv_conditional_register_usage): Add
	the VXRM as the global_regs.

2025-02-07  Andrew Pinski  <quic_apinski@quicinc.com>

	PR target/118771
	* config/aarch64/aarch64.cc (aarch64_split_move): Assert that npieces is
	greater than 0.

2025-02-07  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/115538
	* tree-vectorizer.h (vect_get_slp_scalar_def): Declare.
	* tree-vect-slp.cc (vect_get_slp_scalar_def): New helper.
	* tree-vect-generic.cc (expand_vector_conversion): Adjust.
	* tree-vect-stmts.cc (vectorizable_conversion): For SLP
	correctly look at ranges of the scalar defs of the SLP operand.
	(supportable_indirect_convert_operation): Likewise.

2025-02-07  Tobias Burnus  <tburnus@baylibre.com>

	* config/gcn/gcn.cc (gcn_hsa_declare_function_name): Update
	'amdhsa.version' output to match used code version.
	* config/gcn/gen-gcn-device-macros.awk: Add a comment to
	crosslink.

2025-02-07  Xi Ruoyao  <xry111@xry111.site>

	* config/loongarch/loongarch.md
	(*sel<code><GPR:mode>_using_<GPR2:mode>): Rename to ...
	(*sel<code><GPR:mode>_using_<X:mode>): ... here.
	(GPR2): Remove as nothing uses it now.

2025-02-07  Alexandre Oliva  <oliva@adacore.com>

	PR tree-optimization/118514
	PR tree-optimization/118706
	* gimple-fold.cc (decode_field_reference): Refuse to consider
	merging out-of-bounds BIT_FIELD_REFs.
	(make_bit_field_load): Drop too-strict assert.
	* tree-eh.cc (bit_field_ref_in_bounds_p): Rename to...
	(access_in_bounds_of_type_p): ... this.  Change interface,
	export.
	(tree_could_trap_p): Adjust.
	* tree-eh.h (access_in_bounds_of_type_p): Declare.

2025-02-07  Tobias Burnus  <tburnus@baylibre.com>

	* config/gcn/gcn-devices.def (GCN_DEVICE): Add gfx9-generic,
	gfx902, gfx904, gfx909, gfx1031, gfx1032, gfx1033, gfx1034,
	gfx1035, gfx1101, gfx1102, gfx1150, gfx1151, gfx1152, and gfx1153.
	Add a currently unused column linking, a specific ISA to a generic
	one (if it exists).
	* config/gcn/gcn-tables.opt: Regenerate
	* doc/invoke.texi (AMD GCN): Add the the new gfc... and the older
	gfx{10-3,11}-generic to -march= as 'experimental'.

2025-02-07  Tobias Burnus  <tburnus@baylibre.com>

	* config/gcn/gcn-devices.def (GCN_DEVICE): Change sramecc for
	gfx906 to 'any'.
	* config/gcn/gcn.cc (GCN_DEVICE): Add tailing ... to #define.

2025-02-07  H.J. Lu  <hjl.tools@gmail.com>

	PR rtl-optimization/111673
	PR rtl-optimization/115932
	PR rtl-optimization/116028
	PR rtl-optimization/117081
	PR rtl-optimization/117082
	PR rtl-optimization/118497
	* ira-color.cc (assign_hard_reg): Call the target hook for the
	callee-saved register cost scale in epilogue and prologue.
	* target.def (ira_callee_saved_register_cost_scale): New target
	hook.
	* targhooks.cc (default_ira_callee_saved_register_cost_scale):
	New.
	* targhooks.h (default_ira_callee_saved_register_cost_scale):
	Likewise.
	* config/i386/i386.cc (ix86_ira_callee_saved_register_cost_scale):
	New.
	(TARGET_IRA_CALLEE_SAVED_REGISTER_COST_SCALE): Likewise.
	* doc/tm.texi: Regenerated.
	* doc/tm.texi.in (TARGET_IRA_CALLEE_SAVED_REGISTER_COST_SCALE):
	New.

2025-02-06  Craig Blackmore  <craig.blackmore@embecosm.com>

	* config/riscv/riscv.md: Move UNSPEC_SSP_SET and UNSPEC_SSP_TEST
	to unspec enum.

2025-02-06  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/avr.opt.urls: Add mcvt.

2025-02-06  Tamar Christina  <tamar.christina@arm.com>

	PR tree-optimization/118756
	* tree-ssa-loop-ivopts.cc (contain_complex_addr_expr): Remove.

2025-02-06  Georg-Johann Lay  <avr@gjlay.de>

	PR target/118764
	* config/avr/avr.opt (-mcvt): New target option.
	* config/avr/avr-arch.h (AVR_CVT): New enum value.
	* config/avr/avr-mcus.def: Add AVR_CVT flag for devices that
	support it.
	* config/avr/avr.cc (avr_handle_isr_attribute) [TARGET_CVT]: Issue
	an error when a vector number larger that 3 is used.
	* config/avr/gen-avr-mmcu-specs.cc (McuInfo.have_cvt): New property.
	(print_mcu) <*avrlibc_startfile>: Use crt<mcu>-cvt.o depending
	on -mcvt (or issue an error when the device doesn't support a CVT).
	* doc/invoke.texi (AVR Options): Document -mcvt.

2025-02-06  Jakub Jelinek  <jakub@redhat.com>

	PR rtl-optimization/117506
	* loop-iv.cc (get_biv_step_1): For {ZERO,SIGN}_EXTEND
	of PLUS apply {ZERO,SIGN}_EXTEND to op1.

2025-02-06  Georg-Johann Lay  <avr@gjlay.de>

	PR target/118768
	* config/avr/genmultilib.awk: Parse the AVR_MCU lines in
	a more robust way w.r.t. white spaces.

2025-02-06  Lulu Cheng  <chenglulu@loongson.cn>

	PR target/118561
	* config/loongarch/loongarch-builtins.cc
	(loongarch_expand_builtin_lsx_test_branch):
	NULL_RTX will not be returned when an error is detected.
	(loongarch_expand_builtin): Likewise.

2025-02-06  Richard Sandiford  <richard.sandiford@arm.com>

	PR tree-optimization/110449
	* tree-ssa-loop-manip.h (insert_iv_increment): Declare.
	* tree-ssa-loop-manip.cc (insert_iv_increment): New function,
	split out from...
	(create_iv): ...here and generalized to gimple_seqs.
	* tree-vect-loop.cc (vectorizable_induction): Use
	standard_iv_increment_position and insert_iv_increment
	to insert the IV increment.

2025-02-06  Richard Biener  <rguenther@suse.de>

	PR rtl-optimization/117922
	* fold-mem-offsets.cc (pass_fold_mem_offsets::execute):
	Do nothing for a highly connected CFG.

2025-02-06  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/118749
	* tree-vect-data-refs.cc (vector_alignment_reachable_p): Pass
	in the vectorization factor, when that cannot maintain
	the DRs target alignment do not claim we can reach that
	by peeling.

2025-02-05  Jeff Law  <jlaw@ventanamicro.com>

	* config/bfin/bfin.md (abssi): Disable pattern.

2025-02-05  Vladimir N. Makarov  <vmakarov@redhat.com>

	PR rtl-optimization/115568
	* lra-remat.cc (create_cands): Check that output reload insn is
	adjacent to given insn.  Update a comment.

2025-02-05  Richard Sandiford  <richard.sandiford@arm.com>

	* config/aarch64/aarch64.cc (aarch64_insn_cost): Give PARALLELs
	the same cost as the costliest SET.

2025-02-05  Jakub Jelinek  <jakub@redhat.com>

	PR rtl-optimization/117239
	* cselib.cc (cselib_init): Remove spurious closing paren in
	the #ifdef STACK_ADDRESS_OFFSET specific code.

2025-02-05  Jakub Jelinek  <jakub@redhat.com>

	PR rtl-optimization/117239
	* cselib.cc: Include predict.h.
	(callmem): Change type from rtx to rtx[2].
	(cselib_preserve_only_values): Use callmem[0] rather than callmem.
	(cselib_invalidate_mem): Optimize and don't try to invalidate
	for the mem_rtx == callmem[1] case MEMs which clearly can't be
	below the stack pointer.
	(cselib_process_insn): Use callmem[0] rather than callmem.
	For const/pure calls also call cselib_invalidate_mem (callmem[1])
	in !ACCUMULATE_OUTGOING_ARGS or cfun->calls_alloca functions.
	(cselib_init): Initialize callmem[0] rather than callmem and also
	initialize callmem[1].

2025-02-05  Richard Earnshaw  <rearnsha@arm.com>

	PR target/118089
	* config/arm/arm.cc (thumb2_expand_return): Use LDM SP!, {PC}
	when optimizing for size, or when there's no performance benefit over
	LDR PC, [SP], #4.
	(arm_expand_epilogue): Likewise.

2025-02-05  Richard Earnshaw  <rearnsha@arm.com>

	* config/arm/arm.md (*pop_multiple_with_writeback_and_return): Remove
	constraints.  Don't validate the first transfer register here.

2025-02-05  Richard Earnshaw  <rearnsha@arm.com>

	* config/arm/arm.cc (decompose_addr_for_ldm_stm): New function.
	(ldm_stm_operation_p): Rework to clarify logic.  Allow single
	registers to be pushed or popped using LDM/STM.

2025-02-05  Xi Ruoyao  <xry111@xry111.site>

	PR tree-optimization/118727
	* tree-vect-patterns.cc (vect_recog_sad_pattern): Don't call
	vect_look_through_possible_promotion on ABD inputs.

2025-02-05  Sebastian Huber  <sebastian.huber@embedded-brains.de>

	* config/arm/t-rtems: Add Cortex-M33 multilib.

2025-02-04  Andi Kleen  <ak@gcc.gnu.org>

	* doc/invoke.texi: Document file cache tunables.
	* params.opt: Move auto tuning description to lines.

2025-02-04  Ilya Leoshkevich  <iii@linux.ibm.com>

	* config/s390/s390.cc (print_operand): Remove the no longer
	necessary 31-bit and weak symbol handling.
	* config/s390/s390.md (*movdi_64): Do not use @PLT with larl.
	(*movsi_larl): Likewise.
	(main_base_64): Likewise.
	(reload_base_64): Likewise.

2025-02-04  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/117113
	* gimple-loop-jam.cc (unroll_jam_possible_p): Detect when
	we cannot handle virtual SSA update.

2025-02-04  Andrew Pinski  <quic_apinski@quicinc.com>

	PR middle-end/116926
	* optabs-query.cc (find_widening_optab_handler_and_mode): Fix
	limit for `vec-mode -> scalar-mode` case.

2025-02-04  Richard Biener  <rguenther@suse.de>

	PR rtl-optimization/117611
	* combine.cc (simplify_shift_const_1): Bail if not
	scalar int mode.

2025-02-04  Richard Biener  <rguenther@suse.de>

	PR lto/113207
	* ipa-free-lang-data.cc (free_lang_data_in_type): First drop
	const/volatile qualifiers from function argument types,
	then build a simplified type.

2025-02-03  Uros Bizjak  <ubizjak@gmail.com>

	* config/i386/i386.md (*sibcall_pop_memory):
	Disable for TARGET_INDIRECT_BRANCH_REGISTER
	* config/i386/predicates.md (call_insn_operand): Enable when
	"satisfies_constraint_Bw (op)" is true, instead of open-coding
	constraint here.
	(sibcall_insn_operand): Ditto with "satisfies_constraint_Bs (op)"

2025-02-03  Richard Sandiford  <richard.sandiford@arm.com>

	* config/aarch64/aarch64.cc (aarch64_choose_vector_init_constant):
	New function, split out from...
	(aarch64_expand_vector_init_fallback): ...here.  Use a bit-
	reversed increment to find a constant index.  Add support for
	stepped constants.

2025-02-03  John David Anglin  <danglin@gcc.gnu.org>

	PR rtl-optimization/117248
	* config/pa/predicates.md (r25_operand): New predicate.
	(r26_operand): Likewise.
	* config/pa/pa.md: Use match_operand for r25 and r26 hard
	register operands in mult, div, udiv, mod and umod millicode
	patterns.

2025-02-03  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/118717
	* tree-ssa-phiopt.cc (cond_if_else_store_replacement_1):
	Do not common stores referencing abnormal SSA names.
	* tree-ssa-sink.cc (sink_common_stores_to_bb): Likewise.

2025-02-03  Andi Kleen  <ak@gcc.gnu.org>

	* input.cc (check_line): New.
	(test_replacement): New function to test line caching.
	(input_cc_tests): Call test_replacement

2025-02-03  Andi Kleen  <ak@gcc.gnu.org>

	PR preprocessor/118168
	* input.cc (file_cache_slot::get_next_line): Implement
	dynamic sizing of m_line_record based on input length.
	* params.opt: (param_file_cache_lines): Set to 0 to size
	dynamically.

2025-02-03  Andi Kleen  <ak@gcc.gnu.org>

	PR preprocessor/118168
	* input.cc (total_lines_num): Remove.
	(file_cache_slot::evict): Ditto.
	(file_cache_slot::create): Ditto.
	(file_cache_slot::set_content): Ditto.
	(file_cache_slot::file_cache_slot): Ditto.
	(file_cache_slot::dump): Ditto.

2025-02-03  Andi Kleen  <ak@gcc.gnu.org>

	PR preprocessor/118168
	* input.cc (file_cache_slot::get_next_line): Use new algorithm
	to maintain
	(file_cache_slot::read_line_num): Use binary search for lookup.

2025-02-03  Andi Kleen  <ak@gcc.gnu.org>

	PR preprocessor/118168
	* input.cc (file_cache::tune): New function.
	* input.h (class file_cache): Make tunables non const.
	* params.opt: Add new tunables.
	* toplev.cc (toplev::main): Initialize input buffer context
	tunables.

2025-02-02  Gaius Mulley  <gaiusmod2@gmail.com>

	PR modula2/117411
	* doc/gm2.texi (Exception handling): New section.
	(The ISO system module): Add description of COFF_T.
	(Assembler language): Tidy up last sentance.

2025-02-02  Lewis Hyatt  <lhyatt@gmail.com>

	PR middle-end/115913
	* optc-save-gen.awk (cl_optimization_compare): Skip options with
	CL_WARNING flag.

2025-02-01  H.J. Lu  <hjl.tools@gmail.com>

	PR target/118713
	* config/i386/i386-expand.cc (ix86_expand_call): Change "if
	(TARGET_X32 ...)" back to "else if (TARGET_X32 ...)".

2025-02-01  H.J. Lu  <hjl.tools@gmail.com>

	PR target/118713
	* config/i386/constraints.md (Bs): Always disable if
	TARGET_INDIRECT_BRANCH_REGISTER is true.
	(Bw): Likewise.
	* config/i386/i386-expand.cc (ix86_expand_call): Force indirect
	call via register for x32 GOT slot call if
	TARGET_INDIRECT_BRANCH_REGISTER is true.
	* config/i386/i386-protos.h (ix86_nopic_noplt_attribute_p): New.
	* config/i386/i386.cc (ix86_nopic_noplt_attribute_p): Make it
	global.
	* config/i386/i386.md (*call_got_x32): Disable indirect call via
	memory for TARGET_INDIRECT_BRANCH_REGISTER.
	(*call_value_got_x32): Likewise.
	(*sibcall_value_pop_memory): Likewise.
	* config/i386/predicates.md (constant_call_address_operand):
	Return false if both TARGET_INDIRECT_BRANCH_REGISTER and
	ix86_nopic_noplt_attribute_p are true.

2025-02-01  David Malcolm  <dmalcolm@redhat.com>

	* libsarifreplay.cc (sarif_replayer::handle_run_obj): Pass run to
	handle_result_obj.
	(sarif_replayer::handle_result_obj): Add run_obj param and pass it
	to handle_location_object and handle_thread_flow_object.
	(sarif_replayer::handle_thread_flow_object): Add run_obj param and
	pass it to handle_thread_flow_location_object.
	(sarif_replayer::handle_thread_flow_location_object): Add run_obj
	param and pass it to handle_location_object.
	(sarif_replayer::handle_location_object): Add run_obj param and
	pass it to handle_logical_location_object.
	(sarif_replayer::handle_logical_location_object): Add run_obj
	param.  If the run_obj is non-null and has "logicalLocations",
	then use these "cached" logical locations if we see an "index"
	property, as per §3.33.3

2025-02-01  Jeff Law  <jlaw@ventanamicro.com>

	PR tree-optimization/114277
	* match.pd (a * (a || b) -> a): New pattern.
	(a * !(a || b) -> 0): Likewise.

2025-01-31  Jakub Jelinek  <jakub@redhat.com>

	PR ipa/117432
	* ipa-icf-gimple.cc (func_checker::compare_asm_inputs_outputs):
	Also return_false if operands have incompatible types.
	(func_checker::compare_gimple_call): Check fntype1 vs. fntype2
	compatibility for all non-internal calls and assume fntype1 and
	fntype2 are non-NULL for those.  For calls to non-prototyped
	calls or for stdarg_p functions after the last named argument (if any)
	check type compatibility of call arguments.

2025-01-31  Vladimir N. Makarov  <vmakarov@redhat.com>

	PR rtl-optimization/116234
	* lra-constraints.cc (multiple_insn_refs_p): New function.
	(curr_insn_transform): Use it.

2025-01-31  Richard Biener  <rguenther@suse.de>

	PR debug/100530
	* dwarf2out.cc (modified_type_die): Do not claim we handle
	address-space qualification with dwarf_qual_info[].

2025-01-31  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/118689
	PR modula2/115032
	* tree-ssa-loop-niter.cc (build_cltz_expr): Return NULL_TREE if fn is
	NULL and use_ifn is false.

2025-01-31  Richard Biener  <rguenther@suse.de>

	* tree-vect-loop.cc (vect_analyze_loop_operations): Only
	call vectorizable_lc_phi when not PURE_SLP.
	(vectorizable_reduction): Do not claim having handled
	the inner loop LC PHI for outer loop vectorization.

2025-01-30  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/builtins.def (STRLEN_FLASH, STRLEN_FLASHX)
	(STRLEN_MEMX): New DEF_BUILTIN's.
	* config/avr/avr.cc (avr_ftype_strlen): New static function.
	(avr_builtin_supported_p): New built-ins are not for AVR_TINY.
	(avr_init_builtins) <strlen_flash_node, strlen_flashx_node,
	strlen_memx_node>: Provide new fntypes.
	(avr_fold_builtin) [AVR_BUILTIN_STRLEN_FLASH]
	[AVR_BUILTIN_STRLEN_FLASHX, AVR_BUILTIN_STRLEN_MEMX]: Fold if
	possible.
	* doc/extend.texi (AVR Built-in Functions): Document
	__builtin_avr_strlen_flash, __builtin_avr_strlen_flashx,
	__builtin_avr_strlen_memx.

2025-01-30  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/builtins.def (AVR_FIRST_C_ONLY_BUILTIN_ID): New macro.
	* config/avr/avr-protos.h (avr_builtin_supported_p): New.
	* config/avr/avr.cc (avr_builtin_supported_p): New function.
	(avr_init_builtins): Only provide a built-in when it is supported.
	* config/avr/avr-c.cc (avr_cpu_cpp_builtins): Only define the
	__BUILTIN_AVR_<NAME> build-in defines when the associated built-in
	function is supported.
	* doc/extend.texi (AVR Built-in Functions): Add a note that
	following built-ins are supported for only for GNU-C.

2025-01-30  Jakub Jelinek  <jakub@redhat.com>
	    Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>

	PR target/118696
	* config/s390/vector.md (*vec_cmpgt<mode><mode>_nocc_emu,
	*vec_cmpgtu<mode><mode>_nocc_emu): Duplicate the first rather than
	second V2DImode element.

2025-01-30  Richard Biener  <rguenther@suse.de>

	PR middle-end/118695
	* expr.cc (expand_expr_real_1): When expanding a MEM_REF
	to a non-MEM by committing it to a stack temporary make
	sure to handle misaligned accesses correctly.

2025-01-30  Tobias Burnus  <tburnus@baylibre.com>

	* gimplify.cc (gimplify_call_expr): For OpenMP's append_args clause
	processed by 'omp dispatch', update for internal-representation
	changes; fix handling of hidden arguments, add some comments and
	handle Fortran's value dummy and optional/pointer/allocatable actual
	args.

2025-01-30  Richard Biener  <rguenther@suse.de>

	PR middle-end/118692
	* expr.cc (expand_expr_real_1): When expanding a MEM_REF
	as BIT_FIELD_REF avoid large offsets for accesses not
	overlapping the base object.

2025-01-30  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114052
	* tree-ssa-loop-niter.cc (maybe_lower_iteration_bound): Check
	for infinite subloops we might not exit.

2025-01-30  Richard Sandiford  <richard.sandiford@arm.com>

	PR rtl-optimization/118320
	* pair-fusion.cc (pair_fusion_bb_info::fuse_pair): Commonize
	the merge of input_uses and return early if it fails.

2025-01-29  Gaius Mulley  <gaiusmod2@gmail.com>

	PR modula2/118010
	PR modula2/118183
	PR modula2/116073
	* doc/gm2.texi (-fm2-file-offset-bits=): Change the default size
	description to CSSIZE_T.
	Add COFF_T to the list of data types exported by SYSTEM.def.

2025-01-29  Richard Sandiford  <richard.sandiford@arm.com>

	PR rtl-optimization/118429
	* pair-fusion.cc (latest_hazard_before): Add an extra parameter
	to say whether the instruction is a load or a store.  If the
	instruction is not a load or store and has memory side effects,
	prevent it from being moved earlier.
	(pair_fusion::find_trailing_add): Update call accordingly.
	(pair_fusion_bb_info::fuse_pair): If the trailng addition had
	a memory side-effect, use a tombstone to preserve it.

2025-01-29  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/avr.md (*negsi2.libgcc): New insn.

2025-01-29  Yoshinori Sato  <ysato@users.sourceforge.jp>

	* config/rx/constraints.md (Q): Also check that the address
	passes rx_is_restricted_memory-address.

2025-01-29  Andrew Pinski  <quic_apinski@quicinc.com>

	PR tree-optimization/118505
	* gimple-ssa-split-paths.cc (poor_ifcvt_pred): Return
	true for trapping statements.

2025-01-29  Andrew Pinski  <quic_apinski@quicinc.com>

	* gimple-ssa-split-paths.cc (poor_ifcvt_candidate_code): Remove CALL_EXPR handling.

2025-01-29  Martin Jambor  <mjambor@suse.cz>
	    Michal Jireš  <mjires@suse.cz>

	PR tree-optimization/117892
	* tree-ssa-dse.cc (dse_optimize_call): Leave control-altering
	noreturn calls alone.

2025-01-29  Pan Li  <pan2.li@intel.com>

	PR target/117688
	* config/riscv/riscv.cc (riscv_expand_sstrunc): Leverage the helper
	riscv_extend_to_xmode_reg with SIGN_EXTEND.

2025-01-29  Pan Li  <pan2.li@intel.com>

	PR target/117688
	* config/riscv/riscv.cc (riscv_expand_sssub): Leverage the helper
	riscv_extend_to_xmode_reg with SIGN_EXTEND.

2025-01-29  Pan Li  <pan2.li@intel.com>

	PR target/117688
	* config/riscv/riscv.cc (riscv_expand_ssadd): Leverage the helper
	riscv_extend_to_xmode_reg with SIGN_EXTEND.

2025-01-29  Pan Li  <pan2.li@intel.com>

	* config/riscv/riscv.cc (riscv_gen_zero_extend_rtx): Rename from ...
	(riscv_extend_to_xmode_reg): Rename to and add rtx_code for
	zero/sign extend if non-Xmode.
	(riscv_expand_usadd): Leverage the renamed function with ZERO_EXTEND.
	(riscv_expand_ussub): Ditto.

2025-01-29  Richard Biener  <rguenther@suse.de>

	PR middle-end/118684
	* expr.cc (expand_expr_real_1): When creating a stack local
	during expansion of a handled component, when the base is
	a SSA_NAME use its type alignment and avoid calling
	get_object_alignment.

2025-01-28  Richard Biener  <rguenther@suse.de>

	PR middle-end/118684
	* expr.cc (expand_expr_real_1): When expanding a reference
	based on a register and we end up needing a MEM make sure
	that's aligned as the original reference required.

2025-01-28  David Malcolm  <dmalcolm@redhat.com>

	* input.cc (file_cache_slot::dump): Show indices within
	m_line_record when dumping entries.

2025-01-28  David Malcolm  <dmalcolm@redhat.com>

	PR other/118675
	* diagnostic-format-sarif.cc: Define INCLUDE_STRING.
	(escape_braces): New.
	(set_string_property_escaping_braces): New.
	(sarif_builder::make_message_object): Escape braces in the "text"
	property.
	(sarif_builder::make_message_object_for_diagram): Likewise, and
	for the "markdown" property.
	(sarif_builder::make_multiformat_message_string): Likewise for the
	"text" property.
	(xelftest::test_message_with_braces): New.
	(selftest::diagnostic_format_sarif_cc_tests): Call it.

2025-01-28  Richard Sandiford  <richard.sandiford@arm.com>

	PR tree-optimization/117270
	* tree-vect-slp.cc (vectorizable_slp_permutation_1): Make nperms
	account for the number of times that each permutation will be used
	during transformation.

2025-01-28  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/112859
	* tree-loop-distribution.cc
	(loop_distribution::pg_add_dependence_edges): Add comment.

2025-01-28  Vladimir N. Makarov  <vmakarov@redhat.com>

	PR target/118663
	* lra-constraints.cc (invalid_mode_reg_p): Check empty
	reg_class_contents.

2025-01-28  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/117424
	* tree-eh.cc (tree_could_trap_p): Verify the base is
	fully contained within a decl.

2025-01-28  Thomas Schwinge  <tschwinge@baylibre.com>

	* tree-pretty-print.cc (dump_omp_clause): Clarify
	'OMP_CLAUSE_MAP_RUNTIME_IMPLICIT_P'.

2025-01-28  Jakub Jelinek  <jakub@redhat.com>

	PR rtl-optimization/118638
	* combine.cc (make_extraction): Only optimize (mult x 2^n) if len is
	larger than 1.

2025-01-28  Richard Sandiford  <richard.sandiford@arm.com>

	* tree-vect-slp.cc (vectorizable_slp_permutation_1): Remove
	extra newline from dump message.

2025-01-28  Jeff Law  <jlaw@ventanamicro.com>

	PR target/114085
	* config/h8300/constraints.md (U): No longer accept REGs.
	* config/h8300/logical.md (andqi3_2): Use "rU" rather than "U".
	(andqi3_2_clobber_flags, andqi3_1, <code>qi3_1): Likewise.
	* config/h8300/testcompare.md (tst_extzv_1_n): Likewise.

2025-01-27  Robin Dapp  <rdapp@ventanamicro.com>

	PR target/117173
	* config/riscv/riscv-v.cc (shuffle_generic_patterns): Only
	support single-source permutes by default.
	* config/riscv/riscv.opt: New param "riscv-two-source-permutes".

2025-01-27  John David Anglin  <danglin@gcc.gnu.org>

	PR c++/116524
	* configure.ac: Check for munmap and msync.
	* configure: Regenerate.
	* config.in: Regenerate.

2025-01-27  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/118653
	* tree-vect-loop.cc (vectorizable_live_operation): Also allow
	out-of-loop debug uses.

2025-01-27  Richard Biener  <rguenther@suse.de>

	PR rtl-optimization/118662
	* combine.cc (try_combine): When re-materializing a load
	from an extended reg by a lowpart subreg make sure we're
	not dealing with vector or complex modes.

2025-01-27  Richard Biener  <rguenther@suse.de>

	PR middle-end/118643
	* expr.cc (expand_expr_real_1): Avoid falling back to BIT_FIELD_REF
	expansion for negative offset.

2025-01-27  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/112859
	PR tree-optimization/115347
	* tree-loop-distribution.cc
	(loop_distribution::pg_add_dependence_edges): For a zero
	distance vector still make sure to not have an inner
	loop with zero distance.

2025-01-27  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/118637
	* match.pd: Canonicalize unsigned division by power of two to
	right shift.

2025-01-27  Soumya AR  <soumyaa@nvidia.com>

	PR target/118490
	* match.pd: Added ! to verify that log/exp (CST) can be constant folded.

2025-01-26  Ilya Leoshkevich  <iii@linux.ibm.com>

	* asan.cc (asan_emit_stack_protection): Always zero the flag
	unless it is cleared by the __asan_stack_free_N() libcall.

2025-01-26  Pan Li  <pan2.li@intel.com>

	PR target/118103
	* config/riscv/riscv.cc (riscv_conditional_register_usage): Add
	the FRM as the global_regs.

2025-01-25  Andi Kleen  <ak@gcc.gnu.org>

	PR preprocessor/118168
	* input.cc (file_cache_slot::m_error): New field.
	(file_cache_slot::create): Clear m_error.
	(file_cache_slot::file_cache_slot): Clear m_error.
	(file_cache_slot::read_data): Set m_error on error.
	(file_cache_slot::get_next_line): Use m_error instead of ferror.

2025-01-25  Jeff Law  <jlaw@ventanamicro.com>

	PR target/116256
	* config/riscv/riscv.md (mvconst_internal): Reject single bit
	constants.
	* config/riscv/riscv.cc (riscv_gen_zero_extend_rtx): Improve
	handling constants.

2025-01-24  Andrew Carlotti  <andrew.carlotti@arm.com>

	* config/aarch64/aarch64-arches.def (V9_5A): Add CPA.
	* config/aarch64/aarch64-option-extensions.def (CPA): New.
	* doc/invoke.texi: Document +cpa.

2025-01-24  Andrew Carlotti  <andrew.carlotti@arm.com>

	* doc/invoke.texi: Add +wfxt and +xs to armv9.2-a

2025-01-24  Andrew Carlotti  <andrew.carlotti@arm.com>

	* config/aarch64/aarch64-arches.def (V9_5A): New.
	* doc/invoke.texi: Document armv9.5-a option.

2025-01-24  Andrew Carlotti  <andrew.carlotti@arm.com>

	* common/config/aarch64/aarch64-common.cc: Assert that CRYPTO
	bit is not set.
	* config/aarch64/aarch64-feature-deps.h
	(info<FEAT>.explicit_on): Unset CRYPTO bit.
	(cpu_##CORE_IDENT): Ditto.

2025-01-24  Andrew Carlotti  <andrew.carlotti@arm.com>

	* common/config/aarch64/aarch64-common.cc
	(aarch64_rewrite_selected_cpu): Refactor and inline into...
	(aarch64_rewrite_mcpu): this.
	* config/aarch64/aarch64-protos.h
	(aarch64_rewrite_selected_cpu): Delete.

2025-01-24  Andrew Carlotti  <andrew.carlotti@arm.com>

	* common/config/aarch64/aarch64-common.cc
	(aarch64_get_arch_string_for_assembler): New.
	(aarch64_rewrite_march): New.
	(aarch64_rewrite_selected_cpu): Call new function.
	* config/aarch64/aarch64-elf.h (ASM_SPEC): Remove identity mapping.
	* config/aarch64/aarch64-protos.h
	(aarch64_get_arch_string_for_assembler): New.
	* config/aarch64/aarch64.cc
	(aarch64_declare_function_name): Call new function.
	(aarch64_start_file): Ditto.
	* config/aarch64/aarch64.h
	(EXTRA_SPEC_FUNCTIONS): Use new macro name.
	(MCPU_TO_MARCH_SPEC): Rename to...
	(MARCH_REWRITE_SPEC): ...this, and extend the spec rule.
	(aarch64_rewrite_march): New declaration.
	(MCPU_TO_MARCH_SPEC_FUNCTIONS): Rename to...
	(AARCH64_BASE_SPEC_FUNCTIONS): ...this, and add new function.
	(ASM_CPU_SPEC): Use new macro name.

2025-01-24  Andrew Carlotti  <andrew.carlotti@arm.com>

	* common/config/aarch64/aarch64-common.cc
	(aarch64_get_all_extension_candidates): Inline into...
	(aarch64_print_hint_for_extensions): ...this.

2025-01-24  Andrew Carlotti  <andrew.carlotti@arm.com>

	* common/config/aarch64/aarch64-common.cc
	(aarch64_get_all_extension_candidates): Move within file.
	(aarch64_print_hint_candidates): Move from aarch64.cc.
	(aarch64_print_hint_for_extensions): Ditto.
	(aarch64_print_hint_for_arch): Ditto.
	(aarch64_print_hint_for_core): Ditto.
	(enum aarch_parse_opt_result): Ditto.
	(aarch64_parse_arch): Ditto.
	(aarch64_parse_cpu): Ditto.
	(aarch64_parse_tune): Ditto.
	(aarch64_validate_march): Ditto.
	(aarch64_validate_mcpu): Ditto.
	(aarch64_validate_mtune): Ditto.
	* config/aarch64/aarch64-protos.h
	(aarch64_rewrite_selected_cpu): Move within file.
	(aarch64_print_hint_for_extensions): Share function prototype.
	(aarch64_print_hint_for_arch): Ditto.
	(aarch64_print_hint_for_core): Ditto.
	(enum aarch_parse_opt_result): Ditto.
	(aarch64_validate_march): Ditto.
	(aarch64_validate_mcpu): Ditto.
	(aarch64_validate_mtune): Ditto.
	(aarch64_get_all_extension_candidates): Unshare prototype.
	* config/aarch64/aarch64.cc
	(aarch64_parse_arch): Move to aarch64-common.cc.
	(aarch64_parse_cpu): Ditto.
	(aarch64_parse_tune): Ditto.
	(aarch64_print_hint_candidates): Ditto.
	(aarch64_print_hint_for_core): Ditto.
	(aarch64_print_hint_for_arch): Ditto.
	(aarch64_print_hint_for_extensions): Ditto.
	(aarch64_validate_mcpu): Ditto.
	(aarch64_validate_march): Ditto.
	(aarch64_validate_mtune): Ditto.

2025-01-24  Andrew Carlotti  <andrew.carlotti@arm.com>

	* config/aarch64/aarch64.cc
	(aarch64_print_hint_candidates): New helper function.
	(aarch64_print_hint_for_core_or_arch): Inline into callers.
	(aarch64_print_hint_for_core): Inline callee and use new helper.
	(aarch64_print_hint_for_arch): Ditto.
	(aarch64_print_hint_for_extensions): Use new helper.

2025-01-24  Andrew Carlotti  <andrew.carlotti@arm.com>

	* config/aarch64/aarch64.cc
	(aarch64_print_hint_for_extensions): Receive string as a char *.
	(aarch64_parse_arch): Don't return a const struct processor *.
	(aarch64_parse_cpu): Ditto.
	(aarch64_parse_tune): Ditto.
	(aarch64_validate_mtune): Ditto.
	(aarch64_validate_mcpu): Ditto, and use temporary variables for
	march/mcpu cross-check.
	(aarch64_validate_march): Ditto.
	(aarch64_override_options): Adjust for changed parameter types.
	(aarch64_handle_attr_arch): Ditto.
	(aarch64_handle_attr_cpu): Ditto.
	(aarch64_handle_attr_tune): Ditto.

2025-01-24  Andrew Carlotti  <andrew.carlotti@arm.com>

	* common/config/aarch64/aarch64-common.cc
	(struct aarch64_option_extension): Rename to..
	(struct aarch64_extension_info): ...this.
	(all_extensions): Update type name.
	(struct arch_to_arch_name): Rename to...
	(struct aarch64_arch_info): ...this, and rename name field.
	(all_architectures): Update type names, and move before...
	(struct processor_name_to_arch): ...this. Rename to...
	(struct aarch64_processor_info): ...this, rename name field and
	add cpu field.
	(all_cores): Update type name, and set new field.
	(aarch64_parse_extension): Update names.
	(aarch64_get_all_extension_candidates): Ditto.
	(aarch64_rewrite_selected_cpu): Ditto.

2025-01-24  Andrew Carlotti  <andrew.carlotti@arm.com>

	* common/config/aarch64/aarch64-common.cc
	(all_cores): Remove explicit generic entry.

2025-01-24  Andrew Carlotti  <andrew.carlotti@arm.com>

	* config/aarch64/aarch64-opts.h
	(enum aarch64_processor): Rename to...
	(enum aarch64_cpu): ...this, and rename the entries.
	* config/aarch64/aarch64.cc
	(aarch64_type): Rename type and initial value.
	(struct processor): Rename member types.
	(all_architectures): Rename enum members.
	(all_cores): Ditto.
	(aarch64_get_tune_cpu): Rename type and enum member.
	* config/aarch64/aarch64.h (enum target_cpus): Remove.
	(TARGET_CPU_DEFAULT): Rename default value.
	(aarch64_tune): Rename type.
	* config/aarch64/aarch64.opt:
	(selected_tune): Rename type and default value.

2025-01-24  Andrew Carlotti  <andrew.carlotti@arm.com>

	* config/aarch64/aarch64.cc (aarch64_override_options): Compare
	returned feature masks directly.

2025-01-24  Vladimir N. Makarov  <vmakarov@redhat.com>

	PR target/118497
	* ira-int.h (target_ira_int): Add x_ira_hard_regno_nrefs.
	(ira_hard_regno_nrefs): New macro.
	* ira.cc (setup_hard_regno_aclass): Remove unused code.  Modify
	the comment.
	(setup_hard_regno_nrefs): New function.
	(ira): Call it.
	* ira-color.cc (calculate_saved_nregs): Check
	ira_hard_regno_nrefs.

2025-01-24  yxj-github-437  <2457369732@qq.com>

	* config/aarch64/aarch64.cc (aarch64_build_builtin_va_list): Mark
	__builtin_va_list as TREE_PUBLIC.
	* config/arm/arm.cc (arm_build_builtin_va_list): Likewise.

2025-01-24  David Malcolm  <dmalcolm@redhat.com>

	PR sarif-replay/117670
	* Makefile.in (SARIF_REPLAY_INSTALL_NAME): New.
	(install-libgdiagnostics): Use it,and exeext, rather than just
	sarif-replay.

2025-01-24  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/116010
	* tree-data-ref.cc (contains_ssa_ref_p_1): New function.
	(contains_ssa_ref_p): Likewise.
	(dr_may_alias_p): Avoid treating unanalyzed base parts without
	SSA reference conservatively.

2025-01-24  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>

	* config/s390/s390.h (S390_TDC_POSITIVE_ZERO): Remove.
	(S390_TDC_NEGATIVE_ZERO): Remove.
	(S390_TDC_POSITIVE_NORMALIZED_BFP_NUMBER): Remove.
	(S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER): Remove.
	(S390_TDC_POSITIVE_DENORMALIZED_BFP_NUMBER): Remove.
	(S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER): Remove.
	(S390_TDC_POSITIVE_INFINITY): Remove.
	(S390_TDC_NEGATIVE_INFINITY): Remove.
	(S390_TDC_POSITIVE_QUIET_NAN): Remove.
	(S390_TDC_NEGATIVE_QUIET_NAN): Remove.
	(S390_TDC_POSITIVE_SIGNALING_NAN): Remove.
	(S390_TDC_NEGATIVE_SIGNALING_NAN): Remove.
	(S390_TDC_POSITIVE_DENORMALIZED_DFP_NUMBER): Remove.
	(S390_TDC_NEGATIVE_DENORMALIZED_DFP_NUMBER): Remove.
	(S390_TDC_POSITIVE_NORMALIZED_DFP_NUMBER): Remove.
	(S390_TDC_NEGATIVE_NORMALIZED_DFP_NUMBER): Remove.
	(S390_TDC_SIGNBIT_SET): Remove.
	(S390_TDC_INFINITY): Remove.
	* config/s390/s390.md (signbit<mode>2<tf_fpr>): Merge this one
	(isinf<mode>2<tf_fpr>): and this one into
	(<TDC_CLASS:tdc_insn><mode>2<tf_fpr>): new expander.
	(isnormal<mode>2<tf_fpr>): New BFP expander.
	(isnormal<mode>2): New DFP expander.
	* config/s390/vector.md (signbittf2_vr): Merge this one
	(isinftf2_vr): and this one into
	(<tdc_insn>tf2_vr): new expander.
	(signbittf2): Merge this one
	(isinftf2): and this one into
	(<tdc_insn>tf2): new expander.

2025-01-24  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/118634
	* tree-ssa-loop-ivcanon.cc (try_unroll_loop_completely):
	Dump the number of estimated eliminated insns.

2025-01-24  Saurabh Jha  <saurabh.jha@arm.com>

	* config/aarch64/aarch64-sve2.md:
	(*aarch64_pred_faminmax_fused): Fix to use the correct flags.
	* config/aarch64/aarch64.h
	(TARGET_SVE_FAMINMAX): Remove.
	* config/aarch64/iterators.md: Fix iterators so that famax and
	famin use correct flags.

2025-01-24  Alexandre Oliva  <oliva@adacore.com>

	PR tree-optimization/118572
	* gimple-fold.cc (fold_truth_andor_for_ifcombine): Compare as
	unsigned the variables whose extension bits are masked out.

2025-01-24  Alexandre Oliva  <oliva@adacore.com>

	* gimple-fold.cc (fold_truth_andor_for_ifcombine): Document
	reversep's absence of effects on range tests.  Don't reject
	reversep mismatches before trying compare swapping.

2025-01-24  Alexandre Oliva  <oliva@adacore.com>

	PR tree-optimization/118514
	* tree-eh.cc (bit_field_ref_in_bounds_p): New.
	(tree_could_trap_p) <BIT_FIELD_REF>: Call it.
	* gimple-fold.cc (make_bit_field_load): Check trapping status
	of replacement load against original load.

2025-01-23  John David Anglin  <danglin@gcc.gnu.org>

	* config/pa/pa32-regs.h (ADDITIONAL_REGISTER_NAMES): Change
	register 86 name to "%fr31L".

2025-01-23  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/118628
	* tree-vect-stmts.cc (vectorizable_store, vectorizable_load):
	Initialize offvar to NULL_TREE.

2025-01-23  Georg-Johann Lay  <avr@gjlay.de>

	PR tree-optimization/118012
	PR tree-optimization/118360
	* config/avr/avr.opt (-mpr118012): New undocumented option.
	* config/avr/avr-protos.h (avr_out_sextr)
	(avr_emit_skip_pixop, avr_emit_skip_clear): New protos.
	* config/avr/avr.cc (avr_adjust_insn_length)
	[case ADJUST_LEN_SEXTR]: Handle case.
	(avr_rtx_costs_1) [NEG]: Costs for NEG (ZERO_EXTEND (ZERO_EXTRACT)).
	[MULT && avropt_pr118012]: Costs for MULT (x AND 1).
	(avr_out_sextr, avr_emit_skip_pixop, avr_emit_skip_clear): New
	functions.
	* config/avr/avr.md [avropt_pr118012]: Add combine patterns with
	that condition that try to work around PR118012.
	(adjust_len) <sextr>: Add insn attr value.
	(pixop): New code iterator.
	(mulsi3) [avropt_pr118012 && !AVR_TINY]: Allow these in insn condition.

2025-01-23  Richard Sandiford  <richard.sandiford@arm.com>

	PR rtl-optimization/118562
	* rtl-ssa/blocks.cc (function_info::replace_phi): When converting
	to a degenerate phi, make sure to remove all uses of the previous
	inputs.

2025-01-23  Richard Sandiford  <richard.sandiford@arm.com>

	* config/aarch64/aarch64-tuning-flags.def
	(AARCH64_EXTRA_TUNE_CHEAP_FPMR_WRITE): New tuning flag.
	* config/aarch64/aarch64.h (TARGET_CHEAP_FPMR_WRITE): New macro.
	* config/aarch64/aarch64.md: Split moves into FPMR into a test
	and branch around.
	(aarch64_write_fpmr): New pattern.

2025-01-23  Richard Sandiford  <richard.sandiford@arm.com>

	* config/aarch64/aarch64.cc (aarch64_memory_move_cost): Account
	for the cost of moving in and out of GENERAL_SYSREGS.

2025-01-23  Richard Sandiford  <richard.sandiford@arm.com>

	* config/aarch64/aarch64.md (*mov<SHORT:mode>_aarch64)
	(*movsi_aarch64, *movdi_aarch64): Allow the source of an MSR
	to be zero.

2025-01-23  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/118605
	* tree-assume.cc (assume_query::m_parm_list): Change type
	from bitmap & to bitmap.

2025-01-23  Tejas Belagod  <tejas.belagod@arm.com>

	* omp-low.cc (use_pointer_for_field): Use pointer if the OMP data
	structure's field type is a poly-int.

2025-01-23  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/114877
	* builtins.cc (fold_builtin_frexp): Handle rvc_nan and rvc_inf cases
	like rvc_zero, return passed in arg and set *exp = 0.

2025-01-23  Torbjörn SVENSSON  <torbjorn.svensson@foss.st.com>

	* doc/sourcebuild.texi (Effective-Target Keywords): Document
	'alarm'.

2025-01-23  Georg-Johann Lay  <avr@gjlay.de>

	PR target/117726
	* config/avr/avr.cc (avr_ld_regno_p): New function.
	(ashlsi3_out) [case 25,26,27,28,29,30]: Handle and tweak.
	(lshrsi3_out): Same.
	(avr_rtx_costs_1) [SImode, ASHIFT, LSHIFTRT]: Adjust costs.
	* config/avr/avr.md (ashlsi3, *ashlsi3, *ashlsi3_const):
	Add "r,r,C4L" alternative.
	(lshrsi3, *lshrsi3, *lshrsi3_const): Add "r,r,C4R" alternative.
	* config/avr/constraints.md (C4R, C4L): New,

2025-01-23  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/118558
	* tree-vectorizer.h (vect_known_alignment_in_bytes): Pass
	through offset to dr_misalignment.
	* tree-vect-stmts.cc (get_group_load_store_type): Compute
	offset applied for negative stride and use it when querying
	alignment of accesses.
	(vectorizable_load): Likewise.

2025-01-23  Nathaniel Shead  <nathanieloshead@gmail.com>

	PR c++/107741
	* common.opt: Add -fabi-version=20.
	* doc/invoke.texi: Likewise.

2025-01-23  Xi Ruoyao  <xry111@xry111.site>

	PR target/118501
	* config/loongarch/loongarch.md (@xorsign<mode>3): Use
	force_lowpart_subreg.

2025-01-23  Haochen Jiang  <haochen.jiang@intel.com>

	* config/i386/avx10_2-512convertintrin.h:
	Omit "p" for packed for FP8.
	* config/i386/avx10_2convertintrin.h: Ditto.

2025-01-23  Haochen Jiang  <haochen.jiang@intel.com>

	PR target/118270
	* config/i386/avx10_2-512satcvtintrin.h: Change intrin and
	builtin name according to new mnemonics.
	* config/i386/avx10_2satcvtintrin.h: Ditto.
	* config/i386/i386-builtin.def (BDESC): Ditto.
	* config/i386/sse.md
	(UNSPEC_VCVTBF162IBS): Rename from UNSPEC_VCVTNEBF162IBS.
	(UNSPEC_VCVTBF162IUBS): Rename from UNSPEC_VCVTNEBF162IUBS.
	(UNSPEC_VCVTTBF162IBS): Rename from UNSPEC_VCVTTNEBF162IBS.
	(UNSPEC_VCVTTBF162IUBS): Rename from UNSPEC_VCVTTNEBF162IUBS.
	(UNSPEC_CVTNE_BF16_IBS_ITER): Rename to...
	(UNSPEC_CVT_BF16_IBS_ITER): ...this. Adjust UNSPEC name.
	(sat_cvt_sign_prefix): Adjust UNSPEC name.
	(sat_cvt_trunc_prefix): Ditto.
	(avx10_2_cvt<sat_cvt_trunc_prefix>nebf162i<sat_cvt_sign_prefix>bs<mode><mask_name>):
	Rename to...
	(avx10_2_cvt<sat_cvt_trunc_prefix>bf162i<sat_cvt_sign_prefix>bs<mode><mask_name>):
	...this. Change instruction name output.

2025-01-23  Haochen Jiang  <haochen.jiang@intel.com>

	PR target/118270
	* config/i386/avx10_2-512convertintrin.h: Change intrin and
	builtin name according to new mnemonics.
	* config/i386/avx10_2convertintrin.h: Ditto.
	* config/i386/i386-builtin.def (BDESC): Ditto.
	* config/i386/sse.md
	(UNSPEC_VCVTPH2BF8): Rename from UNSPEC_VCVTNEPH2BF8.
	(UNSPEC_VCVTPH2BF8S): Rename from UNSPEC_VCVTNEPH2BF8S.
	(UNSPEC_VCVTPH2HF8): Rename from UNSPEC_VCVTNEPH2HF8.
	(UNSPEC_VCVTPH2HF8S): Rename from UNSPEC_VCVTNEPH2HF8S.
	(UNSPEC_CONVERTPH2FP8): Rename from UNSPEC_NECONVERTPH2FP8.
	Adjust UNSPEC name.
	(convertph2fp8): Rename from neconvertph2fp8. Adjust
	iterator map.
	(vcvt<neconvertph2fp8>v8hf): Rename to...
	(vcvt<neconvertph2fp8>v8hf): ...this.
	(*vcvt<neconvertph2fp8>v8hf): Rename to...
	(*vcvt<neconvertph2fp8>v8hf): ...this.
	(vcvt<neconvertph2fp8>v8hf_mask): Rename to...
	(vcvt<neconvertph2fp8>v8hf_mask): ...this.
	(*vcvt<neconvertph2fp8>v8hf_mask): Rename to...
	(*vcvt<neconvertph2fp8>v8hf_mask): ...this.
	(vcvt<neconvertph2fp8><mode><mask_name>): Rename to...
	(vcvt<convertph2fp8><mode><mask_name>): ...this.

2025-01-23  Haochen Jiang  <haochen.jiang@intel.com>

	PR target/118270
	* config/i386/avx10_2-512convertintrin.h: Change intrin and
	builtin name according to new mnemonics.
	* config/i386/avx10_2convertintrin.h: Ditto.
	* config/i386/i386-builtin.def (BDESC): Ditto.
	* config/i386/sse.md
	(UNSPEC_VCVT2PH2BF8): Rename from UNSPEC_VCVTNE2PH2BF8.
	(UNSPEC_VCVT2PH2BF8S): Rename from UNSPEC_VCVTNE2PH2BF8S.
	(UNSPEC_VCVT2PH2HF8): Rename from UNSPEC_VCVTNE2PH2HF8.
	(UNSPEC_VCVT2PH2HF8S): Rename from UNSPEC_VCVTNE2PH2HF8S.
	(UNSPEC_CONVERTFP8_PACK): Rename from UNSPEC_NECONVERTFP8_PACK.
	Adjust UNSPEC name.
	(convertfp8_pack): Rename from neconvertfp8_pack. Adjust
	iterator map.
	(vcvt<neconvertfp8_pack><mode><mask_name>): Rename to...
	(vcvt<convertfp8_pack><mode><mask_name>): ...this.

2025-01-23  Haochen Jiang  <haochen.jiang@intel.com>

	PR target/118270
	* config/i386/avx10_2bf16intrin.h: Change intrin and builtin
	name according to new mnemonics.
	* config/i386/i386-builtin.def (BDESC): Ditto.
	* config/i386/i386-expand.cc
	(ix86_expand_fp_compare): Adjust comments.
	(ix86_expand_builtin): Adjust switch case.
	* config/i386/i386.md (cmpibf): Change instruction name output.
	* config/i386/sse.md (UNSPEC_VCOMSBF16): Removed.
	(avx10_2_comisbf16_v8bf): New.
	(avx10_2_comsbf16_v8bf): Removed.

2025-01-23  Haochen Jiang  <haochen.jiang@intel.com>

	PR target/118270
	* config/i386/avx10_2-512bf16intrin.h: Change intrin and builtin
	name according to new mnemonics.
	* config/i386/avx10_2bf16intrin.h: Ditto.
	* config/i386/i386-builtin.def (BDESC): Ditto.
	* config/i386/sse.md
	(UNSPEC_VFPCLASSBF16); Rename from UNSPEC_VFPCLASSPBF16.
	(avx10_2_getexppbf16_<mode><mask_name>): Rename to...
	(avx10_2_getexpbf16_<mode><mask_name>): ...this.
	Change instruction name output.
	(avx10_2_fpclasspbf16_<mode><mask_scalar_merge_name>):
	Rename to...
	(avx10_2_fpclassbf16_<mode><mask_scalar_merge_name>): ...this.
	Change instruction name output.

2025-01-23  Haochen Jiang  <haochen.jiang@intel.com>

	PR target/118270
	* config/i386/avx10_2-512bf16intrin.h: Change intrin and builtin
	name according to new mnemonics.
	* config/i386/avx10_2bf16intrin.h: Ditto.
	* config/i386/i386-builtin.def (BDESC): Ditto.
	* config/i386/sse.md
	(UNSPEC_VSCALEFBF16): Rename from UNSPEC_VSCALEFPBF16.
	(avx10_2_scalefpbf16_<mode><mask_name>): Rename to...
	(avx10_2_scalefbf16_<mode><mask_name>): ...this.
	Change instruction name output.
	(avx10_2_rsqrtpbf16_<mode><mask_name>): Rename to...
	(avx10_2_rsqrtbf16_<mode><mask_name>): ...this.
	Change instruction name output.
	(avx10_2_sqrtnepbf16_<mode><mask_name>): Rename to...
	(avx10_2_sqrtbf16_<mode><mask_name>): ...this.
	Change instruction name output.

2025-01-23  Haochen Jiang  <haochen.jiang@intel.com>

	PR target/118270
	* config/i386/avx10_2-512bf16intrin.h: Change intrin and builtin
	name according to new mnemonics.
	* config/i386/avx10_2bf16intrin.h: Ditto.
	* config/i386/i386-builtin.def (BDESC): Ditto.
	* config/i386/sse.md
	(UNSPEC_VRNDSCALEBF16): Rename from UNSPEC_VRNDSCALENEPBF16.
	(UNSPEC_VREDUCEBF16): Rename from UNSPEC_VREDUCENEPBF16.
	(UNSPEC_VGETMANTBF16): Rename from UNSPEC_VGETMANTPBF16.
	(BF16IMMOP): Adjust iterator due to UNSPEC name change.
	(bf16immop): Ditto.
	(avx10_2_<bf16immop>pbf16_<mode><mask_name>): Rename to...
	(avx10_2_<bf16immop>bf16_<mode><mask_name>): ...this. Change
	instruction name output.

2025-01-23  Haochen Jiang  <haochen.jiang@intel.com>

	PR target/118270
	* config/i386/avx10_2-512minmaxintrin.h: Change intrin and
	builtin name according to new mnemonics.
	* config/i386/avx10_2minmaxintrin.h: Ditto.
	* config/i386/i386-builtin.def (BDESC): Ditto.
	* config/i386/sse.md
	(UNSPEC_MINMAXBF16): Rename from UNSPEC_MINMAXNEPBF16.
	(avx10_2_minmaxnepbf16_<mode><mask_name>): Rename to...
	(avx10_2_minmaxbf16_<mode><mask_name>): ...this. Change
	instruction name output.

2025-01-23  Haochen Jiang  <haochen.jiang@intel.com>

	PR target/118270
	* config/i386/avx10_2-512bf16intrin.h: Change intrin and builtin
	name according to new mnemonics.
	* config/i386/avx10_2bf16intrin.h: Ditto.
	* config/i386/i386-builtin.def (BDESC): Ditto.
	* config/i386/sse.md
	(avx10_2_<code>pbf16_<mode><mask_name>): Rename to...
	(avx10_2_<code>bf16_<mode><mask_name>): ...this.
	Change instruction name output.
	(avx10_2_cmppbf16_<mode><mask_scalar_merge_name>): Rename to...
	(avx10_2_cmpbf16_<mode><mask_scalar_merge_name>): ...this.
	Change instruction name output.

2025-01-23  Haochen Jiang  <haochen.jiang@intel.com>

	PR target/118270
	* config/i386/avx10_2-512bf16intrin.h: Change intrin and builtin
	names according to new mnemonics.
	* config/i386/avx10_2bf16intrin.h: Ditto.
	* config/i386/i386-builtin.def (BDESC): Ditto.
	* config/i386/sse.md
	(avx10_2_fmaddnepbf16_<mode>_maskz): Rename to...
	(avx10_2_fmaddbf16_<mode>_maskz): ...this. Adjust emit_insn.
	(avx10_2_fmaddnepbf16_<mode><sd_maskz_name>): Rename to...
	(avx10_2_fmaddbf16_<mode><sd_maskz_name>): ...this.
	Change instruction name output.
	(avx10_2_fmaddnepbf16_<mode>_mask): Rename to...
	(avx10_2_fmaddbf16_<mode>_mask): ...this.
	Change instruction name output.
	(avx10_2_fmaddnepbf16_<mode>_mask3): Rename to...
	(avx10_2_fmaddbf16_<mode>_mask3): ...this.
	Change instruction name output.
	(avx10_2_fnmaddnepbf16_<mode>_maskz): Rename to...
	(avx10_2_fnmaddbf16_<mode>_maskz): ...this. Adjust emit_insn.
	(avx10_2_fnmaddnepbf16_<mode><sd_maskz_name>): Rename to...
	(avx10_2_fnmaddbf16_<mode><sd_maskz_name>): ...this.
	Change instruction name output.
	(avx10_2_fnmaddnepbf16_<mode>_mask): Rename to...
	(avx10_2_fnmaddbf16_<mode>_mask): ...this.
	Change instruction name output.
	(avx10_2_fnmaddnepbf16_<mode>_mask3): Rename to...
	(avx10_2_fnmaddbf16_<mode>_mask3): ...this.
	Change instruction name output.
	(avx10_2_fmsubnepbf16_<mode>_maskz): Rename to...
	(avx10_2_fmsubbf16_<mode>_maskz): ...this. Adjust emit_insn.
	(avx10_2_fmsubnepbf16_<mode><sd_maskz_name>): Rename to...
	(avx10_2_fmsubbf16_<mode><sd_maskz_name>): ...this.
	Change instruction name output.
	(avx10_2_fmsubnepbf16_<mode>_mask): Rename to...
	(avx10_2_fmsubbf16_<mode>_mask): ...this.
	Change instruction name output.
	(avx10_2_fmsubnepbf16_<mode>_mask3): Rename to...
	(avx10_2_fmsubbf16_<mode>_mask3): ...this.
	Change instruction name output.
	(avx10_2_fnmsubnepbf16_<mode>_maskz): Rename to...
	(avx10_2_fnmsubbf16_<mode>_maskz): ...this. Adjust emit_insn.
	(avx10_2_fnmsubnepbf16_<mode><sd_maskz_name>): Rename to...
	(avx10_2_fnmsubbf16_<mode><sd_maskz_name>): ...this.
	Change instruction name output.
	(avx10_2_fnmsubnepbf16_<mode>_mask): Rename to...
	(avx10_2_fnmsubbf16_<mode>_mask): ...this.
	Change instruction name output.
	(avx10_2_fnmsubnepbf16_<mode>_mask3): Rename to...
	(avx10_2_fnmsubbf16_<mode>_mask3): ...this.
	Change instruction name output.

2025-01-23  Haochen Jiang  <haochen.jiang@intel.com>

	PR target/118270
	* config/i386/avx10_2-512bf16intrin.h: Change intrin and builtin
	name according to new mnemonics.
	* config/i386/avx10_2bf16intrin.h: Ditto.
	* config/i386/i386-builtin.def (BDESC): Ditto.
	* config/i386/sse.md (div<mode>3): Adjust emit_insn.
	(avx10_2_<insn>nepbf16_<mode><mask_name>): Rename to...
	(avx10_2_<insn>bf16_<mode><mask_name>): ...this. Change
	instruction name output.
	(avx10_2_rcppbf16_<mode><mask_name>): Rename to...
	(avx10_2_rcpbf16_<mode><mask_name>):...this. Change
	instruction name output.

2025-01-22  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>

	* config/s390/s390.cc: Fix arch15 machine string which must not
	be empty.

2025-01-22  Richard Sandiford  <richard.sandiford@arm.com>

	* config/aarch64/aarch64.md (aarch64_read_sysregti): Change
	the source predicate to aarch64_reg_or_zero.

2025-01-22  Xi Ruoyao  <xry111@xry111.site>

	* config/loongarch/loongarch.md
	(<optab>_alsl_reversesi_extended): Add '&' to the destination
	register constraint and append '0' to the first source register
	constraint to indicate the destination register cannot be same
	as the second source register, and change the split condition to
	reload_completed so that the insn will be split only after RA in
	order to obtain allocated registers that satisfy the above
	constraints.

2025-01-21  Jeff Law  <jlaw@ventanamicro.com>

	Revert:
	2024-10-29  yulong  <shiyulong@iscas.ac.cn>

	* config.gcc: Add riscv_cmo.h.
	* config/riscv/riscv_cmo.h: New file.

2025-01-21  Andrew Pinski  <quic_apinski@quicinc.com>

	PR tree-optimization/118483
	* match.pd (`x ==/!= ~x`): Allow for an optional convert
	and use itwise_inverted_equal_p/maybe_bit_not instead of
	directly matching bit_not.

2025-01-21  Robin Dapp  <rdapp@ventanamicro.com>

	* config/riscv/riscv.cc (riscv_file_end): Fix format string.
	(riscv_lshift_subword): Mark MODE as unused.

2025-01-21  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/avr-passes.cc (avr_emit_shift) [ASHIFT,HImode]:
	Allow offsets 5 and 6 as 3op provided have MUL and a scratch.
	* config/avr/avr.cc (avr_optimize_size_max_p): New function.
	(avr_out_ashlhi3_mul): New function.
	(ashlhi3_out) [case 4, 5, 6]: Better speed for -Os.
	* config/avr/avr.md (isa) <mul, no_mul>: New attr values.
	(*ashlhi3_const): Add alternative for offsets 5 and 6.

2025-01-21  Jin Ma  <jinma@linux.alibaba.com>

	PR target/116593
	* config/riscv/constraints.md (vl): New.
	* config/riscv/thead-vector.md: Replacing rK with rvl.
	* config/riscv/vector.md: Likewise.

2025-01-21  Denis Chertykov  <chertykov@gmail.com>

	* lra-spills.cc (assign_stack_slot_num_and_sort_pseudos): Use known_ge
	to compare sizes.

2025-01-21  Jeff Law  <jlaw@ventanamicro.com>

	PR target/116256
	* config/riscv/predicates.md (consecutive_bits_operand): Properly
	handle (const_int 0).

2025-01-21  Alfie Richards  <alfie.richards@arm.com>

	* config/aarch64/aarch64.opt.urls: Regenerate

2025-01-21  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/118569
	* cfgloopmanip.cc (fix_loop_placement): When the loops
	nesting parents changed, mark all blocks to be scanned
	for LC PHI uses.
	(fix_bb_placements): Remove code moved into fix_loop_placement.

2025-01-21  Vladimir Miloserdov  <vladimir.miloserdov@arm.com>

	* config/aarch64/aarch64-c.cc
	(aarch64_update_cpp_builtins): Add new flag TARGET_LUT.
	* config/aarch64/aarch64-sve-builtins-shapes.cc
	(struct luti_base): Shape for lut intrinsics.
	(SHAPE): Specializations for lut shapes for luti2 and luti4..
	* config/aarch64/aarch64-sve-builtins-shapes.h: Declare lut
	intrinsics.
	* config/aarch64/aarch64-sve-builtins-sve2.cc
	(class svluti_lane_impl): Define expand for lut intrinsics.
	(FUNCTION): Define expand for lut intrinsics.
	* config/aarch64/aarch64-sve-builtins-sve2.def
	(REQUIRED_EXTENSIONS): Declare lut intrinsics behind lut flag.
	(svluti2_lane): Define intrinsic behind flag.
	(svluti4_lane): Define intrinsic behind flag.
	* config/aarch64/aarch64-sve-builtins-sve2.h: Declare lut
	intrinsics.
	* config/aarch64/aarch64-sve-builtins.cc
	(TYPES_bh_data): New type for byte and halfword.
	(bh_data): Type array for byte and halfword.
	(h_data): Type array for halfword.
	* config/aarch64/aarch64-sve2.md
	(@aarch64_sve_luti<LUTI_BITS><mode>): Instruction patterns for
	lut intrinsics.
	* config/aarch64/iterators.md: Iterators and attributes for lut
	intrinsics.

2025-01-21  Tamar Christina  <tamar.christina@arm.com>

	PR middle-end/118273
	* tree-vect-stmts.cc (vectorizable_simd_clone_call): Use nvectors when
	doing mask registrations.

2025-01-21  Tamar Christina  <tamar.christina@arm.com>

	* config.gcc (aarch64-*-elf): Drop ILP32 from default multilibs.

2025-01-21  Lulu Cheng  <chenglulu@loongson.cn>

	* config/loongarch/loongarch-protos.h
	(loongarch_reset_previous_fndecl):  Add function declaration.
	(loongarch_save_restore_target_globals): Likewise.
	(loongarch_register_pragmas): Likewise.
	* config/loongarch/loongarch-target-attr.cc
	(loongarch_option_valid_attribute_p): Optimize the processing
	of attributes.
	(loongarch_pragma_target_parse): New functions.
	(loongarch_register_pragmas): Likewise.
	* config/loongarch/loongarch.cc
	(loongarch_reset_previous_fndecl): New functions.
	(loongarch_set_current_function): When the old_tree is the same
	as the new_tree, the rules for using registers, etc.,
	are set according to the option values to ensure that the
	pragma can be processed correctly.
	* config/loongarch/loongarch.h (REGISTER_TARGET_PRAGMAS):
	Define macro.
	* doc/extend.texi: Supplemental Documentation.

2025-01-21  Lulu Cheng  <chenglulu@loongson.cn>

	* attr-urls.def: Regenerate.
	* config.gcc: Add loongarch-target-attr.o to extra_objs.
	* config/loongarch/loongarch-protos.h
	(loongarch_option_valid_attribute_p): Function declaration.
	(loongarch_option_override_internal): Likewise.
	* config/loongarch/loongarch.cc
	(loongarch_option_override_internal): Delete the modifications
	to target_option_default_node and target_option_current_node.
	(loongarch_set_current_function): Add annotation information.
	(loongarch_option_override): add assignment operations to
	target_option_default_node and target_option_current_node.
	(TARGET_OPTION_VALID_ATTRIBUTE_P): Define.
	* config/loongarch/t-loongarch: Add compilation of target file
	loongarch-target-attr.o.
	* doc/extend.texi: Add description information of LoongArch
	Function Attributes.
	* config/loongarch/loongarch-target-attr.cc: New file.

2025-01-21  Alfie Richards  <alfie.richards@arm.com>

	* config/aarch64/aarch64.cc
	(aarch64_process_target_version_attr): Add experimental warning.
	* config/aarch64/aarch64.opt: Add command line option to disable
	warning.
	* doc/invoke.texi: Add documentation for -W[no-]experimental-fmv-target.

2025-01-20  Vladimir N. Makarov  <vmakarov@redhat.com>

	PR target/118560
	* lra-constraints.cc (invalid_mode_reg_p): Exchange args in
	hard_reg_set_subset_p call.

2025-01-20  Jeff Law  <jlaw@ventanamicro.com>

	PR target/114442
	* config/riscv/xiangshan.md: Add missing insn types to a
	new dummy insn reservation.

2025-01-20  Jeff Law  <jlaw@ventanamicro.com>

	PR target/116256
	* config/riscv/riscv.md (reassocating constant addition): Adjust
	condition to avoid creating an unrecognizable insn.

2025-01-20  Denis Chertykov  <chertykov@gmail.com>

	PR rtl-optimization/117868
	* lra-spills.cc (assign_stack_slot_num_and_sort_pseudos): Reuse slots
	only without allocated memory or only with equal or smaller registers
	with equal or smaller alignment.
	(lra_spill): Print slot size as width.

2025-01-20  Richard Sandiford  <richard.sandiford@arm.com>

	PR tree-optimization/118348
	* tree-vectorizer.cc (vec_info::move_dr): Copy
	STMT_VINFO_SIMD_LANE_ACCESS_P.

2025-01-20  Richard Sandiford  <richard.sandiford@arm.com>

	Revert:
	2025-01-20  Richard Sandiford  <richard.sandiford@arm.com>

	PR tree-optimization/118384
	* tree-vectorizer.cc (vec_info::move_dr): Copy
	STMT_VINFO_SIMD_LANE_ACCESS_P.

2025-01-20  Richard Sandiford  <richard.sandiford@arm.com>

	PR tree-optimization/118384
	* tree-vectorizer.cc (vec_info::move_dr): Copy
	STMT_VINFO_SIMD_LANE_ACCESS_P.

2025-01-20  Richard Sandiford  <richard.sandiford@arm.com>

	PR target/118501
	* config/aarch64/aarch64.md (@xorsign<mode>3): Use
	force_lowpart_subreg.

2025-01-20  Richard Sandiford  <richard.sandiford@arm.com>

	PR target/118531
	* config/aarch64/aarch64.md (*insv_reg<mode>_<SUBDI_BITS>)
	(*aarch64_bfi<GPI:mode><ALLX:mode>_<SUBDI_BITS>)
	(*aarch64_bfidi<ALLX:mode>_subreg_<SUBDI_BITS>): Add missing
	simd requirements.

2025-01-20  Jin Ma  <jinma@linux.alibaba.com>

	* config/riscv/thead.md (*th_cond_mov<GPR:mode><GPR2:mode>):
	Change GPR2 to X.
	(*th_cond_mov<GPR:mode>): Likewise.

2025-01-20  Andrew Pinski  <quic_apinski@quicinc.com>

	PR tree-optimization/118077
	PR tree-optimization/117668
	* tree-inline.cc (fold_marked_statements): Purge abnormal edges
	as needed.

2025-01-20  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/117875
	* tree-vect-slp.cc (vect_build_slp_tree_1): Handle SSA copies.

2025-01-20  Xi Ruoyao  <xry111@xry111.site>

	PR target/115921
	* config/loongarch/loongarch-protos.h
	(loongarch_reassoc_shift_bitwise): New function prototype.
	* config/loongarch/loongarch.cc
	(loongarch_reassoc_shift_bitwise): Implement.
	* config/loongarch/loongarch.md
	(*alslsi3_extend_subreg): New define_insn_and_split.
	(<any_bitwise:optab>_shift_reverse<X:mode>): New
	define_insn_and_split.
	(<any_bitwise:optab>_alsl_reversesi_extended): New
	define_insn_and_split.
	(zero_extend_ashift): Remove as it's just a special case of
	and_shift_reversedi, and it does not make too much sense to
	write "alsl.d rd,rs,r0,shamt" instead of "slli.d rd,rs,shamt".
	(bstrpick_alsl_paired): Remove as it is already done by
	splitting and_shift_reversedi into and + ashift first, then
	late combining the ashift and a further add.

2025-01-20  Xi Ruoyao  <xry111@xry111.site>

	* config/loongarch/constraints.md (Yy): New define_constriant.
	* config/loongarch/loongarch.cc (loongarch_print_operand):
	For "%M", output the index of bits to be used with
	bstrins/bstrpick.
	* config/loongarch/predicates.md (ins_zero_bitmask_operand):
	Exclude low_bitmask_operand as for low_bitmask_operand it's
	always better to use bstrpick instead of bstrins.
	(and_operand): New define_predicate.
	* config/loongarch/loongarch.md (any_or): New
	define_code_iterator.
	(bitwise_operand): New define_code_attr.
	(*<optab:any_or><mode:GPR>3): New define_insn.
	(*and<mode:GPR>3): New define_insn.
	(<optab:any_bitwise><mode:X>3): New define_expand.
	(and<mode>3_extended): Remove, replaced by the 3rd alternative
	of *and<mode:GPR>3.
	(bstrins_<mode>_for_mask): Remove, replaced by the 4th
	alternative of *and<mode:GPR>3.
	(*<optab:any_bitwise>si3_internal): Remove, already covered by
	the *<optab:any_or><mode:GPR>3 and *and<mode:GPR>3 templates.

2025-01-20  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/118552
	* cfgloopmanip.cc (fix_loop_placement): Properly mark
	exit source blocks as to be scanned for LC SSA update when
	the loops nesting relationship changed.
	(fix_loop_placements): Adjust.
	(fix_bb_placements): Likewise.

2025-01-20  Thomas Schwinge  <tschwinge@baylibre.com>

	* config/nvptx/t-nvptx (MULTILIB_OPTIONS): Don't add 'mptx=3.1' if
	neither sm_30 nor sm_35 multilib variant is built.

2025-01-20  Jakub Jelinek  <jakub@redhat.com>

	PR c++/118509
	* tree.cc (tree_invariant_p_1): Return true for TARGET_EXPR too.

2025-01-20  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/118224
	* tree-ssa-dce.cc (is_removable_allocation_p): Multiply a1 by a2
	instead of adding it.

2025-01-20  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>

	* config/s390/s390-builtins.def (s390_vec_load_len): Deprecate
	some overloads.
	(s390_vec_store_len): Deprecate some overloads.
	(s390_vec_load_len_r): Add.
	(s390_vec_store_len_r): Add.
	* config/s390/s390-c.cc (s390_vec_load_len_r): Add.
	(s390_vec_store_len_r): Add.
	* config/s390/vecintrin.h (vec_load_len_r): Redefine.
	(vec_store_len_r): Redefine.

2025-01-20  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>

	* config/s390/s390-builtins.def: Add 128-bit variants.
	* config/s390/s390-builtin-types.def: Update accordingly.
	* config/s390/vector.md (<vec_shifts_name><mode>3): Add 128-bit
	variants.
	* config/s390/vx-builtins.md: Ditto.

2025-01-20  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>

	* config/s390/s390-builtins.def: Add 128-bit variants and remove
	bool variants.
	* config/s390/s390-builtin-types.def: Update accordinly.
	* config/s390/s390.md: Emulate min/max for GPR.
	* config/s390/vector.md: Add min/max patterns and emulate in
	case of no VXE3.

2025-01-20  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>

	* config/s390/s390-builtins.def (s390_vec_abs_s128): Add.
	(s390_vlpq): Add.
	* config/s390/s390-builtin-types.def: Update accordingly.
	* config/s390/vector.md (abs<mode>2): Emulate w/o VXE3.
	(*abs<mode>2): Add 128-bit variant.
	(*vec_sel0<mode>): Make it a ...
	(vec_sel0<mode>): named pattern.

2025-01-20  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>

	* config/s390/s390-builtins.def: Add 128-bit variants.
	* config/s390/s390-builtin-types.def: Update accordingly.
	* config/s390/s390.cc (s390_expand_vec_compare_cc): Also
	consider TI modes for vectors.
	* config/s390/vector.md: Enable *vec_cmp et al. for VXE3.
	* config/s390/vx-builtins.md: Ditto.

2025-01-20  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>

	* config/s390/vector.md (div<mode>3): Add.
	(udiv<mode>3): Add.
	(mod<mode>3): Add.
	(umod<mode>3): Add.

2025-01-20  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>

	* config/s390/s390-builtins.def (s390_vec_cntlz): Add 128-bit
	integer overloads.
	(s390_vclzq): Add.
	(s390_vec_cnttz): Add 128-bit integer overloads.
	(s390_vctzq): Add.
	* config/s390/s390-builtin-types.def: Update accordingly.
	* config/s390/s390.h (CTZ_DEFINED_VALUE_AT_ZERO): Define.
	* config/s390/s390.md (*clzg): New insn.
	(clztidi2): Exploit new insn for target arch15.
	(ctzdi2): New insn.
	* config/s390/vector.md (clz<mode>2): Extend modes including
	128-bit integer.
	(ctz<mode>2): Likewise.

2025-01-20  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>

	* config/s390/s390-builtins.def (s390_vec_gen_element_masks_128): Add.
	(s390_vgemb): Add.
	(s390_vgemh): Add.
	(s390_vgemf): Add.
	(s390_vgemg): Add.
	(s390_vgemq): Add.
	* config/s390/s390-builtin-types.def: Update accordingly.
	* config/s390/s390.md (UNSPEC_VEC_VGEM): Add.
	* config/s390/vecintrin.h (vec_gen_element_masks_8): Define.
	(vec_gen_element_masks_16): Define.
	(vec_gen_element_masks_32): Define.
	(vec_gen_element_masks_64): Define.
	(vec_gen_element_masks_128): Define.
	* config/s390/vx-builtins.md (vgemv16qi): Add.
	(vgem<mode>): Add.

2025-01-20  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>

	* config/s390/s390-builtins.def (s390_vec_evaluate): Add.
	(s390_veval): Add.
	* config/s390/s390-builtin-types.def: Update accordingly.
	* config/s390/s390.md (UNSPEC_VEC_VEVAL): Add.
	* config/s390/vecintrin.h (vec_evaluate): Define.
	* config/s390/vector.md
	(*veval<mode>_<logic_op1:logic_op_stringify><logic_op2:logic_op_stringify>):
	Add.
	(veval<mode>): Add.

2025-01-20  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>

	* config/s390/s390-builtins.def (s390_vec_blend): Add.
	(s390_vblendb): Add.
	(s390_vblendh): Add.
	(s390_vblendf): Add.
	(s390_vblendg): Add.
	(s390_vblendq): Add.
	* config/s390/s390-builtin-types.def: Update accordingly.
	* config/s390/s390.md (UNSPEC_VEC_VBLEND): Add.
	* config/s390/vecintrin.h (vec_blend): Define.
	* config/s390/vx-builtins.md (vblend<mode>): Add.

2025-01-20  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>

	* config/s390/s390-builtins.def (s390_bdepg): Add.
	(s390_bextg): Add.
	* config/s390/s390-builtin-types.def: Update accordingly.
	* config/s390/s390.md (UNSPEC_BDEPG): Add.
	(UNSPEC_BEXTG): Add.
	(bdepg): Add.
	(bextg): Add.

2025-01-20  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>

	* config/s390/s390.md (*lxa<LXAMODE>_index): Add.
	(*lxa<LXAMODE>_displacement_index): Add.
	(*lxa<LXAMODE>_index_base): Add.
	(*lxa<LXAMODE>_displacement_index_base): Add.
	(*lxab_displacement_index_base): Add.
	(*llxa<LXAMODE>_displacement_index): Add.
	(*llxa<LXAMODE>_index_base): Add.
	(*llxa<LXAMODE>_displacement_index_base): Add.
	(*llxab_displacement_index_base): Add.

2025-01-20  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>

	* config/s390/s390-builtins.def: Add new instruction variants.
	* config/s390/s390-builtin-types.def: Update accordingly.
	* config/s390/vecintrin.h: Add new defines.
	* config/s390/vector.md: Adapt insns for new instruction
	variants.
	* config/s390/vx-builtins.md: Ditto.

2025-01-20  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>

	* config/s390/s390-builtins.def (B_VXE3): Define.
	(B_ARCH15): Define.
	* config/s390/s390-c.cc (s390_resolve_overloaded_builtin):
	Consistency checks for VXE3.
	* config/s390/s390.cc (s390_expand_builtin): Consistency checks
	for VXE3.

2025-01-20  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>

	* config/s390/s390-c.cc (rid_int128): New helper function.
	(s390_macro_to_expand): Deal with `vector __int128`.
	(s390_cpu_cpp_builtins_internal): Bump __VEC__.
	* config/s390/s390.cc (s390_handle_vectorbool_attribute): Add
	128-bit bool zvector.

2025-01-20  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>

	* common/config/s390/s390-common.cc: Add arch15 processor flags.
	* config.gcc: Add arch15 for options --with-{arch,mtune}.
	* config/s390/driver-native.cc (s390_host_detect_local_cpu):
	Default to arch15.
	* config/s390/s390-opts.h (enum processor_type): Add
	PROCESSOR_ARCH15.
	* config/s390/s390.cc (processor_table,s390_issue_rate,
	s390_get_sched_attrmask,s390_get_unit_mask): Add arch15.
	* config/s390/s390.h (enum processor_flags): Add processor flags
	for VXE3 and ARCH15.
	(TARGET_CPU_VXE3): Define.
	(TARGET_CPU_VXE3_P): Define.
	(TARGET_CPU_ARCH15): Define.
	(TARGET_CPU_ARCH15_P): Define.
	(TARGET_VXE3): Define.
	(TARGET_VXE3_P): Define.
	(TARGET_ARCH15): Define.
	(TARGET_ARCH15_P): Define.
	* config/s390/s390.md: Add VXE3 and ARCH15 to cpu_facility, and
	let attribute "enabled" deal with them.
	* config/s390/s390.opt: Add arch15.

2025-01-20  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>

	* config/s390/vecintrin.h: Sort definitions.

2025-01-20  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>

	* config/s390/vector.md: Stay scalar for TOINTVEC/tointvec.

2025-01-20  Kito Cheng  <kito.cheng@sifive.com>

	* config.gcc (riscv*): Install sifive_vector.h.
	* config/riscv/sifive_vector.h: New.

2025-01-20  Hongyu Wang  <hongyu.wang@intel.com>

	PR target/118510
	* config/i386/i386.md (*x86_64_shld_ndd_2): Use register_operand
	for operand[0] and adjust the output template to directly
	generate ndd form shld pattern.
	(*x86_shld_ndd_2): Likewise.
	(*x86_64_shrd_ndd_2): Likewise.
	(*x86_shrd_ndd_2): Likewise.

2025-01-19  Uros Bizjak  <ubizjak@gmail.com>

	* config/i386/i386.md (*movdi_internal): Reorder ISA attribute
	by ascending alternative index.

2025-01-19  Mark Wielaard  <mark@klomp.org>

	* config/sparc/sparc.opt.urls: Regenerated.

2025-01-19  Gerald Pfeifer  <gerald@pfeifer.com>

	* doc/gm2.texi (Type compatibility): Move modula2.org link
	to https.

2025-01-19  Gerald Pfeifer  <gerald@pfeifer.com>

	* doc/extend.texi (OpenMP): Adjust link to specifications.

2025-01-18  Jeff Law  <jlaw@ventanamicro.com>

	PR target/116308
	* config/riscv/riscv.cc (riscv_lshift_subword): Use gen_lowpart
	rather than simplify_gen_subreg.

2025-01-18  Michal Jires  <mjires@suse.cz>

	* cgraph.cc (symbol_table::create_empty):
	Move uid to symtab_node.
	(test_symbol_table_test): Change expected dump id.
	* cgraph.h (struct cgraph_node):
	Move uid to symtab_node.
	(symbol_table::register_symbol): Likewise.
	* dumpfile.cc (test_capture_of_dump_calls):
	Change expected dump id.
	* ipa-inline.cc (update_caller_keys):
	Use summary id instead of uid.
	(update_callee_keys): Likewise.
	* symtab.cc (symtab_node::get_dump_name):
	Use uid instead of order.

2025-01-18  Eric Botcazou  <ebotcazou@adacore.com>

	PR target/118512
	* config/sparc/sparc-c.cc (sparc_target_macros): Deal with VIS 3B.
	* config/sparc/sparc.cc (dump_target_flag_bits): Likewise.
	(sparc_option_override): Likewise.
	(sparc_vis_init_builtins): Likewise.
	* config/sparc/sparc.md (fpcmp_vis): Replace TARGET_VIS3 with
	TARGET_VIS3B.
	(vec_cmp): Likewise.
	(fpcmpu_vis): Likewise.
	(vec_cmpu): Likewise.
	(vcond_mask_): Likewise.
	* config/sparc/sparc.opt (VIS3B): New target mask.
	* doc/invoke.texi (SPARC options): Document -mvis3b.

2025-01-18  Jin Ma  <jinma@linux.alibaba.com>

	PR target/118357
	* config/riscv/riscv-vsetvl.cc: Function change_vtype_only_p always
	returns false for XTheadVector.

2025-01-18  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/118529
	* tree-vect-stmts.cc (vectorizable_condition): Check the
	shape of the vector and condition vector type are compatible.

2025-01-18  Georg-Johann Lay  <avr@gjlay.de>

	* doc/invoke.texi (AVR Options): Fix plenk at -msplit-ldst.

2025-01-18  Akram Ahmad  <Akram.Ahmad@arm.com>
	    Tamar Christina  <tamar.christina@arm.com>

	* config/aarch64/aarch64-builtins.cc: Expand iterators.
	* config/aarch64/aarch64-simd-builtins.def: Use standard names
	* config/aarch64/aarch64-simd.md: Use standard names, split insn
	definitions on signedness of operator and type of operands.
	* config/aarch64/arm_neon.h: Use standard builtin names.
	* config/aarch64/iterators.md: Add VSDQ_I_QI_HI iterator to
	simplify splitting of insn for unsigned scalar arithmetic.

2025-01-18  Akram Ahmad  <Akram.Ahmad@arm.com>

	* config/aarch64/aarch64-sve.md: Rename insns

2025-01-18  Tamar Christina  <tamar.christina@arm.com>

	Revert:
	2025-01-17  Tamar Christina  <tamar.christina@arm.com>

	* config/aarch64/aarch64-builtins.cc: Expand iterators.
	* config/aarch64/aarch64-simd-builtins.def: Use standard names
	* config/aarch64/aarch64-simd.md: Use standard names, split insn
	definitions on signedness of operator and type of operands.
	* config/aarch64/arm_neon.h: Use standard builtin names.
	* config/aarch64/iterators.md: Add VSDQ_I_QI_HI iterator to
	simplify splitting of insn for unsigned scalar arithmetic.

2025-01-18  Tamar Christina  <tamar.christina@arm.com>

	Revert:
	2025-01-17  Tamar Christina  <tamar.christina@arm.com>

	* config/aarch64/aarch64-sve.md: Rename insns

2025-01-18  Monk Chiang  <monk.chiang@sifive.com>

	* config/riscv/riscv.cc: Remove unused variable.

2025-01-18  Xi Ruoyao  <xry111@xry111.site>

	* config/loongarch/loongarch.cc (loongarch_rtx_costs): Fix the
	cost for (a + b * imm) and (a + (b << imm)) which can be
	implemented with a single alsl instruction.

2025-01-18  Xi Ruoyao  <xry111@xry111.site>

	* config/loongarch/loongarch.md (alslsi3_extend): Add alsl.wu.

2025-01-17  Vladimir N. Makarov  <vmakarov@redhat.com>

	PR rtl-optimization/118067
	* lra-constraints.cc (invalid_mode_reg_p): New function.
	(curr_insn_transform): Use it to check mode returned by target
	secondary_memory_needed_mode.

2025-01-17  Jakub Jelinek  <jakub@redhat.com>

	PR target/118511
	* config/s390/s390.cc (print_operand) <case 'p'>: Use
	output_operand_lossage instead of gcc_checking_assert.
	(print_operand) <case 'q'>: Likewise.
	(print_operand) <case 'r'>: Likewise.

2025-01-17  Tamar Christina  <tamar.christina@arm.com>

	* config/aarch64/aarch64-sve.md: Rename insns

2025-01-17  Tamar Christina  <tamar.christina@arm.com>

	* config/aarch64/aarch64-builtins.cc: Expand iterators.
	* config/aarch64/aarch64-simd-builtins.def: Use standard names
	* config/aarch64/aarch64-simd.md: Use standard names, split insn
	definitions on signedness of operator and type of operands.
	* config/aarch64/arm_neon.h: Use standard builtin names.
	* config/aarch64/iterators.md: Add VSDQ_I_QI_HI iterator to
	simplify splitting of insn for unsigned scalar arithmetic.

2025-01-17  Carl Love  <cel@linux.ibm.com>

	* config/rs6000/rs6000-builtins.def (__builtin_vsx_xvcvuxwdp):
	Remove built-in definition.

2025-01-17  Carl Love  <cel@linux.ibm.com>

	* config/rs6000/rs6000-builtins.def (__builtin_vsx_vperm_8hi,
	__builtin_vsx_vperm_8hi_uns): Remove built-in definitions.

2025-01-17  Carl Love  <cel@linux.ibm.com>

	* doc/extend.texi: Fix spelling mistake in description of the
	vec_sel built-in.  Add documentation of the 128-bit vec_perm
	instance.

2025-01-17  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/avr-c.cc (DEF_BUILTIN): Add ATTRS argument to macro
	definition.
	* config/avr/avr.cc: Same.
	(avr_init_builtins) <attr_const>: New variable that can be used
	as ATTRS argument in DEF_BUILTIN.
	* config/avr/builtins.def (DEF_BUILTIN): Add ATTRS parameter
	to all definitions.

2025-01-17  Georg-Johann Lay  <avr@gjlay.de>

	PR target/118329
	* config/avr/avr-modes.def: Add INT_N (PSI, 24).
	* config/avr/avr.cc (avr_init_builtin_int24)
	<__int24>: Remove definition.
	<__uint24>: Adjust definition to INT_N interface.

2025-01-17  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/118522
	* match.pd ((FTYPE) N CMP (FTYPE) M): Add convert, as in GENERIC
	integral types with the same precision and sign might actually not
	be compatible types.

2025-01-17  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/92539
	* tree-ssa-loop-ivcanon.cc (tree_unroll_loops_completely_1):
	Also try force-evaluation if ivcanon did not yet run.
	(canonicalize_loop_induction_variables):
	When niter was computed constant by force evaluation add a
	canonical IV if we didn't unroll.
	* tree-ssa-loop-niter.cc (loop_niter_by_eval): When we
	don't find a proper PHI try if the exit condition scans
	over a STRING_CST and simulate that.

2025-01-17  Monk Chiang  <monk.chiang@sifive.com>

	* config/riscv/riscv.cc
	(is_zicfilp_p): New function.
	(is_zicfiss_p): New function.
	* config/riscv/riscv-zicfilp.cc: Update.
	* config/riscv/riscv.h: Update.
	* config/riscv/riscv.md: Update.
	* config/riscv/riscv-c.cc: Add CFI predefine marco.

2025-01-17  Monk Chiang  <monk.chiang@sifive.com>

	* config/riscv/riscv.cc
	(riscv_file_end): Add .note.gnu.property.

2025-01-17  Monk Chiang  <monk.chiang@sifive.com>

	* common/config/riscv/riscv-common.cc: Add ZICFILP ISA
	string.
	* config.gcc: Add riscv-zicfilp.o
	* config/riscv/riscv-passes.def (INSERT_PASS_BEFORE):
	Insert landing pad instructions.
	* config/riscv/riscv-protos.h (make_pass_insert_landing_pad):
	Declare.
	* config/riscv/riscv-zicfilp.cc: New file.
	* config/riscv/riscv.cc
	(riscv_trampoline_init): Add landing pad instructions.
	(riscv_legitimize_call_address): Likewise.
	(riscv_output_mi_thunk): Likewise.
	* config/riscv/riscv.h: Update.
	* config/riscv/riscv.md: Add landing pad patterns.
	* config/riscv/riscv.opt (TARGET_ZICFILP): Define.
	* config/riscv/t-riscv: Add build rule for
	riscv-zicfilp.o

2025-01-17  Monk Chiang  <monk.chiang@sifive.com>

	* common/config/riscv/riscv-common.cc: Add ZICFISS ISA string.
	* config/riscv/predicates.md: New predicate x1x5_operand.
	* config/riscv/riscv.cc
	(riscv_expand_prologue): Insert shadow stack instructions.
	(riscv_expand_epilogue): Likewise.
	(riscv_for_each_saved_reg): Assign t0 or ra register for
	sspopchk instruction.
	(need_shadow_stack_push_pop_p): New function. Omit shadow
	stack operation on leaf function.
	* config/riscv/riscv.h
	(need_shadow_stack_push_pop_p): Define.
	* config/riscv/riscv.md: Add shadow stack patterns.
	(save_stack_nonlocal): Add shadow stack instructions for setjump.
	(restore_stack_nonlocal): Add shadow stack instructions for longjump.
	* config/riscv/riscv.opt (TARGET_ZICFISS): Define.

2025-01-16  Tamar Christina  <tamar.christina@arm.com>
	    Richard Sandiford  <richard.sandiford@arm.com>

	PR target/113257
	* config/aarch64/driver-aarch64.cc (get_cpu_from_id, DEFAULT_CPU): New.
	(host_detect_local_cpu): Use it.

2025-01-16  Tamar Christina  <tamar.christina@arm.com>

	PR target/110901
	* config/aarch64/aarch64.h (MCPU_TO_MARCH_SPEC): Don't override if
	march is set.

2025-01-16  Vladimir N. Makarov  <vmakarov@redhat.com>

	PR rtl-optimization/1180167
	* lra-constraints.cc (process_alt_operands): Use operand mode not
	subreg reg mode.  Add and improve debugging prints for updating
	losers.

2025-01-16  Sandra Loosemore  <sloosemore@baylibre.com>

	* omp-general.cc (omp_complete_construct_context): Check
	"omp declare target" attribute, not "omp declare target block".

2025-01-16  Peter Bergner  <bergner@linux.ibm.com>

	* config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Return
	const0_rtx when there is an error.

2025-01-16  Peter Bergner  <bergner@linux.ibm.com>

	* config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Use correct
	array size for the loop limit.
	* config/rs6000/rs6000-builtins.def: Fix field size for PMASK operand.

2025-01-16  Liao Shihua  <shihua@iscas.ac.cn>

	* config/riscv/vector.md: New attr set.

2025-01-16  Jiawei  <jiawei@iscas.ac.cn>

	* config/riscv/genrvv-type-indexer.cc (expand_floattype): New func.
	(main): New type.
	* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_XFQF_OPS): New def.
	(vint8mf8_t): Ditto.
	(vint8mf4_t): Ditto.
	(vint8mf2_t): Ditto.
	(vint8m1_t): Ditto.
	(vint8m2_t): Ditto.
	* config/riscv/riscv-vector-builtins.cc (DEF_RVV_XFQF_OPS): Ditto.
	(rvv_arg_type_info::get_xfqf_float_type): Ditto.
	* config/riscv/riscv-vector-builtins.def (xfqf_vector): Ditto.
	(xfqf_float): Ditto.
	* config/riscv/riscv-vector-builtins.h
	(struct rvv_arg_type_info): New function prototype.
	* config/riscv/sifive-vector.md: Update iterator.
	* config/riscv/vector-iterators.md: Ditto.

2025-01-16  Christoph Müllner  <christoph.muellner@vrull.eu>

	PR tree-optimization/118487
	* tree-ssa-forwprop.cc (recognise_vec_perm_simplify_seq):
	Ensure that shuffle masks are VECTOR_CSTs.

2025-01-16  Christoph Müllner  <christoph.muellner@vrull.eu>

	* tree-ssa-forwprop.cc (recognise_vec_perm_simplify_seq):
	Eliminate redundant calls to to_constant().

2025-01-16  Richard Biener  <rguenther@suse.de>
	    Mikael Morin  <mikael@gcc.gnu.org>

	PR tree-optimization/115494
	* tree-ssa-pre.cc (phi_translate_1): Always generate a
	representative for translated dependent expressions.

2025-01-16  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/118430
	* tree-ssa-propagate.cc (may_propagate_copy): Return false if dest
	is lhs of an [[gnu::musttail]] call.
	(substitute_and_fold_dom_walker::before_dom_children): Formatting fix.

2025-01-16  Jakub Jelinek  <jakub@redhat.com>
	    Andrew Pinski  <quic_apinski@quicinc.com>

	PR tree-optimization/118430
	* tree-tailcall.cc: Include gimple-range.h, alloc-pool.h, sreal.h,
	symbol-summary.h, ipa-cp.h and ipa-prop.h.
	(find_tail_calls): If ass_var is NULL and ret_var is not, check if
	IPA-VRP has not found singleton return range for it.  In that case,
	don't punt if ret_var is the only value in that range.  Adjust the
	maybe_error_musttail message otherwise to diagnose different value
	being returned from the caller and callee rather than using return
	slot.  Formatting fixes.

2025-01-16  Jakub Jelinek  <jakub@redhat.com>

	* doc/extend.texi (Using Assembly Language with C): Add Asm constexprs
	to @menu.
	(Basic Asm): Move @node asm constexprs before Asm Labels, rename to
	Asm constexprs, change wording so that it is clearer that the constant
	expression actually must not return a string literal, just some specific
	container and other wording tweaks.  Only talk about top-level for basic
	asms in this @node, move restrictions on top-level extended asms to ...
	(Extended Asm): ... here.

2025-01-16  Jakub Jelinek  <jakub@redhat.com>

	PR ipa/118400
	* vec.h (vec<T, va_heap, vl_ptr>::release): Call m_vec->truncate (0)
	instead of clearing m_vec->m_vecpfx.m_num.

2025-01-16  liuhongt  <hongtao.liu@intel.com>

	PR target/118489
	* config/i386/sse.md (VF1_AVX512BW): Fix typo.

2025-01-16  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/115895
	* tree-vect-stmts.cc (get_group_load_store_type): When we
	might overrun because the group size is not a multiple of the
	vector size we cannot use loop masking since that does not
	implement the required load shortening.

2025-01-16  Keith Packard  <keithp@keithp.com>

	* config/lm32/lm32.cc: Add several #includes.
	(va_list_type): New.
	(lm32_build_va_list): New function.
	(lm32_builtin_va_start): Likewise.
	(lm32_sd_gimplify_va_arg_expr): Likewise.
	(lm32_gimplify_va_arg_expr): Likewise.

2025-01-16  Keith Packard  <keithp@keithp.com>

	* config/lm32/lm32.cc (setup_incoming_varargs): Adjust the
	conditionals so that pretend_size is always computed, even
	if no_rtl is set.

2025-01-16  Keith Packard  <keithp@keithp.com>

	* config/lm32/lm32.cc (lm32_setup_incoming_varargs): Skip last
	named parameter when preparing to flush registers with unnamed
	arguments to th stack.

2025-01-16  Keith Packard  <keithp@keithp.com>

	* config/lm32/lm32.cc (lm32_function_arg): Pass unnamed
	arguments in registers too, just like named arguments.

2025-01-16  Andi Kleen  <ak@gcc.gnu.org>

	* config/i386/x86-tune-sched-core.cc: Fix incorrect comment.

2025-01-16  Eugene Rozenfeld  <erozen@microsoft.com>

	PR gcov-profile/116743
	* auto-profile.cc (afdo_annotate_cfg): Fix mismatch between the call graph node count
	and the entry block count.

2025-01-15  Andrew Pinski  <quic_apinski@quicinc.com>

	PR tree-optimization/102705
	* match.pd (`(1 >> X) != 0`): Remove pattern.
	(`1 >> x`): New pattern.

2025-01-15  Sam James  <sam@gentoo.org>

	* doc/extend.texi: Cleanup trailing whitespace.

2025-01-15  Sam James  <sam@gentoo.org>

	* doc/extend.texi: Add 'a' for grammar fix.

2025-01-15  Wilco Dijkstra  <wilco.dijkstra@arm.com>

	* config/aarch64/tuning_models/neoverse512tvb.h (tune_flags): Update.

2025-01-15  Wilco Dijkstra  <wilco.dijkstra@arm.com>

	* config/aarch64/aarch64-tuning-flags.def (AARCH64_EXTRA_TUNE_BASE):
	Add AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
	* config/aarch64/tuning_models/ampere1b.h: Remove redundant
	AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
	* config/aarch64/tuning_models/neoversev2.h: Likewise.

2025-01-15  Wilco Dijkstra  <wilco.dijkstra@arm.com>

	* config/aarch64/aarch64.cc (aarch64_override_options): Add warning.
	* doc/invoke.texi: Document -mabi=ilp32 as deprecated.

2025-01-15  Cupertino Miranda  <cupertino.miranda@oracle.com>

	* config/bpf/core-builtins.cc (compute_field_expr): Change
	VAR_DECL outcome in switch case.

2025-01-15  Cupertino Miranda  <cupertino.miranda@oracle.com>

	* config/bpf/core-builtins.cc
	(make_gimple_core_safe_access_index): Fix in condition.

2025-01-15  Cupertino Miranda  <cupertino.miranda@oracle.com>

	* btfout.cc (get_btf_kind): Remove static from function definition.
	* config/bpf/btfext-out.cc (bpf_code_reloc_add): Check if CO-RE type
	is not a const or volatile.
	* ctfc.h (btf_dtd_kind): Add prototype for function.

2025-01-15  Tamar Christina  <tamar.christina@arm.com>

	PR middle-end/118472
	* fold-const.cc (operand_compare::operand_equal_p): Fix incorrect
	replacement.

2025-01-15  Richard Biener  <rguenther@suse.de>

	* genmatch.cc (define_dump_logs): Make reverse lookup in
	dbg_line_numbers easier by adding comments with start index
	and cutting number of elements per line to 10.

2025-01-15  Jakub Jelinek  <jakub@redhat.com>

	PR ipa/116068
	* cgraphunit.cc (symbol_table::process_new_functions): Call
	bitmap_obstack_initialize (NULL); and bitmap_obstack_release (NULL)
	around processing the functions.

2025-01-15  Kito Cheng  <kito.cheng@sifive.com>

	PR target/118182
	* config/riscv/autovec-opt.md (*widen_reduc_plus_scal_<mode>): Adjust
	argument for expand_reduction.
	(*widen_reduc_plus_scal_<mode>): Ditto.
	(*fold_left_widen_plus_<mode>): Ditto.
	(*mask_len_fold_left_widen_plus_<mode>): Ditto.
	(*cond_widen_reduc_plus_scal_<mode>): Ditto.
	(*cond_len_widen_reduc_plus_scal_<mode>): Ditto.
	(*cond_widen_reduc_plus_scal_<mode>): Ditto.
	* config/riscv/autovec.md (reduc_plus_scal_<mode>): Adjust argument for
	expand_reduction.
	(reduc_smax_scal_<mode>): Ditto.
	(reduc_umax_scal_<mode>): Ditto.
	(reduc_smin_scal_<mode>): Ditto.
	(reduc_umin_scal_<mode>): Ditto.
	(reduc_and_scal_<mode>): Ditto.
	(reduc_ior_scal_<mode>): Ditto.
	(reduc_xor_scal_<mode>): Ditto.
	(reduc_plus_scal_<mode>): Ditto.
	(reduc_smax_scal_<mode>): Ditto.
	(reduc_smin_scal_<mode>): Ditto.
	(reduc_fmax_scal_<mode>): Ditto.
	(reduc_fmin_scal_<mode>): Ditto.
	(fold_left_plus_<mode>): Ditto.
	(mask_len_fold_left_plus_<mode>): Ditto.
	* config/riscv/riscv-v.cc (expand_reduction): Add one more
	argument for reduction code for vl0-safe.
	* config/riscv/riscv-protos.h (expand_reduction): Ditto.
	* config/riscv/vector-iterators.md (unspec): Add _VL0_SAFE variant of
	reduction.
	(ANY_REDUC_VL0_SAFE): New.
	(ANY_WREDUC_VL0_SAFE): Ditto.
	(ANY_FREDUC_VL0_SAFE): Ditto.
	(ANY_FREDUC_SUM_VL0_SAFE): Ditto.
	(ANY_FWREDUC_SUM_VL0_SAFE): Ditto.
	(reduc_op): Add _VL0_SAFE variant of reduction.
	(order) Ditto.
	* config/riscv/vector.md (@pred_<reduc_op><mode>): New.

2025-01-15  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/115777
	* tree-vect-slp.cc (vect_bb_slp_scalar_cost): Do not
	cost a scalar stmt that needs to be preserved.

2025-01-15  Michal Jires  <mjires@suse.cz>

	PR lto/118238
	* lto-wrapper.cc (run_gcc): Remove link() copying.

2025-01-15  Anton Blanchard  <antonb@tenstorrent.com>
	    Jeff Law  <jlaw@ventanamicro.com>

	PR target/118170
	* config/riscv/generic-ooo.md (generic_ooo_float_div_half): New
	reservation.

2025-01-15  Richard Sandiford  <richard.sandiford@arm.com>
	    Jeff Law  <jlaw@ventanamicro.com>

	PR rtl-optimization/109592
	* simplify-rtx.cc (simplify_context::simplify_binary_operation_1):
	Simplify nested shifts with subregs.

2025-01-14  anetczuk  <anetczuk@o2.pl>

	* tree-dump.cc (dequeue_and_dump): Handle OBJ_TYPE_REF.

2025-01-14  Alexandre Oliva  <oliva@adacore.com>

	* gimple-fold.cc (decode_field_reference): Rebustify to set
	out parms only when returning non-NULL.
	(fold_truth_andor_for_ifcombine): Bail if
	decode_field_reference returns NULL.  Add complementary assert
	on r_const's not being set when l_const isn't.

2025-01-14  Sandra Loosemore  <sloosemore@baylibre.com>

	* cgraph.cc (symbol_table::create_edge): Don't set
	calls_declare_variant_alt in the caller.
	* cgraph.h (struct cgraph_node): Remove declare_variant_alt
	and calls_declare_variant_alt flags.
	* cgraphclones.cc (cgraph_node::create_clone): Don't copy
	calls_declare_variant_alt bit.
	* gimplify.cc: Remove previously #ifdef-ed out code.
	* ipa-free-lang-data.cc (free_lang_data_in_decl): Adjust code
	referencing declare_variant_alt bit.
	* ipa.cc (symbol_table::remove_unreachable_nodes): Likewise.
	* lto-cgraph.cc (lto_output_node): Remove references to deleted
	bits.
	(output_refs): Adjust code referencing declare_variant_alt bit.
	(input_overwrite_node): Remove references to deleted bits.
	(input_refs): Adjust code referencing declare_variant_alt bit.
	* lto-streamer-out.cc (lto_output): Likewise.
	* lto-streamer.h (omp_lto_output_declare_variant_alt): Delete.
	(omp_lto_input_declare_variant_alt): Delete.
	* omp-expand.cc (expand_omp_target): Use has_omp_variant_constructs
	bit to trigger pass_omp_device_lower instead of
	calls_declare_variant_alt.
	* omp-general.cc (struct omp_declare_variant_entry): Delete.
	(struct omp_declare_variant_base_entry): Delete.
	(struct omp_declare_variant_hasher): Delete.
	(omp_declare_variant_hasher::hash): Delete.
	(omp_declare_variant_hasher::equal): Delete.
	(omp_declare_variants): Delete.
	(omp_declare_variant_alt_hasher): Delete.
	(omp_declare_variant_alt_hasher::hash): Delete.
	(omp_declare_variant_alt_hasher::equal): Delete.
	(omp_declare_variant_alt): Delete.
	(omp_lto_output_declare_variant_alt): Delete.
	(omp_lto_input_declare_variant_alt): Delete.
	(includes): Delete unnecessary include of gt-omp-general.h.
	* omp-offload.cc (execute_omp_device_lower): Remove references
	to deleted bit.
	(pass_omp_device_lower::gate): Likewise.
	* omp-simd-clone.cc (simd_clone_create): Likewise.
	* passes.cc (ipa_write_summaries): Likeise.
	* symtab.cc (symtab_node::get_partitioning_class): Likewise.
	* tree-inline.cc (expand_call_inline): Likewise.
	(tree_function_versioning): Likewise.

2025-01-14  Sandra Loosemore  <sloosemore@baylibre.com>
	    Kwok Cheung Yeung  <kcy@codesourcery.com>
	    Sandra Loosemore  <sandra@codesourcery.com>
	    Marcel Vollweiler  <marcel@codesourcery.com>

	PR middle-end/114596
	PR middle-end/112779
	PR middle-end/113904
	* Makefile.in (GTFILES): Move omp-general.h earlier; required
	because of moving score_wide_int declaration to that file.
	* cgraph.h (struct cgraph_node): Add has_omp_variant_constructs flag.
	* cgraphclones.cc (cgraph_node::create_clone): Propagate
	has_omp_variant_constructs flag.
	* gimplify.cc (omp_resolved_variant_calls): New.
	(expand_late_variant_directive): New.
	(find_supercontext): New.
	(gimplify_variant_call_expr): New.
	(gimplify_call_expr): Adjust parameters to make fallback available.
	Update processing for "declare variant" substitution.
	(is_gimple_stmt): Add OMP_METADIRECTIVE.
	(omp_construct_selector_matches): Ifdef out unused function.
	(omp_get_construct_context): New.
	(gimplify_omp_dispatch): Replace call to deleted function
	omp_resolve_declare_variant with equivalent logic.
	(expand_omp_metadirective): New.
	(expand_late_variant_directive): New.
	(gimplify_omp_metadirective): New.
	(gimplify_expr): Adjust arguments to gimplify_call_expr.  Add
	cases for OMP_METADIRECTIVE, OMP_NEXT_VARIANT, and
	OMP_TARGET_DEVICE_MATCHES.
	(gimplify_function_tree): Initialize/clean up
	omp_resolved_variant_calls.
	* gimplify.h (omp_construct_selector_matches): Delete declaration.
	(omp_get_construct_context): Declare.
	* lto-cgraph.cc (lto_output_node): Write has_omp_variant_constructs.
	(input_overwrite_node): Read has_omp_variant_constructs.
	* omp-builtins.def (BUILT_IN_OMP_GET_NUM_DEVICES): New.
	* omp-expand.cc (expand_omp_taskreg): Propagate
	has_omp_variant_constructs.
	(expand_omp_target): Likewise.
	* omp-general.cc (omp_maybe_offloaded): Add construct_context
	parameter; use it instead of querying gimplifier state.  Add
	comments.
	(omp_context_name_list_prop): Do not test lang_GNU_Fortran in
	offload compiler, just use the string as-is.
	(expr_uses_parm_decl): New.
	(omp_check_context_selector): Add metadirective_p parameter.
	Remove sorry for target_device selector.  Add additional checks
	specific to metadirective or declare variant.
	(make_omp_metadirective_variant): New.
	(omp_construct_traits_match): New.
	(omp_context_selector_matches): Temporarily ifdef out the previous
	code, and add a new implementation based on the old one with
	different parameters, some unnecessary loops removed, and code
	re-indented.
	(omp_target_device_matches_on_host): New.
	(resolve_omp_target_device_matches): New.
	(omp_construct_simd_compare): Support matching of "simdlen" and
	"aligned" clauses.
	(omp_context_selector_set_compare): Make static.  Adjust call to
	omp_construct_simd_compare.
	(score_wide_int): Move declaration to omp-general.h.
	(omp_selector_is_dynamic): New.
	(omp_device_num_check): New.
	(omp_dynamic_cond): New.
	(omp_context_compute_score): Ifdef out the old version and
	re-implement with different parameters.
	(omp_complete_construct_context): New.
	(omp_resolve_late_declare_variant): Ifdef out.
	(omp_declare_variant_remove_hook): Likewise.
	(omp_resolve_declare_variant): Likewise.
	(sort_variant): New.
	(omp_get_dynamic_candidates): New.
	(omp_declare_variant_candidates): New.
	(omp_metadirective_candidates): New.
	(omp_early_resolve_metadirective): New.
	(omp_resolve_variant_construct): New.
	* omp-general.h (score_wide_int): Moved here from omp-general.cc.
	(struct omp_variant): New.
	(make_omp_metadirective_variant): Declare.
	(omp_construct_traits_to_codes): Delete declaration.
	(omp_check_context_selector): Adjust parameters.
	(omp_context_selector_matches): Likewise.
	(omp_context_selector_set_compare): Delete declaration.
	(omp_resolve_declare_variant): Likewise.
	(omp_declare_variant_candidates): Declare.
	(omp_metadirective_candidates): Declare.
	(omp_get_dynamic_candidates): Declare.
	(omp_early_resolve_metadirective): Declare.
	(omp_resolve_variant_construct): Declare.
	(omp_dynamic_cond): Declare.
	* omp-offload.cc (resolve_omp_variant_cookies): New.
	(execute_omp_device_lower): Call the above function to resolve
	variant directives.  Remove call to omp_resolve_declare_variant.
	(pass_omp_device_lower::gate): Check has_omp_variant_construct bit.
	* omp-simd-clone.cc (simd_clone_create): Propagate
	has_omp_variant_constructs bit.
	* tree-inline.cc (expand_call_inline): Likewise.
	(tree_function_versioning): Likewise.

2025-01-14  Sandra Loosemore  <sloosemore@baylibre.com>
	    Kwok Cheung Yeung  <kcy@codesourcery.com>
	    Sandra Loosemore  <sandra@codesourcery.com>

	* doc/generic.texi (OpenMP): Document OMP_METADIRECTIVE,
	OMP_NEXT_VARIANT, and OMP_TARGET_DEVICE_MATCHES.
	* fold-const.cc (operand_compare::hash_operand): Ignore
	the new nodes.
	* gimple-expr.cc (is_gimple_val): Allow OMP_NEXT_VARIANT
	and OMP_TARGET_DEVICE_MATCHES.
	* gimple.cc (get_gimple_rhs_num_ops): OMP_NEXT_VARIANT and
	OMP_TARGET_DEVICE_MATCHES are both GIMPLE_SINGLE_RHS.
	* tree-cfg.cc (tree_node_can_be_shared): Allow sharing of
	OMP_NEXT_VARIANT.
	* tree-inline.cc (remap_gimple_op_r): Ignore subtrees of
	OMP_NEXT_VARIANT.
	* tree-pretty-print.cc (dump_generic_node): Handle OMP_METADIRECTIVE,
	OMP_NEXT_VARIANT, and OMP_TARGET_DEVICE_MATCHES.
	* tree-ssa-operands.cc (operands_scanner::get_expr_operands):
	Ignore operands of OMP_NEXT_VARIANT and OMP_TARGET_DEVICE_MATCHES.
	* tree.def (OMP_METADIRECTIVE): New.
	(OMP_NEXT_VARIANT): New.
	(OMP_TARGET_DEVICE_MATCHES): New.
	* tree.h (OMP_METADIRECTIVE_VARIANTS): New.
	(OMP_METADIRECTIVE_VARIANT_SELECTOR): New.
	(OMP_METADIRECTIVE_VARIANT_DIRECTIVE): New.
	(OMP_METADIRECTIVE_VARIANT_BODY): New.
	(OMP_NEXT_VARIANT_INDEX): New.
	(OMP_NEXT_VARIANT_STATE): New.
	(OMP_TARGET_DEVICE_MATCHES_SELECTOR): New.
	(OMP_TARGET_DEVICE_MATCHES_PROPERTIES): New.

2025-01-14  Alexandre Oliva  <oliva@adacore.com>

	PR tree-optimization/118456
	* gimple-fold.cc (decode_field_reference): Punt if shifting
	after changing signedness.
	(fold_truth_andor_for_ifcombine): Check extension bits in
	constants before clipping.

2025-01-14  Robin Dapp  <rdapp@ventanamicro.com>

	PR target/118154
	* config/riscv/riscv-vsetvl.cc (MAX_LMUL): New define.
	(pre_vsetvl::earliest_fuse_vsetvl_info): Use.
	(pre_vsetvl::pre_global_vsetvl_info): New predicate with equal
	ratio.
	* config/riscv/riscv-vsetvl.def: Use.

2025-01-14  Robin Dapp  <rdapp@ventanamicro.com>

	PR middle-end/118140
	* gimple-match-exports.cc (maybe_resimplify_conditional_op): Add
	COND_EXPR when we simplified to a scalar gimple value but still
	have an else value.

2025-01-14  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/118405
	* tree-vect-stmts.cc (vectorizable_load): When we fall back
	to scalar loads make sure we properly convert to vector(1) T
	when there was only a single vector element.

2025-01-14  Robin Dapp  <rdapp.gcc@gmail.com>

	* config/riscv/riscv-v.cc (expand_const_vector): Shift in Xmode.

2025-01-14  Jiufu Guo  <guojiufu@linux.ibm.com>

	PR target/116030
	* config/rs6000/vsx.md (vsx_stxvd2x4_le_const_<mode>): Add clobber
	and guard with !altivec_indexed_or_indirect_operand.

2025-01-14  Robin Dapp  <rdapp.gcc@gmail.com>

	PR target/117682
	* config/riscv/riscv-v.cc (expand_const_vector): Fall back to
	merging if either step is negative.

2025-01-13  Xi Ruoyao  <xry111@xry111.site>

	PR target/115921
	* config/riscv/riscv.md (<optab>_shift_reverse): Remove
	check for TARGET_ZBA.

2025-01-13  Richard Sandiford  <richard.sandiford@arm.com>

	PR target/118418
	* simplify-rtx.cc (simplify_context::simplify_relational_operation_1):
	Take STORE_FLAG_VALUE into account when handling signed comparisons
	of comparison results.

2025-01-13  Xi Ruoyao  <xry111@xry111.site>

	PR target/115921
	* config/riscv/riscv.md (<optab>_shift_reverse): Only check
	popcount_hwi if !TARGET_ZBS.

2025-01-13  Jin Ma  <jinma@linux.alibaba.com>

	* config/riscv/riscv-vsetvl.cc (demand_system::use_max_sew): Also
	set the ratio for PREV.

2025-01-13  Vineet Gupta  <vineetg@rivosinc.com>

	* config/riscv/riscv.cc (riscv_register_move_cost): Remove buggy
	check.

2025-01-13  Jin Ma  <jinma@linux.alibaba.com>

	* config/riscv/riscv.cc (riscv_build_integer_1): Change
	1UL/1ULL to HOST_WIDE_INT_1U.

2025-01-13  Jeff Law  <jlaw@ventanamicro.com>

	PR rtl-optimization/107455
	* postreload.cc (reload_cse_regs_1): Take advantage of conditional
	equivalences.

2025-01-13  Alexandre Oliva  <oliva@adacore.com>

	PR tree-optimization/118409
	* gimple-fold.cc (fold_truth_andor_for_ifcombine): Apply the
	signbit mask to the right-hand XOR operand too.

2025-01-13  Jakub Jelinek  <jakub@redhat.com>

	PR target/115910
	* expr.cc (expand_expr_divmod): Prefix the TDF_DETAILS note with
	";; " and add a space before (needed tie breaker).  Formatting fixes.

2025-01-13  Richard Biener  <rguenther@suse.de>
	    Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>

	PR tree-optimization/117119
	* tree-data-ref.cc (initialize_matrix_A): Check whether
	an INTEGER_CST fits in HWI, otherwise return chrec_dont_know.

2025-01-13  Michal Jires  <mjires@suse.cz>

	PR lto/118181
	* lto-ltrans-cache.cc (ltrans_file_cache::create_item):
	Pass checksum by reference.
	* lto-ltrans-cache.h: Likewise.

2025-01-13  Michal Jires  <mjires@suse.cz>

	* lockfile.cc (LOCKFILE_USE_FCNTL): New.
	(lockfile::lock_write): Use LOCKFILE_USE_FCNTL.
	(lockfile::try_lock_write): Use LOCKFILE_USE_FCNTL.
	(lockfile::lock_read): Use LOCKFILE_USE_FCNTL.
	(lockfile::unlock): Use LOCKFILE_USE_FCNTL.
	(lockfile::lockfile_supported): Use LOCKFILE_USE_FCNTL.

2025-01-13  liuhongt  <hongtao.liu@intel.com>

	* config/i386/i386-expand.cc (ix86_expand_vecop_qihi2):
	Refactor to avoid redundant TARGET_AVX512BW in many places.

2025-01-13  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/117997
	PR middle-end/118415
	* expr.cc (assemble_crc_table): Make static, remove id argument,
	use output_constant_def.  Emit note if -fdump-rtl-expand-details
	about which table has been emitted.
	(generate_crc_table): Make static, adjust assemble_crc_table
	caller, call it always.
	(calculate_table_based_CRC): Make static.
	* internal-fn.cc (expand_crc_optab_fn): Emit note if
	-fdump-rtl-expand-details about using optab for crc.  Formatting fix.

2025-01-12  Maciej W. Rozycki  <macro@orcam.me.uk>

	* config/alpha/alpha.cc (alpha_expand_block_move): Use a HImode
	subreg of a DImode register to hold data from an aligned HImode
	load.

2025-01-12  Maciej W. Rozycki  <macro@orcam.me.uk>

	* config/alpha/alpha.cc (alpha_expand_block_move): Merge loaded
	data from pairs of SImode registers into single DImode registers
	if to be used with unaligned stores.

2025-01-12  Maciej W. Rozycki  <macro@orcam.me.uk>

	* config/alpha/alpha.cc (alpha_option_override): Ignore CPU
	flags corresponding to features the enabling or disabling of
	which has been requested with an individual feature option.

2025-01-12  Maciej W. Rozycki  <macro@orcam.me.uk>

	PR middle-end/64242
	* config/alpha/alpha.md (`builtin_longjmp'): Restore frame
	pointer last.  Add frame clobber and schedule blockage.

2025-01-12  Maciej W. Rozycki  <macro@orcam.me.uk>

	* config/alpha/alpha.md (builtin_longjmp): Add memory clobbers.

2025-01-12  Richard Biener  <rguenther@suse.de>

	* tree-vect-slp.cc (vect_analyze_slp): Release saved_stmts
	vector.
	(vect_build_slp_tree_2): Release new_oprnds_info when not
	used.
	(vect_analyze_slp): Release root_stmts when gcond SLP
	build fails.

2025-01-12  Andrew Pinski  <quic_apinski@quicinc.com>

	PR middle-end/118411
	* final.cc (get_attr_length_1): Handle asm for CALL_INSN
	and JUMP_INSNs.

2025-01-11  mengqinggang  <mengqinggang@loongson.cn>

	* config/loongarch/lasx.md: Use new loongarch_output_move.
	* config/loongarch/loongarch-protos.h (loongarch_output_move):
	Change parameters from (rtx, rtx) to (rtx *).
	* config/loongarch/loongarch.cc (loongarch_output_move):
	Generate final immediate for lu12i.w and lu52i.d.
	* config/loongarch/loongarch.md:
	Generate final immediate for lu32i.d and lu52i.d.
	* config/loongarch/lsx.md: Use new loongarch_output_move.

2025-01-11  Andrew MacLeod  <amacleod@redhat.com>

	PR tree-optimization/88575
	* vr-values.cc (simplify_using_ranges::fold_cond_with_ops): Query
	relation between op0 and op1 and utilize it.
	(simplify_using_ranges::simplify): Do not eliminate float checks.

2025-01-10  Alex Coplan  <alex.coplan@arm.com>

	PR tree-optimization/118211
	PR tree-optimization/116126
	* tree-vect-loop.cc (vect_compute_single_scalar_iteration_cost):
	Don't skip over gconds.

2025-01-10  Alex Coplan  <alex.coplan@arm.com>

	PR tree-optimization/118211
	PR tree-optimization/116126
	* tree-vect-loop-manip.cc (vect_do_peeling): Adjust skip_vector
	condition to only omit the edge if we're versioning for
	alignment.

2025-01-10  Tamar Christina  <Tamar.Christina@arm.com>
	    Alex Coplan  <alex.coplan@arm.com>

	PR tree-optimization/118211
	PR tree-optimization/116126
	* tree-vect-loop-manip.cc (vect_do_peeling): Update immediate
	dominators of nodes that were dominated by the prolog skip block
	after inserting vector skip edge.  Initialize prolog variable to
	NULL to avoid bogus -Wmaybe-uninitialized during bootstrap.

2025-01-10  Alex Coplan  <alex.coplan@arm.com>

	PR tree-optimization/118211
	PR tree-optimization/116126
	* tree-vect-loop-manip.cc (vect_do_peeling): Avoid emitting an
	epilogue guard for inverted early-exit loops.

2025-01-10  Alex Coplan  <alex.coplan@arm.com>
	    Tamar Christina  <tamar.christina@arm.com>

	PR tree-optimization/118211
	PR tree-optimization/116126
	* tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
	Set need_peeling_for_alignment flag on read DRs instead of
	failing vectorization.  Punt on gathers.
	(dr_misalignment): Handle non-constant target alignments.
	(vect_compute_data_ref_alignment): If need_peeling_for_alignment
	flag is set on the DR, then override the target alignment chosen
	by the preferred_vector_alignment hook to choose a safe
	alignment.
	(vect_supportable_dr_alignment): Override
	support_vector_misalignment hook if need_peeling_for_alignment
	is set on the DR: in this case we must return
	dr_unaligned_unsupported in order to force peeling.
	* tree-vect-loop-manip.cc (vect_do_peeling): Allow prolog
	peeling by a compile-time non-constant amount.
	* tree-vectorizer.h (dr_vec_info): Add new flag
	need_peeling_for_alignment.

2025-01-10  Tamar Christina  <tamar.christina@arm.com>

	* config/aarch64/aarch64-cores.def (AARCH64_CORE): Fix cortex-x4 parts
	num.

2025-01-10  Richard Biener  <rguenther@suse.de>

	* df-core.cc (rest_of_handle_df_finish): Release dflow for
	problems without free function (like LR).
	* gimple-crc-optimization.cc (crc_optimization::loop_may_calculate_crc):
	Release loop_bbs on all exits.
	* tree-vectorizer.h (supportable_indirect_convert_operation): Change.
	* tree-vect-generic.cc (expand_vector_conversion): Adjust.
	* tree-vect-stmts.cc (vectorizable_conversion): Use auto_vec for
	converts.
	(supportable_indirect_convert_operation): Get a reference to
	the output vector of converts.

2025-01-10  Christophe Lyon  <christophe.lyon@linaro.org>

	PR target/118332
	* config/arm/arm-mve-builtins.cc (wrap_type_in_struct): Delete.
	(register_type_decl): Delete.
	(register_builtin_tuple_types): Use
	lang_hooks.types.simulate_record_decl.

2025-01-10  Richard Biener  <rguenther@suse.de>

	* gcse.cc (pass_hardreg_pre::gate): Wrap possibly unused
	fun argument.

2025-01-10  Richard Biener  <rguenther@suse.de>

	PR rtl-optimization/117467
	PR rtl-optimization/117934
	* ext-dce.cc (ext_dce_execute): Do nothing if a memory
	allocation estimate exceeds what is allowed by
	--param max-gcse-memory.

2025-01-10  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>

	* config/s390/s390-protos.h (s390_emit_compare): Add mode
	parameter for the resulting RTX.
	* config/s390/s390.cc (s390_emit_compare): Dito.
	(s390_emit_compare_and_swap): Change.
	(s390_expand_vec_strlen): Change.
	(s390_expand_cs_hqi): Change.
	(s390_expand_split_stack_prologue): Change.
	* config/s390/s390.md (*add<mode>3_carry1_cc): Renamed to ...
	(add<mode>3_carry1_cc): this and in order to use the
	corresponding gen function, encode CC mode into pattern.
	(*sub<mode>3_borrow_cc): Renamed to ...
	(sub<mode>3_borrow_cc): this and in order to use the
	corresponding gen function, encode CC mode into pattern.
	(*add<mode>3_alc_carry1_cc): Renamed to ...
	(add<mode>3_alc_carry1_cc): this and in order to use the
	corresponding gen function, encode CC mode into pattern.
	(sub<mode>3_slb_borrow1_cc): New.
	(uaddc<mode>5): New.
	(usubc<mode>5): New.

2025-01-10  Andrew Carlotti  <andrew.carlotti@arm.com>

	* doc/passes.texi: Document hardreg PRE pass.

2025-01-10  Andrew Carlotti  <andrew.carlotti@arm.com>

	* config/aarch64/aarch64.h (HARDREG_PRE_REGNOS): New macro.
	* gcse.cc (doing_hardreg_pre_p): New global variable.
	(do_load_motion): New boolean check.
	(current_hardreg_regno): New global variable.
	(compute_local_properties): Unset transp for hardreg clobbers.
	(prune_hardreg_uses): New function.
	(want_to_gcse_p): Use different checks for hardreg PRE.
	(oprs_unchanged_p): Disable load motion for hardreg PRE pass.
	(hash_scan_set): For hardreg PRE, skip non-hardreg sets and
	check for hardreg clobbers.
	(record_last_mem_set_info): Skip for hardreg PRE.
	(compute_pre_data): Prune hardreg uses from transp bitmap.
	(pre_expr_reaches_here_p_work): Add sentence to comment.
	(insert_insn_start_basic_block): New functions.
	(pre_edge_insert): Don't add hardreg sets to predecessor block.
	(pre_delete): Use hardreg for the reaching reg.
	(reset_hardreg_debug_uses): New function.
	(pre_gcse): For hardreg PRE, reset debug uses and don't insert
	copies.
	(one_pre_gcse_pass): Disable load motion for hardreg PRE.
	(execute_hardreg_pre): New.
	(class pass_hardreg_pre): New.
	(pass_hardreg_pre::gate): New.
	(make_pass_hardreg_pre): New.
	* passes.def (pass_hardreg_pre): New pass.
	* tree-pass.h (make_pass_hardreg_pre): New.

2025-01-10  Andrew Carlotti  <andrew.carlotti@arm.com>

	* multiple_target.cc
	(redirect_to_specific_clone): Assert that "target" attribute is
	used for FMV before checking it.
	(ipa_target_clone): Skip redirect_to_specific_clone on some
	targets.

2025-01-10  Andrew Carlotti  <andrew.carlotti@arm.com>

	* doc/invoke.texi: Add new AArch64 flags.

2025-01-10  Andrew Carlotti  <andrew.carlotti@arm.com>

	* config/aarch64/aarch64-arches.def (V8_7A): Add XS.
	* config/aarch64/aarch64-option-extensions.def (XS): New flag.

2025-01-10  Andrew Carlotti  <andrew.carlotti@arm.com>

	* config/aarch64/aarch64-arches.def (V8_7A): Add WFXT.
	* config/aarch64/aarch64-option-extensions.def (WFXT): New flag.

2025-01-10  Andrew Carlotti  <andrew.carlotti@arm.com>

	* config/aarch64/aarch64-arches.def (V8_4A): Add RCPC2.
	* config/aarch64/aarch64-option-extensions.def
	(RCPC2): New flag.
	(RCPC3): Add RCPC2 dependency.
	* config/aarch64/aarch64.h (TARGET_RCPC2): Use new flag.

2025-01-10  Andrew Carlotti  <andrew.carlotti@arm.com>

	* config/aarch64/aarch64-arches.def (V8_5A): Add FLAGM2.
	* config/aarch64/aarch64-option-extensions.def (FLAGM2): New flag.

2025-01-10  Andrew Carlotti  <andrew.carlotti@arm.com>

	* config/aarch64/aarch64-arches.def (V8_5A): Add FRINTTS
	* config/aarch64/aarch64-option-extensions.def (FRINTTS): New flag.
	* config/aarch64/aarch64.h (TARGET_FRINT): Use new flag.
	* config/aarch64/arm_acle.h: Use new flag for frintts intrinsics.
	* config/aarch64/arm_neon.h: Ditto.

2025-01-10  Andrew Carlotti  <andrew.carlotti@arm.com>

	* config/aarch64/aarch64-arches.def (V8_3A): Add JSCVT.
	* config/aarch64/aarch64-option-extensions.def (JSCVT): New flag.
	* config/aarch64/aarch64.h (TARGET_JSCVT): Use new flag.
	* config/aarch64/arm_acle.h: Use new flag for jscvt intrinsics.

2025-01-10  Andrew Carlotti  <andrew.carlotti@arm.com>

	* config/aarch64/aarch64-arches.def (V8_3A): Add FCMA.
	* config/aarch64/aarch64-option-extensions.def (FCMA): New flag.
	(SVE): Add FCMA dependency.
	* config/aarch64/aarch64.h (TARGET_COMPLEX): Use new flag.
	* config/aarch64/arm_neon.h: Use new flag for fcma intrinsics.

2025-01-10  Andrew Carlotti  <andrew.carlotti@arm.com>

	* config/aarch64/aarch64.cc
	(aarch64_expand_epilogue): Use TARGET_PAUTH.
	* config/aarch64/aarch64.md: Update comment.

2025-01-10  Richard Sandiford  <richard.sandiford@arm.com>

	PR rtl-optimization/117186
	* rtl.h (simplify_context::simplify_logical_relational_operation): Add
	an invert0_p parameter.
	* simplify-rtx.cc (unsigned_comparison_to_mask): New function.
	(mask_to_unsigned_comparison): Likewise.
	(comparison_code_valid_for_mode): Delete.
	(simplify_context::simplify_logical_relational_operation): Add
	an invert0_p parameter.  Handle AND and XOR.  Handle unsigned
	comparisons.  Handle always-false results.  Ignore the low bit
	of the mask if the operands are always ordered and remove the
	then-redundant check of comparison_code_valid_for_mode.  Check
	for side-effects in the operands before simplifying them away.
	(simplify_context::simplify_binary_operation_1): Remove
	simplification of (compare (gt ...) (lt ...)) and instead...
	(simplify_context::simplify_relational_operation_1): ...handle
	comparisons of comparisons here.
	(test_comparisons): New function.
	(test_scalar_ops): Call it.

2025-01-10  Alexandre Oliva  <oliva@adacore.com>

	* gimple-fold.cc (decode_field_reference): Drop misuses of
	uniform_integer_cst_p.
	(fold_truth_andor_for_ifcombine): Likewise.

2025-01-10  Alexandre Oliva  <oliva@adacore.com>

	PR tree-optimization/118344
	* gimple-fold.cc (fold_truth_andor_for_ifcombine): Fix typo in
	rr_and_mask's type adjustment test.

2025-01-10  Alexandre Oliva  <oliva@adacore.com>

	* gimple-fold.cc (decode_field_reference): Add xor_pand_mask.
	Propagate pand_mask to the right-hand xor operand.  Don't
	require the right-hand xor operand to be a constant.
	(fold_truth_andor_for_ifcombine): Pass right-hand mask when
	appropriate.

2025-01-10  Alexandre Oliva  <oliva@adacore.com>

	PR tree-optimization/118206
	* gimple-fold.cc (decode_field_reference): Account for upper
	bits dropped by narrowing conversions whether before or after
	a right shift.
	(fold_truth_andor_for_ifcombine): Fold masks, compares, and
	combined results.

2025-01-10  Alexandre Oliva  <oliva@adacore.com>

	* gimple-fold.cc (fold_truth_andor_for_ifcombine): Limit
	boundary choice by word size as well.  Try aligned double-word
	loads as a last resort.

2025-01-10  Martin Jambor  <mjambor@suse.cz>

	PR ipa/118138
	* ipa-cp.cc (ipacp_value_safe_for_type): Return the appropriate
	type instead of a bool, accept NULL_TREE VALUEs.
	(propagate_vals_across_arith_jfunc): Use the new returned value of
	ipacp_value_safe_for_type.
	(propagate_vals_across_ancestor): Likewise.
	(propagate_scalar_across_jump_function): Likewise.

2025-01-10  chenxiaolong  <chenxiaolong@loongson.cn>
	    Deng Jianbo  <dengjianbo@loongson.cn>.

	* config/loongarch/loongarch.cc
	(loongarch_builtin_vectorization_cost): Modify the
	construction cost of the vec_construct vector.

2025-01-09  Tamar Christina  <tamar.christina@arm.com>

	PR target/118188
	* config/aarch64/aarch64.cc (aarch64_vector_costs::count_ops): Adjust
	throughput of emulated gather and scatters.

2025-01-09  Vladimir N. Makarov  <vmakarov@redhat.com>

	PR target/118017
	* lra-constraints.cc (inherit_reload_reg): Check reg class on uniformity.

2025-01-09  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>

	PR target/118362
	* config/s390/s390.cc (s390_constant_via_vgbm_p): Allow at most
	16-byte vectors.

2025-01-09  Christophe Lyon  <christophe.lyon@linaro.org>

	PR target/118131
	* config/arm/arm.h (VALID_MVE_STRUCT_MODE): Accept TI, OI and XI
	modes again.

2025-01-09  Thomas Schwinge  <tschwinge@baylibre.com>

	PR target/65181
	* config/nvptx/nvptx.cc (nvptx_get_drap_rtx): Handle
	'!TARGET_SOFT_STACK'.
	* config/nvptx/nvptx.md (define_c_enum "unspec"): Add
	'UNSPEC_STACKSAVE', 'UNSPEC_STACKRESTORE'.
	(define_expand "allocate_stack", define_expand "save_stack_block")
	(define_expand "save_stack_block"): Handle '!TARGET_SOFT_STACK',
	PTX 'alloca'.
	(define_insn "@nvptx_alloca_<mode>")
	(define_insn "@nvptx_stacksave_<mode>")
	(define_insn "@nvptx_stackrestore_<mode>"): New.
	* doc/invoke.texi (Nvidia PTX Options): Update '-msoft-stack',
	'-mno-soft-stack'.
	* doc/sourcebuild.texi (nvptx-specific attributes): Document
	'nvptx_runtime_alloca_ptx'.
	(Add Options): Document 'nvptx_alloca_ptx'.

2025-01-09  Richard Biener  <rguenther@suse.de>

	* cfgloopmanip.cc (duplicate_loop_body_to_header_edge): When
	copying to the header edge first redirect the entry to the
	new loop and then the exit to the old to avoid PHI node
	re-allocation.

2025-01-09  H.J. Lu  <hjl.tools@gmail.com>

	PR rtl-optimization/118266
	* ree.cc (add_removable_extension): Skip extension on fixed
	register.

2025-01-09  Jakub Jelinek  <jakub@redhat.com>
	    Andrew Pinski  <quic_apinski@quicinc.com>

	PR tree-optimization/117927
	* tree-pass.h (PROP_last_full_fold): Define.
	* passes.def: Add last= parameters to pass_forwprop.
	* tree-ssa-forwprop.cc (pass_forwprop): Add last_p non-static
	data member and initialize it in the ctor.
	(pass_forwprop::set_pass_param): New method.
	(pass_forwprop::execute): Set PROP_last_full_fold in curr_properties
	at the start if last_p.
	* match.pd (a rrotate (32-b) -> a lrotate b): Only optimize either
	if @2 is known not to be equal to prec or if during/after last
	forwprop the subtraction has single use and prec is power of two; in
	that case transform it into orotate by masked count.

2025-01-09  Haochen Jiang  <haochen.jiang@intel.com>

	* common/config/i386/cpuinfo.h (get_intel_cpu): Remove 0x00.

2025-01-09  xuli  <xuli1@eswincomputing.com>

	* config/riscv/riscv-vector-builtins.cc (function_builder::add_unique_function):
	Only register overloaded intrinsic for g++.
	Only insert non_overloaded_function_table for gcc.
	(function_builder::add_overloaded_function): Only register overloaded intrinsic for gcc.
	(handle_pragma_vector): Only initialize non_overloaded_function_table for gcc.

2025-01-09  Tobias Burnus  <tburnus@baylibre.com>

	* builtin-types.def (BT_FN_PTRMODE_PTR_INT_PTR): Add.
	* gimplify.cc (gimplify_call_expr): Add error for multiple
	list items to the OpenMP interop clause if no device clause;
	continue instead of restarting after append_args handling.
	(gimplify_omp_dispatch): Extract device number from the
	single interop-clause list item.
	* omp-builtins.def (BUILT_IN_OMP_GET_INTEROP_INT): Add.

2025-01-08  Thomas Schwinge  <tschwinge@baylibre.com>

	PR target/65181
	* config/nvptx/nvptx.cc (default_ptx_version_option): For
	'-march=sm_52' and higher, default at least to '-mptx=7.3'.
	* doc/invoke.texi (Nvidia PTX Options): Update '-mptx=[...]'.

2025-01-08  Thomas Schwinge  <tschwinge@baylibre.com>

	* config/nvptx/nvptx-opts.h (enum ptx_version): Add
	'PTX_VERSION_7_3'.
	* config/nvptx/nvptx.cc (ptx_version_to_string)
	(ptx_version_to_number): Adjust.
	* config/nvptx/nvptx.h (TARGET_PTX_7_3): New.
	* config/nvptx/nvptx.opt (Enum(ptx_version)): Add 'EnumValue'
	'7.3' for 'PTX_VERSION_7_3'.
	* doc/invoke.texi (Nvidia PTX Options): Document '-mptx=7.3'.

2025-01-08  Thomas Schwinge  <tschwinge@baylibre.com>

	* doc/sourcebuild.texi (Effective-Target Keywords): Document
	'nvptx_softstack'.

2025-01-08  Thomas Schwinge  <tschwinge@baylibre.com>

	PR target/65181
	* config/nvptx/nvptx.h (STACK_SAVEAREA_MODE): '#define'.
	* config/nvptx/nvptx.md [!TARGET_SOFT_STACK]
	(save_stack_function): 'define_expand'.
	(restore_stack_function): Handle '!TARGET_SOFT_STACK'.

2025-01-08  Thomas Schwinge  <tschwinge@baylibre.com>

	PR target/65181
	* config/nvptx/nvptx.md [!TARGET_SOFT_STACK] (save_stack_block):
	'define_expand'.

2025-01-08  Thiago Jung Bauermann  <thiago.bauermann@linaro.org>

	* configure.ac: Fix check for HAVE_GAS_SHF_MERGE on Arm targets.
	* configure: Regenerate.

2025-01-08  Richard Sandiford  <richard.sandiford@arm.com>

	PR target/107102
	* config/aarch64/aarch64.cc (aarch64_function_ok_for_sibcall): Only
	reject calls with different PCSes if the callee clobbers register
	state that the caller must preserve.

2025-01-08  Tobias Burnus  <tburnus@baylibre.com>

	* gimplify.cc (gimplify_call_expr): Disable variant function's
	append_args in 'omp dispatch' when invoking the variant directly
	and not through the base function.

2025-01-08  Thomas Schwinge  <tschwinge@baylibre.com>

	* doc/invoke.texi (Nvidia PTX Options): Update '-march-map=sm_50'.

2025-01-08  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/117979
	* tree-ssa-dce.cc (make_forwarders_with_degenerate_phis):
	Properly update the irreducible region state.

2025-01-08  Jakub Jelinek  <jakub@redhat.com>

	* dwarf2out.cc (break_out_comdat_types): Copy over
	DW_AT_language_{name,version} if present.
	(output_skeleton_debug_sections): Remove also
	DW_AT_language_{name,version}.
	(gen_compile_unit_die): For C17, C23, C2Y, C++17, C++20, C++23
	and C++26 emit for -gdwarf-5 -gno-strict-dwarf also
	DW_AT_language_{name,version} attributes.

2025-01-08  Richard Biener  <rguenther@suse.de>

	PR middle-end/118325
	* tree-nested.cc (convert_nl_goto_reference): Assign proper
	context to generated artificial label.

2025-01-08  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/118269
	* tree-vect-loop.cc (vect_create_epilog_for_reduction):
	Use the correct stmt for the REDUC_GROUP_FIRST_ELEMENT lookup.

2025-01-08  Christophe Lyon  <christophe.lyon@linaro.org>

	PR target/118332
	* config/arm/arm-mve-builtins.cc (wrap_type_in_struct): Use 'val'
	instead of '__val'.

2025-01-08  Haochen Jiang  <haochen.jiang@intel.com>

	* config/i386/amxavx512intrin.h
	(_tile_cvtrowps2pbf16h_internal): Rename to...
	(_tile_cvtrowps2bf16h_internal): ...this.
	(_tile_cvtrowps2pbf16hi_internal): Rename to...
	(_tile_cvtrowps2bf16hi_internal): ...this.
	(_tile_cvtrowps2pbf16l_internal): Rename to...
	(_tile_cvtrowps2bf16l_internal): ...this.
	(_tile_cvtrowps2pbf16li_internal): Rename to...
	(_tile_cvtrowps2bf16li_internal): ...this.
	(_tile_cvtrowps2pbf16h): Rename to...
	(_tile_cvtrowps2bf16h): ...this.
	(_tile_cvtrowps2pbf16hi): Rename to...
	(_tile_cvtrowps2bf16hi): ...this.
	(_tile_cvtrowps2pbf16l): Rename to...
	(_tile_cvtrowps2bf16l): ...this.
	(_tile_cvtrowps2pbf16li): Rename to...
	(_tile_cvtrowps2bf16li): ...this.

2025-01-08  Hongyu Wang  <hongyu.wang@intel.com>

	* config/i386/i386.cc (ix86_noce_max_ifcvt_seq_cost): Adjust
	cost with ix86_tune_cost->br_mispredict_scale.
	* config/i386/i386.h (processor_costs): Add br_mispredict_scale.
	* config/i386/x86-tune-costs.h: Add new br_mispredict_scale to
	all processor_costs, in which icelake_cost/alderlake_cost
	with value COSTS_N_INSNS (2) + 3 and other processor with value
	COSTS_N_INSNS (2).

2025-01-07  Pan Li  <pan2.li@intel.com>

	* match.pd: Update comments for sat_* pattern.

2025-01-07  Pan Li  <pan2.li@intel.com>

	* match.pd: Extract saturated value match for signed SAT_*.

2025-01-07  Pan Li  <pan2.li@intel.com>

	* match.pd: Refactor sorts of signed SAT_TRUNC match patterns

2025-01-07  Pan Li  <pan2.li@intel.com>

	* match.pd: Refactor sorts of signed SAT_SUB match patterns.

2025-01-07  Vineet Gupta  <vineetg@rivosinc.com>
	    Pan Li  <pan2.li@intel.com>

	PR target/117722
	* config/riscv/autovec.md: Add uabd expander.

2025-01-07  Tsung Chun Lin  <tclin914@gmail.com>

	* expr.cc (widest_fixed_size_mode_for_size): Prefer scalar modes
	over vector modes in more cases.

2025-01-07  Andreas Schwab  <schwab@suse.de>

	PR target/118137
	* config/riscv/sync.md ("lrsc_atomic_exchange<mode>"): Apply mask
	to shifted value.

2025-01-07  Jeff Law  <jlaw@ventanamicro.com>

	* config/ft32/ft32.md (casesi expander): Force operands[2] into
	a register if it's not a suitable rimm operand.

2025-01-07  Wilco Dijkstra  <wilco.dijkstra@arm.com>

	* common/config/aarch64/aarch64-common.cc: Switch off fschedule_insns.

2025-01-07  Wilco Dijkstra  <wilco.dijkstra@arm.com>

	* config/aarch64/aarch64.md (movhf_aarch64): Use aarch64_valid_fp_move.
	(movsf_aarch64): Likewise.
	(movdf_aarch64): Likewise.
	* config/aarch64/aarch64.cc (aarch64_valid_fp_move): New function.
	* config/aarch64/aarch64-protos.h (aarch64_valid_fp_move): Likewise.

2025-01-07  Paul-Antoine Arras  <parras@baylibre.com>

	* gimplify.cc (gimplify_call_expr): Create variable
	variant_substituted_p to control whether adjust_args applies.

2025-01-07  Tamar Christina  <tamar.christina@arm.com>

	PR tree-optimization/114932
	* tree-ssa-loop-ivopts.cc (alloc_iv): Perform affine unsigned fold.

2025-01-07  Andrew Pinski  <quic_apinski@quicinc.com>

	PR tree-optimization/105769
	* cfgexpand.cc (vars_ssa_cache::operator()): For constructors
	walk over the elements.

2025-01-07  Andrew Pinski  <quic_apinski@quicinc.com>

	PR middle-end/117426
	PR middle-end/111422
	* cfgexpand.cc (struct vars_ssa_cache): New class.
	(vars_ssa_cache::vars_ssa_cache): New constructor.
	(vars_ssa_cache::~vars_ssa_cache): New deconstructor.
	(vars_ssa_cache::create): New method.
	(vars_ssa_cache::exists): New method.
	(vars_ssa_cache::add_one): New method.
	(vars_ssa_cache::update): New method.
	(vars_ssa_cache::dump): New method.
	(add_scope_conflicts_2): Factor mostly out to
	vars_ssa_cache::operator(). New cache argument.
	Walk the bitmap cache for the stack variables addresses.
	(vars_ssa_cache::operator()): New method factored out from
	add_scope_conflicts_2. Rewrite to be a full walk of all operands
	and use a worklist.
	(add_scope_conflicts_1): Add cache new argument for the addr cache.
	Just call add_scope_conflicts_2 for the phi result instead of calling
	for the uses and don't call walk_stmt_load_store_addr_ops for phis.
	Update call to add_scope_conflicts_2 to add cache argument.
	(add_scope_conflicts): Add cache argument and update calls to
	add_scope_conflicts_1.

2025-01-07  Andrew Pinski  <quic_apinski@quicinc.com>

	* cfgexpand.cc (INVALID_STACK_INDEX): New defined.
	(decl_stack_index): New function.
	(visit_op): Use decl_stack_index.
	(visit_conflict): Likewise.
	(add_scope_conflicts_1): Likewise.

2025-01-07  Richard Biener  <rguenther@suse.de>

	PR rtl-optimization/118298
	* loop-unroll.cc (decide_unroll_constant_iterations): Honor
	loop->unroll even if the loop is too big for heuristics.

2025-01-07  Deng Jianbo  <dengjianbo@loongson.cn>

	* config/loongarch/loongarch.cc (loongarch_output_move):
	Optimize instructions for initializing fp regsiter to zero.

2025-01-07  Gaius Mulley  <gaiusmod2@gmail.com>

	PR modula2/118010
	* doc/gm2.texi (Compiler options): New option
	-fm2-file-offset-bits=.

2025-01-07  Jennifer Schmitz  <jschmitz@nvidia.com>

	* tree-vect-stmts.cc (vectorizable_store): Extend the use of
	n_adjacent_stores to also cover vec_to_scalar operations.
	* config/aarch64/aarch64-tuning-flags.def: Remove
	use_new_vector_costs as tuning option.
	* config/aarch64/aarch64.cc (aarch64_use_new_vector_costs_p):
	Remove.
	(aarch64_vector_costs::add_stmt_cost): Remove use of
	aarch64_use_new_vector_costs_p.
	(aarch64_vector_costs::finish_cost): Remove use of
	aarch64_use_new_vector_costs_p.
	* config/aarch64/tuning_models/cortexx925.h: Remove
	AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS.
	* config/aarch64/tuning_models/fujitsu_monaka.h: Likewise.
	* config/aarch64/tuning_models/generic_armv8_a.h: Likewise.
	* config/aarch64/tuning_models/generic_armv9_a.h: Likewise.
	* config/aarch64/tuning_models/neoverse512tvb.h: Likewise.
	* config/aarch64/tuning_models/neoversen2.h: Likewise.
	* config/aarch64/tuning_models/neoversen3.h: Likewise.
	* config/aarch64/tuning_models/neoversev1.h: Likewise.
	* config/aarch64/tuning_models/neoversev2.h: Likewise.
	* config/aarch64/tuning_models/neoversev3.h: Likewise.
	* config/aarch64/tuning_models/neoversev3ae.h: Likewise.

2025-01-06  Alexandre Oliva  <oliva@adacore.com>

	PR middle-end/118006
	* cfgexpand.cc (expand_gimple_basic_block): Do not emit
	pending stack adjustments after a barrier.

2025-01-06  Akram Ahmad  <Akram.Ahmad@arm.com>

	* config/aarch64/aarch64-simd.md: (*aarch64_trunc_concat)
	new insn definition.

2025-01-06  Fangrui Song  <maskray@gcc.gnu.org>

	PR gcov-profile/96092
	* coverage.cc (coverage_init): Remap getpwd().

2025-01-06  Jennifer Schmitz  <jschmitz@nvidia.com>

	* config/aarch64/aarch64-sve-builtins-base.cc
	(svmul_impl::fold): Wrap code for folding to svneg in lambda
	function and pass to gimple_folder::convert_and_fold to enable
	the transform for unsigned types.
	* config/aarch64/aarch64-sve-builtins.cc
	(gimple_folder::convert_and_fold): New function that converts
	operands to target type before calling callback function, adding the
	necessary conversion statements.
	(gimple_folder::redirect_call): Set fntype of redirected call.
	(get_vector_type): Move from here to aarch64-sve-builtins.h.
	* config/aarch64/aarch64-sve-builtins.h
	(gimple_folder::convert_and_fold): Declare function.
	(get_vector_type): Move here as inline function.

2025-01-06  Martin Jambor  <mjambor@suse.cz>

	* ipa-cp.cc (ipcp_print_widest_int): New function.
	(ipcp_store_vr_results): Use it.
	(ipcp_bits_lattice::print): Likewise.  Fix formatting.

2025-01-06  Mark Wielaard  <mark@klomp.org>

	PR tree-optimization/118032
	* tree-switch-conversion.cc (jump_table_cluster::find_jump_tables):
	Remove param_switch_lower_slow_alg_max_cases check.

2025-01-06  Tamar Christina  <tamar.christina@arm.com>

	PR target/96342
	PR target/118272
	* config/aarch64/aarch64-sve.md (vec_init<mode><Vquad>,
	vec_initvnx16qivnx2qi): New.
	* config/aarch64/aarch64.cc (aarch64_sve_expand_vector_init_subvector):
	Rewrite to support any arbitrary combinations.
	* config/aarch64/iterators.md (SVE_NO2E): Update to use SVE_NO4E
	(SVE_NO2E, Vquad): New.

2025-01-06  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/118224
	* tree-ssa-dce.cc (is_removable_allocation_p): Don't return true
	for allocations with constant size argument larger than PTRDIFF_MAX
	or for calloc with one of the arguments constant larger than
	PTRDIFF_MAX or their product known constant above PTRDIFF_MAX.
	Fix comment typos, furhter -> further and then -> than.
	* lto-section-in.cc (lto_free_function_in_decl_state_for_node):
	Fix comment typo, furhter -> further.

2025-01-04  Hans-Peter Nilsson  <hp@axis.com>

	* config/mmix/mmix.cc (mmix_asm_output_labelref): Replace '.'
	with '::'.
	* config/mmix/mmix.h (ASM_PN_FORMAT): Define to actual default.

2025-01-03  Richard Sandiford  <richard.sandiford@arm.com>

	PR rtl-optimization/117938
	* rtlanal.cc (rtx_properties::try_to_add_dest): Treat writes
	to the stack pointer as also writing to memory.

2025-01-03  Jakub Jelinek  <jakub@redhat.com>

	PR c++/118275
	* varasm.cc (array_size_for_constructor): Use build_int_cst
	with TREE_TYPE (index) as first argument, instead of bitsize_int.

2025-01-03  Jakub Jelinek  <jakub@redhat.com>

	* tree-ssa-forwprop.cc (check_ctz_array): Use tree_fits_shwi_p instead
	of just TREE_CODE tests for INTEGER_CST.

2025-01-03  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* config.gcc: install a wrapping stdint.h in bpf targets.

2025-01-02  Paul-Antoine Arras  <parras@baylibre.com>

	* gimplify.cc (gimplify_call_expr): Fix handling of need_device_ptr for
	type(c_ptr). Fix handling of nested function calls in a dispatch region.
	(find_ifn_gomp_dispatch): Return the IFN without stripping it.
	(gimplify_omp_dispatch): Keep IFN_GOMP_DISPATCH until
	gimplify_call_expr.

2025-01-02  Tobias Burnus  <tburnus@baylibre.com>

	* doc/install.texi (amdgcn-x-amdhsa): Refer to Newlib 4.5.0 for
	the I/O locking fixes.

2025-01-02  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/118171
	* tree-ssa-pre.cc (create_component_ref_by_pieces_1): Do not
	fold any component ref parts.

2025-01-02  Richard Sandiford  <richard.sandiford@arm.com>

	PR target/118184
	* config/aarch64/aarch64-early-ra.cc (allocno_assignment_is_rmw):
	New function.
	(early_ra::record_insn_defs): Mark the live range information as
	untrustworthy if an assignment would change part of an allocno
	but preserve the rest.

2025-01-02  Jakub Jelinek  <jakub@redhat.com>

	* tree-ssa-forwprop.cc (check_ctz_array): Handle also RAW_DATA_CST
	in the CONSTRUCTOR_ELTS.

2025-01-02  Jakub Jelinek  <jakub@redhat.com>

	* doc/libgdiagnostics/conf.py: Use u'' instead of '' in
	project and copyright initialization.

2025-01-02  Jakub Jelinek  <jakub@redhat.com>

	* gcc.cc (process_command): Update copyright notice dates.
	* gcov-dump.cc (print_version): Ditto.
	* gcov.cc (print_version): Ditto.
	* gcov-tool.cc (print_version): Ditto.
	* gengtype.cc (create_file): Ditto.
	* doc/cpp.texi: Bump @copying's copyright year.
	* doc/cppinternals.texi: Ditto.
	* doc/gcc.texi: Ditto.
	* doc/gccint.texi: Ditto.
	* doc/gcov.texi: Ditto.
	* doc/install.texi: Ditto.
	* doc/invoke.texi: Ditto.

2025-01-02  Guo Jie  <guojie@loongson.cn>

	* config/loongarch/loongarch.cc
	(loongarch_expand_conditional_move): Add some optimization
	implementations based on noce_try_cmove_arith.

2025-01-02  Guo Jie  <guojie@loongson.cn>

	* config/loongarch/lasx.md (lasx_xvabsd_s_<lasxfmt>): Remove.
	(<su>abd<mode>3): New insn pattern.
	(lasx_xvabsd_u_<lasxfmt_u>): Remove.
	* config/loongarch/loongarch-builtins.cc (CODE_FOR_lsx_vabsd_b):
	Rename.
	(CODE_FOR_lsx_vabsd_h): Ditto.
	(CODE_FOR_lsx_vabsd_w): Ditto.
	(CODE_FOR_lsx_vabsd_d): Ditto.
	(CODE_FOR_lsx_vabsd_bu): Ditto.
	(CODE_FOR_lsx_vabsd_hu): Ditto.
	(CODE_FOR_lsx_vabsd_wu): Ditto.
	(CODE_FOR_lsx_vabsd_du): Ditto.
	(CODE_FOR_lasx_xvabsd_b): Ditto.
	(CODE_FOR_lasx_xvabsd_h): Ditto.
	(CODE_FOR_lasx_xvabsd_w): Ditto.
	(CODE_FOR_lasx_xvabsd_d): Ditto.
	(CODE_FOR_lasx_xvabsd_bu): Ditto.
	(CODE_FOR_lasx_xvabsd_hu): Ditto.
	(CODE_FOR_lasx_xvabsd_wu): Ditto.
	(CODE_FOR_lasx_xvabsd_du): Ditto.
	* config/loongarch/loongarch.md (u): Add smax/umax.
	* config/loongarch/lsx.md (SU_MAX): New iterator.
	(su_min): New attr.
	(lsx_vabsd_s_<lsxfmt>): Remove.
	(<su>abd<mode>3): New insn pattern.
	(lsx_vabsd_u_<lsxfmt_u>): Remove.

2025-01-02  Guo Jie  <guojie@loongson.cn>

	* config/loongarch/lasx.md (vec_unpacks_lo_<mode>): Redefine.
	(vec_unpacku_lo_<mode>): Ditto.
	(lasx_vext2xv_h<u>_b<u>): Replaced by vec_unpack<su>_lo_v32qi.
	(vec_unpack<su>_lo_v32qi): New insn.
	(lasx_vext2xv_w<u>_h<u>): Replaced by vec_unpack<su>_lo_v16hi.
	(vec_unpack<su>_lo_v16qi_internal): New insn, for 128 bits.
	(vec_unpack<su>_lo_v16hi): New insn.
	(lasx_vext2xv_d<u>_w<u>): Replaced by vec_unpack<su>_lo_v8si.
	(vec_unpack<su>_lo_v8hi_internal): New insn, for 128 bits.
	(vec_unpack<su>_lo_v8si): New insn.
	(vec_unpack<su>_lo_v4si_internal): New insn, for 128 bits.
	(vec_packs_float_v4di): New expander.
	(vec_pack_sfix_trunc_v4df): Ditto.
	(vec_unpacks_float_hi_v8si): Ditto.
	(vec_unpacks_float_lo_v8si): Ditto.
	(vec_unpack_sfix_trunc_hi_v8sf): Ditto.
	(vec_unpack_sfix_trunc_lo_v8sf): Ditto.
	* config/loongarch/loongarch-builtins.cc
	(CODE_FOR_lsx_vftintrz_w_d): Rename.
	(CODE_FOR_lsx_vftintrzh_l_s): Ditto.
	(CODE_FOR_lsx_vftintrzl_l_s): Ditto.
	(CODE_FOR_lsx_vffint_s_l): Ditto.
	(CODE_FOR_lsx_vffinth_d_w): Ditto.
	(CODE_FOR_lsx_vffintl_d_w): Ditto.
	(CODE_FOR_lsx_vexth_h_b): Ditto.
	(CODE_FOR_lsx_vexth_w_h): Ditto.
	(CODE_FOR_lsx_vexth_d_w): Ditto.
	(CODE_FOR_lsx_vexth_hu_bu): Ditto.
	(CODE_FOR_lsx_vexth_wu_hu): Ditto.
	(CODE_FOR_lsx_vexth_du_wu): Ditto.
	(CODE_FOR_lsx_vfcvth_d_s): Ditto.
	(CODE_FOR_lsx_vfcvtl_d_s): Ditto.
	(CODE_FOR_lasx_vext2xv_h_b): Ditto.
	(CODE_FOR_lasx_vext2xv_w_h): Ditto.
	(CODE_FOR_lasx_vext2xv_d_w): Ditto.
	(CODE_FOR_lasx_vext2xv_hu_bu): Ditto.
	(CODE_FOR_lasx_vext2xv_wu_hu): Ditto.
	(CODE_FOR_lasx_vext2xv_du_wu): Ditto.
	(loongarch_expand_builtin_insn): Swap source operands in
	CODE_FOR_lsx_vftintrz_w_d and CODE_FOR_lsx_vffint_s_l.
	* config/loongarch/loongarch-protos.h
	(loongarch_expand_vec_unpack): Remove useless parameter high_p.
	* config/loongarch/loongarch.cc (loongarch_expand_vec_unpack):
	Rewrite.
	* config/loongarch/lsx.md (vec_unpacks_hi_v4sf): Redefine.
	(vec_unpacks_lo_v4sf): Ditto.
	(vec_unpacks_hi_<mode>): Ditto.
	(vec_unpacku_hi_<mode>): Ditto.
	(lsx_vfcvth_d_s): Replaced by vec_unpacks_hi_v4sf.
	(lsx_vfcvtl_d_s): Replaced by vec_unpacks_lo_v4sf.
	(lsx_vffint_s_l): Replaced by vec_packs_float_v2di.
	(vec_packs_float_v2di): New insn.
	(lsx_vftintrz_w_d): Replaced by vec_pack_sfix_trunc_v2df.
	(vec_pack_sfix_trunc_v2df): New insn.
	(lsx_vffinth_d_w): Replaced by vec_unpacks_float_hi_v4si.
	(vec_unpacks_float_hi_v4si): New insn.
	(lsx_vffintl_d_w): Replaced by vec_unpacks_float_lo_v4si.
	(vec_unpacks_float_lo_v4si): New insn.
	(lsx_vftintrzh_l_s): Replaced by vec_unpack_sfix_trunc_hi_v4sf.
	(vec_unpack_sfix_trunc_hi_v4sf): New insn.
	(lsx_vftintrzl_l_s): Replaced by vec_unpack_sfix_trunc_lo_v4sf.
	(vec_unpack_sfix_trunc_lo_v4sf): New insn.
	(lsx_vexth_h<u>_b<u>): Replaced by vec_unpack<su>_hi_v16qi.
	(vec_unpack<su>_hi_v16qi): New insn.
	(lsx_vexth_w<u>_h<u>): Replaced by vec_unpack<su>_hi_v8hi.
	(vec_unpack<su>_hi_v8hi): New insn.
	(lsx_vexth_d<u>_w<u>): Replaced by vec_unpack<su>_hi_v4si.
	(vec_unpack<su>_hi_v4si): New insn.

2025-01-02  Guo Jie  <guojie@loongson.cn>

	* config/loongarch/loongarch.md
	(bytepick_d_<bytepick_imm>_rev): New combiner.
	(bstrpick_alsl_paired): Reorder input operands.

2025-01-02  Guo Jie  <guojie@loongson.cn>

	* config/loongarch/lasx.md: Remove useless vec_select.
	* config/loongarch/predicates.md: Correct error predicate.

2025-01-02  Guo Jie  <guojie@loongson.cn>

	* config/loongarch/lasx.md: Fix selector index.

2025-01-02  Guo Jie  <guojie@loongson.cn>

	* config/loongarch/lasx.md: Remove useless code.
	* config/loongarch/lsx.md: Ditto.

2025-01-01  Sam James  <sam@gentoo.org>

	* doc/cpp.texi (Common Predefined Macros): Fix syntax.

2025-01-01  Richard Biener  <rguenther@suse.de>

	PR middle-end/118174
	* tree-outof-ssa.cc (ssa_is_replaceable_p): Exclude tailcalls.

2025-01-01  Sandra Loosemore  <sloosemore@baylibre.com>

	* doc/invoke.texi (Option Summary): Put "M32C Options" and
	"Cygwin and MinGW Options" in alphabetical order.  Add
	cross-references.
	(Cygwin and MinGW Options): Likewise move the section to its
	correct alphabetical location.
	* config/lynx.opt.urls: Regenerated.
	* config/mingw/cygming.opt.urls: Regenerated.

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