//=============================================================================
//
//      mod_regs_rtc.h
//
//      RTC (real time clock) Module register definitions
//
//=============================================================================
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// -------------------------------------------                              
// This file is part of eCos, the Embedded Configurable Operating System.   
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// for more details.                                                        
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//
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//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):   jskov
// Contributors:jskov, Hajime Ishitani 
// Date:        2000-10-30
//              
//####DESCRIPTIONEND####
//
//=============================================================================

//--------------------------------------------------------------------------
// RealTime Clock

#define CYGARC_REG_RC64CNT              0xFFC80000		// 8bit
#define CYGARC_REG_RSECCNT              0xFFC80004		// 8bit
#define CYGARC_REG_RMINCNT              0xFFC80008		// 8bit
#define CYGARC_REG_RHRCNT               0xFFC8000C		// 8bit
#define CYGARC_REG_RWKCNT               0xFFC80010		// 8bit
#define CYGARC_REG_RDAYCNT              0xFFC80014		// 8bit
#define CYGARC_REG_RMONCNT              0xFFC80018		// 8bit
#define CYGARC_REG_RYRCNT               0xFFC8001C		// 16bit
#define CYGARC_REG_RSECAR               0xFFC80020		// 8bit
#define CYGARC_REG_RMINAR               0xFFC80024		// 8bit
#define CYGARC_REG_RHRAR                0xFFC80028		// 8bit
#define CYGARC_REG_RWKAR                0xFFC8002C		// 8bit
#define CYGARC_REG_RDAYAR               0xFFC80030		// 8bit
#define CYGARC_REG_RMONAR               0xFFC80034		// 8bit
#define CYGARC_REG_RCR1                 0xFFC80038		// 8bit
#define CYGARC_REG_RCR2                 0xFFC8003C		// 8bit
#define CYGARC_REG_RCR3                 0xFFC80050		// 8bit
#define CYGARC_REG_RYRAR                0xFFC80054		// 8bit

#define CYGARC_REG_RCR1_CF              0x80 // carry flag
#define CYGARC_REG_RCR1_CIE             0x10 // carry interrupt enable
#define CYGARC_REG_RCR1_AIE             0x08 // alarm interrupt enable
#define CYGARC_REG_RCR1_AF              0x01 // alarm flag

#define CYGARC_REG_RCR2_PEF             0x80 // periodic interrupt flag
#define CYGARC_REG_RCR2_PES2            0x40 // periodic interrupt setting
#define CYGARC_REG_RCR2_PES1            0x20
#define CYGARC_REG_RCR2_PES0            0x10
#define CYGARC_REG_RCR2_RTCEN           0x08 // RTC enable
#define CYGARC_REG_RCR2_ADJ             0x04 // second adjustment
#define CYGARC_REG_RCR2_RESET           0x02 // reset
#define CYGARC_REG_RCR2_START           0x01 // start

