#ifndef CYGONCE_VAR_INTR_H
#define CYGONCE_VAR_INTR_H
//=============================================================================
//
//      var_intr.h
//
//      Variant HAL interrupt and clock support
//
//=============================================================================
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//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):   nickg
// Contributors:nickg, jskov, jlarmour, hmt, gthomas
// Date:        2000-04-02
// Purpose:     Variant interrupt support
// Description: The macros defined here provide the HAL APIs for handling
//              interrupts and the clock on the PPC60x variant CPUs.
// Usage:       Is included via the architecture interrupt header:
//              #include <cyg/hal/hal_intr.h>
//              ...
//
//####DESCRIPTIONEND####
//
//=============================================================================

// Additional trap/exceptions on PPC60x
#define CYGNUM_HAL_VECTOR_ITLB_MISS        0x10
#define CYGNUM_HAL_VECTOR_DTLB_LOAD_MISS   0x11
#define CYGNUM_HAL_VECTOR_DTLB_STORE_MISS  0x12
#define CYGNUM_HAL_VECTOR_SMI              0x13

#define CYGNUM_HAL_VSR_MAX                 CYGNUM_HAL_VECTOR_SMI

// No builtin interrupt controller in the PPC60x CPUs.

#include <cyg/hal/plf_intr.h>  // Maybe something on the platform though

//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_VAR_INTR_H
// End of var_intr.h
