// Copyright (c) 1994 - 2025 Advanced Micro Devices, Inc. All rights reserved.

#ifndef _vpe22_MASK_HEADER
#define _vpe22_MASK_HEADER
/*
 *    chip_mask.h      
 *
 *    Register Spec Release:  <unknown>
 *
 *
 *      (c) 2021 Advanced Micro Devices, Inc.  (unpublished)
 *
 *        All rights reserved.  This notice is intended as a precaution against
 *     inadvertent publication and does not imply publication or any waiver
 *      of confidentiality.  The year included in the foregoing notice is the
 *     year of creation of the work.
 *
 */

// VPEP_MGCG_CNTL
#define VPEP_MGCG_CNTL__VPDPP0_CLK_GATE_DIS_MASK           0x00000007UL
#define VPEP_MGCG_CNTL__VPMPC_CLK_GATE_DIS_MASK            0x00003000UL
#define VPEP_MGCG_CNTL__VPOPP_CLK_GATE_DIS_MASK            0x000c0000UL
#define VPEP_MGCG_CNTL__VPCDC_SOCCLK_G_GATE_DIS_MASK       0x00100000UL
#define VPEP_MGCG_CNTL__VPCDC_SOCCLK_R_GATE_DIS_MASK       0x00200000UL
#define VPEP_MGCG_CNTL__VPCDC_VPECLK_G_GATE_DIS_MASK       0x00400000UL
#define VPEP_MGCG_CNTL__VPCDC_VPECLK_R_GATE_DIS_MASK       0x00800000UL

// VPCDC_SOFT_RESET
#define VPCDC_SOFT_RESET__VPCDC_SOCCLK_SOFT_RESET_MASK     0x00000001UL
#define VPCDC_SOFT_RESET__VPCDC_VPECLK_SOFT_RESET_MASK     0x00000002UL

// VPCDC_FE0_SURFACE_CONFIG
#define VPCDC_FE0_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_FE0_MASK 0x000001ffUL
#define VPCDC_FE0_SURFACE_CONFIG__ROTATION_ANGLE_FE0_MASK  0x00000600UL
#define VPCDC_FE0_SURFACE_CONFIG__H_MIRROR_EN_FE0_MASK     0x00001000UL
#define VPCDC_FE0_SURFACE_CONFIG__PIX_SURFACE_LINEAR_FE0_MASK 0x00002000UL

// VPCDC_FE0_CROSSBAR_CONFIG
#define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_ALPHA_FE0_MASK 0x00000003UL
#define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_Y_G_FE0_MASK 0x0000000cUL
#define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_CB_B_FE0_MASK 0x00000030UL
#define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_CR_R_FE0_MASK 0x000000c0UL

// VPCDC_FE0_VIEWPORT_START_CONFIG
#define VPCDC_FE0_VIEWPORT_START_CONFIG__VIEWPORT_X_START_FE0_MASK 0x00003fffUL
#define VPCDC_FE0_VIEWPORT_START_CONFIG__VIEWPORT_Y_START_FE0_MASK 0x3fff0000UL

// VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG
#define VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG__VIEWPORT_WIDTH_FE0_MASK 0x00003fffUL
#define VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG__VIEWPORT_HEIGHT_FE0_MASK 0x3fff0000UL

// VPCDC_FE0_VIEWPORT_START_C_CONFIG
#define VPCDC_FE0_VIEWPORT_START_C_CONFIG__VIEWPORT_X_START_C_FE0_MASK 0x00003fffUL
#define VPCDC_FE0_VIEWPORT_START_C_CONFIG__VIEWPORT_Y_START_C_FE0_MASK 0x3fff0000UL

// VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG
#define VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG__VIEWPORT_WIDTH_C_FE0_MASK 0x00003fffUL
#define VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG__VIEWPORT_HEIGHT_C_FE0_MASK 0x3fff0000UL

// VPCDC_BE0_P2B_CONFIG
#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL0_MASK 0x00000003UL
#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL1_MASK 0x0000000cUL
#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL2_MASK 0x00000030UL
#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL3_MASK 0x000000c0UL
#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_FORMAT_SEL_MASK 0x0001ff00UL
#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_TILED_MASK     0x00020000UL
#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_X_START_PLANE0_MASK 0x007c0000UL
#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_X_START_PLANE1_MASK 0x0f800000UL

// VPCDC_BE0_GLOBAL_SYNC_CONFIG
#define VPCDC_BE0_GLOBAL_SYNC_CONFIG__BE0_VUPDATE_OFFSET_MASK 0x000003ffUL
#define VPCDC_BE0_GLOBAL_SYNC_CONFIG__BE0_VUPDATE_WIDTH_MASK 0x000ffc00UL
#define VPCDC_BE0_GLOBAL_SYNC_CONFIG__BE0_VREADY_OFFSET_MASK 0x3ff00000UL

// VPCDC_GLOBAL_SYNC_TRIGGER
#define VPCDC_GLOBAL_SYNC_TRIGGER__VPBE_GS_TRIG_MASK       0x00000003UL

// VPCDC_VREADY_STATUS
#define VPCDC_VREADY_STATUS__VPFE_VR_STATUS_MASK           0x00000003UL

// VPEP_MEM_GLOBAL_PWR_REQ_CNTL
#define VPEP_MEM_GLOBAL_PWR_REQ_CNTL__MEM_GLOBAL_PWR_REQ_DIS_MASK 0x00000001UL

// VPFE0_MEM_PWR_CNTL
#define VPFE0_MEM_PWR_CNTL__VPFE0_MEM_PWR_FORCE_MASK       0x00000003UL
#define VPFE0_MEM_PWR_CNTL__VPFE0_MEM_PWR_MODE_MASK        0x0000000cUL
#define VPFE0_MEM_PWR_CNTL__VPFE0_MEM_PWR_STATE_MASK       0x00000030UL
#define VPFE0_MEM_PWR_CNTL__VPFE0_MEM_PWR_DIS_MASK         0x00000040UL

// VPBE0_MEM_PWR_CNTL
#define VPBE0_MEM_PWR_CNTL__VPBE0_MEM_PWR_FORCE_MASK       0x00000003UL
#define VPBE0_MEM_PWR_CNTL__VPBE0_MEM_PWR_MODE_MASK        0x0000000cUL
#define VPBE0_MEM_PWR_CNTL__VPBE0_MEM_PWR_STATE_MASK       0x00000030UL
#define VPBE0_MEM_PWR_CNTL__VPBE0_MEM_PWR_DIS_MASK         0x00000040UL

// VPCDC_3DLUT_FL_CONFIG
#define VPCDC_3DLUT_FL_CONFIG__VPCDC_3DLUT_FL_MODE_MASK    0x00000003UL
#define VPCDC_3DLUT_FL_CONFIG__VPCDC_3DLUT_FL_CROSSBAR_SRC_G_MASK 0x0000000cUL
#define VPCDC_3DLUT_FL_CONFIG__VPCDC_3DLUT_FL_CROSSBAR_SRC_B_MASK 0x00000030UL
#define VPCDC_3DLUT_FL_CONFIG__VPCDC_3DLUT_FL_CROSSBAR_SRC_R_MASK 0x000000c0UL
#define VPCDC_3DLUT_FL_CONFIG__VPCDC_3DLUT_FL_SIZE_MASK    0x00000100UL

// VPCDC_CONTROL
#define VPCDC_CONTROL__VPCDC_HISTOGRAM0_EN_MASK            0x00000003UL
#define VPCDC_CONTROL__VPCDC_HISTOGRAM1_EN_MASK            0x0000000cUL
#define VPCDC_CONTROL__VPCDC_FROD_EN_MASK                  0x00000100UL

// VPCNVC_SURFACE_PIXEL_FORMAT
#define VPCNVC_SURFACE_PIXEL_FORMAT__VPCNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007fUL

// VPCNVC_FORMAT_CONTROL
#define VPCNVC_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK  0x00000001UL
#define VPCNVC_FORMAT_CONTROL__FORMAT_CNV16_MASK           0x00000010UL
#define VPCNVC_FORMAT_CONTROL__ALPHA_EN_MASK               0x00000100UL
#define VPCNVC_FORMAT_CONTROL__VPCNVC_BYPASS_MASK          0x00001000UL
#define VPCNVC_FORMAT_CONTROL__VPCNVC_BYPASS_MSB_ALIGN_MASK 0x00002000UL
#define VPCNVC_FORMAT_CONTROL__CLAMP_POSITIVE_MASK         0x00010000UL
#define VPCNVC_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK       0x00020000UL
#define VPCNVC_FORMAT_CONTROL__VPCNVC_UPDATE_PENDING_MASK  0x00100000UL

// VPCNVC_FCNV_FP_BIAS_R
#define VPCNVC_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK         0x0007ffffUL

// VPCNVC_FCNV_FP_BIAS_G
#define VPCNVC_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK         0x0007ffffUL

// VPCNVC_FCNV_FP_BIAS_B
#define VPCNVC_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK         0x0007ffffUL

// VPCNVC_FCNV_FP_SCALE_R
#define VPCNVC_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK       0x0007ffffUL

// VPCNVC_FCNV_FP_SCALE_G
#define VPCNVC_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK       0x0007ffffUL

// VPCNVC_FCNV_FP_SCALE_B
#define VPCNVC_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK       0x0007ffffUL

// VPCNVC_COLOR_KEYER_CONTROL
#define VPCNVC_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK    0x00000001UL
#define VPCNVC_COLOR_KEYER_CONTROL__LUMA_KEYER_EN_MASK     0x00000002UL
#define VPCNVC_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK  0x00000030UL

// VPCNVC_COLOR_KEYER_ALPHA
#define VPCNVC_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000ffffUL
#define VPCNVC_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xffff0000UL

// VPCNVC_COLOR_KEYER_RED
#define VPCNVC_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK   0x0000ffffUL
#define VPCNVC_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK  0xffff0000UL

// VPCNVC_COLOR_KEYER_GREEN
#define VPCNVC_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000ffffUL
#define VPCNVC_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xffff0000UL

// VPCNVC_COLOR_KEYER_BLUE
#define VPCNVC_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000ffffUL
#define VPCNVC_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xffff0000UL

// VPCNVC_ALPHA_2BIT_LUT01
#define VPCNVC_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT0_MASK      0x00000fffUL
#define VPCNVC_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT1_MASK      0x0fff0000UL

// VPCNVC_ALPHA_2BIT_LUT23
#define VPCNVC_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT2_MASK      0x00000fffUL
#define VPCNVC_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT3_MASK      0x0fff0000UL

// VPCNVC_PRE_DEALPHA
#define VPCNVC_PRE_DEALPHA__PRE_DEALPHA_EN_MASK            0x00000001UL
#define VPCNVC_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK      0x00000010UL

// VPCNVC_PRE_CSC_MODE
#define VPCNVC_PRE_CSC_MODE__PRE_CSC_MODE_MASK             0x00000001UL
#define VPCNVC_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK     0x00000004UL

// VPCNVC_PRE_CSC_C11_C12
#define VPCNVC_PRE_CSC_C11_C12__PRE_CSC_C11_MASK           0x0000ffffUL
#define VPCNVC_PRE_CSC_C11_C12__PRE_CSC_C12_MASK           0xffff0000UL

// VPCNVC_PRE_CSC_C13_C14
#define VPCNVC_PRE_CSC_C13_C14__PRE_CSC_C13_MASK           0x0000ffffUL
#define VPCNVC_PRE_CSC_C13_C14__PRE_CSC_C14_MASK           0xffff0000UL

// VPCNVC_PRE_CSC_C21_C22
#define VPCNVC_PRE_CSC_C21_C22__PRE_CSC_C21_MASK           0x0000ffffUL
#define VPCNVC_PRE_CSC_C21_C22__PRE_CSC_C22_MASK           0xffff0000UL

// VPCNVC_PRE_CSC_C23_C24
#define VPCNVC_PRE_CSC_C23_C24__PRE_CSC_C23_MASK           0x0000ffffUL
#define VPCNVC_PRE_CSC_C23_C24__PRE_CSC_C24_MASK           0xffff0000UL

// VPCNVC_PRE_CSC_C31_C32
#define VPCNVC_PRE_CSC_C31_C32__PRE_CSC_C31_MASK           0x0000ffffUL
#define VPCNVC_PRE_CSC_C31_C32__PRE_CSC_C32_MASK           0xffff0000UL

// VPCNVC_PRE_CSC_C33_C34
#define VPCNVC_PRE_CSC_C33_C34__PRE_CSC_C33_MASK           0x0000ffffUL
#define VPCNVC_PRE_CSC_C33_C34__PRE_CSC_C34_MASK           0xffff0000UL

// VPCNVC_COEF_FORMAT
#define VPCNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK       0x00000001UL

// VPCNVC_PRE_DEGAM
#define VPCNVC_PRE_DEGAM__PRE_DEGAM_MODE_MASK              0x00000003UL
#define VPCNVC_PRE_DEGAM__PRE_DEGAM_SELECT_MASK            0x00000070UL

// VPCNVC_PRE_REALPHA
#define VPCNVC_PRE_REALPHA__PRE_REALPHA_EN_MASK            0x00000001UL
#define VPCNVC_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK      0x00000010UL

// VPDSCL_COEF_RAM_TAP_SELECT
#define VPDSCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003UL
#define VPDSCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003f00UL
#define VPDSCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000UL

// VPDSCL_COEF_RAM_TAP_DATA
#define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003fffUL
#define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000UL
#define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3fff0000UL
#define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000UL

// VPDSCL_MODE
#define VPDSCL_MODE__VPDSCL_MODE_MASK                      0x00000007UL
#define VPDSCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK      0x00001000UL
#define VPDSCL_MODE__SCL_CHROMA_COEF_MODE_MASK             0x00010000UL
#define VPDSCL_MODE__SCL_ALPHA_COEF_MODE_MASK              0x00100000UL
#define VPDSCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK           0x01000000UL

// VPDSCL_TAP_CONTROL
#define VPDSCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK            0x00000007UL
#define VPDSCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK            0x00000070UL
#define VPDSCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK          0x00000700UL
#define VPDSCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK          0x00007000UL

// VPDSCL_CONTROL
#define VPDSCL_CONTROL__SCL_BOUNDARY_MODE_MASK             0x00000001UL

// VPDSCL_2TAP_CONTROL
#define VPDSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001UL
#define VPDSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK      0x00000010UL
#define VPDSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK  0x00000700UL
#define VPDSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000UL
#define VPDSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK      0x00100000UL
#define VPDSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK  0x07000000UL

// VPDSCL_MANUAL_REPLICATE_CONTROL
#define VPDSCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000fUL
#define VPDSCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000f00UL

// VPDSCL_HORZ_FILTER_SCALE_RATIO
#define VPDSCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x07ffffffUL

// VPDSCL_HORZ_FILTER_INIT
#define VPDSCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK      0x00ffffffUL
#define VPDSCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK       0x0f000000UL

// VPDSCL_HORZ_FILTER_SCALE_RATIO_C
#define VPDSCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x07ffffffUL

// VPDSCL_HORZ_FILTER_INIT_C
#define VPDSCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK  0x00ffffffUL
#define VPDSCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK   0x0f000000UL

// VPDSCL_VERT_FILTER_SCALE_RATIO
#define VPDSCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x07ffffffUL

// VPDSCL_VERT_FILTER_INIT
#define VPDSCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK      0x00ffffffUL
#define VPDSCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK       0x0f000000UL

// VPDSCL_VERT_FILTER_INIT_BOT
#define VPDSCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00ffffffUL
#define VPDSCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0f000000UL

// VPDSCL_VERT_FILTER_SCALE_RATIO_C
#define VPDSCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x07ffffffUL

// VPDSCL_VERT_FILTER_INIT_C
#define VPDSCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK  0x00ffffffUL
#define VPDSCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK   0x0f000000UL

// VPDSCL_VERT_FILTER_INIT_BOT_C
#define VPDSCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00ffffffUL
#define VPDSCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0f000000UL

// VPDSCL_BLACK_COLOR
#define VPDSCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK     0x0000ffffUL
#define VPDSCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK      0xffff0000UL

// VPDSCL_UPDATE
#define VPDSCL_UPDATE__SCL_UPDATE_PENDING_MASK             0x00000001UL

// VPDSCL_AUTOCAL
#define VPDSCL_AUTOCAL__AUTOCAL_MODE_MASK                  0x00000003UL

// VPDSCL_EXT_OVERSCAN_LEFT_RIGHT
#define VPDSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001fffUL
#define VPDSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1fff0000UL

// VPDSCL_EXT_OVERSCAN_TOP_BOTTOM
#define VPDSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001fffUL
#define VPDSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1fff0000UL

// VPOTG_H_BLANK
#define VPOTG_H_BLANK__OTG_H_BLANK_START_MASK              0x00003fffUL
#define VPOTG_H_BLANK__OTG_H_BLANK_END_MASK                0x3fff0000UL

// VPOTG_V_BLANK
#define VPOTG_V_BLANK__OTG_V_BLANK_START_MASK              0x00003fffUL
#define VPOTG_V_BLANK__OTG_V_BLANK_END_MASK                0x3fff0000UL

// VPDSCL_RECOUT_START
#define VPDSCL_RECOUT_START__RECOUT_START_X_MASK           0x00001fffUL
#define VPDSCL_RECOUT_START__RECOUT_START_Y_MASK           0x1fff0000UL

// VPDSCL_RECOUT_SIZE
#define VPDSCL_RECOUT_SIZE__RECOUT_WIDTH_MASK              0x00003fffUL
#define VPDSCL_RECOUT_SIZE__RECOUT_HEIGHT_MASK             0x3fff0000UL

// VPMPC_SIZE
#define VPMPC_SIZE__VPMPC_WIDTH_MASK                       0x00003fffUL
#define VPMPC_SIZE__VPMPC_HEIGHT_MASK                      0x3fff0000UL

// VPLB_DATA_FORMAT
#define VPLB_DATA_FORMAT__ALPHA_EN_MASK                    0x00000010UL

// VPLB_MEMORY_CTRL
#define VPLB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK           0x00003f00UL
#define VPLB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK           0x007f0000UL
#define VPLB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK         0x7f000000UL

// VPLB_V_COUNTER
#define VPLB_V_COUNTER__V_COUNTER_MASK                     0x00001fffUL
#define VPLB_V_COUNTER__V_COUNTER_C_MASK                   0x1fff0000UL

// VPDSCL_MEM_PWR_CTRL
#define VPDSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK        0x00000003UL
#define VPDSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK          0x00000004UL
#define VPDSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK      0x00000030UL
#define VPDSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK        0x00000040UL
#define VPDSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK      0x00000300UL
#define VPDSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK        0x00000400UL
#define VPDSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK          0x10000000UL

// VPDSCL_MEM_PWR_STATUS
#define VPDSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK      0x00000003UL
#define VPDSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK    0x0000000cUL
#define VPDSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK    0x00000030UL

// VPDSCL_EASF_H_MODE
#define VPDSCL_EASF_H_MODE__SCL_EASF_H_EN_MASK             0x00000001UL
#define VPDSCL_EASF_H_MODE__SCL_EASF_H_RINGEST_FORCE_EN_MASK 0x00000010UL
#define VPDSCL_EASF_H_MODE__SCL_EASF_H_2TAP_SHARP_FACTOR_MASK 0x00003f00UL

// VPDSCL_EASF_V_MODE
#define VPDSCL_EASF_V_MODE__SCL_EASF_V_EN_MASK             0x00000001UL
#define VPDSCL_EASF_V_MODE__SCL_EASF_V_RINGEST_FORCE_EN_MASK 0x00000010UL
#define VPDSCL_EASF_V_MODE__SCL_EASF_V_2TAP_SHARP_FACTOR_MASK 0x00003f00UL

// VPDSCL_SC_MODE
#define VPDSCL_SC_MODE__SCL_SC_MATRIX_MODE_MASK            0x00000001UL
#define VPDSCL_SC_MODE__SCL_SC_LTONL_EN_MASK               0x00000100UL

// VPDSCL_SC_MATRIX_C0C1
#define VPDSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C0_MASK       0x0000ffffUL
#define VPDSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C1_MASK       0xffff0000UL

// VPDSCL_SC_MATRIX_C2C3
#define VPDSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C2_MASK       0x0000ffffUL
#define VPDSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C3_MASK       0xffff0000UL

// VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN
#define VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN1_MASK 0x0000ffffUL
#define VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN2_MASK 0xffff0000UL

// VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE
#define VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1_MASK 0x0000ffffUL
#define VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2_MASK 0xffff0000UL

// VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN
#define VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN1_MASK 0x0000ffffUL
#define VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN2_MASK 0xffff0000UL

// VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE
#define VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1_MASK 0x0000ffffUL
#define VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2_MASK 0xffff0000UL

// VPDSCL_EASF_V_RINGEST_3TAP_CNTL1
#define VPDSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT_MASK 0x0000ffffUL
#define VPDSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL_MASK 0xffff0000UL

// VPDSCL_EASF_V_RINGEST_3TAP_CNTL2
#define VPDSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE_MASK 0x0000ffffUL
#define VPDSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE_MASK 0xffff0000UL

// VPDSCL_EASF_V_RINGEST_3TAP_CNTL3
#define VPDSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE_MASK 0x0000ffffUL
#define VPDSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET_MASK 0xffff0000UL

// VPDSCL_EASF_RINGEST_FORCE
#define VPDSCL_EASF_RINGEST_FORCE__SCL_EASF_H_RINGEST_FORCE_MASK 0x0000ffffUL
#define VPDSCL_EASF_RINGEST_FORCE__SCL_EASF_V_RINGEST_FORCE_MASK 0xffff0000UL

// VPDSCL_EASF_H_BF_CNTL
#define VPDSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF1_EN_MASK      0x00000001UL
#define VPDSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_MODE_MASK    0x00000f00UL
#define VPDSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF3_MODE_MASK    0x00030000UL
#define VPDSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT1_GAIN_MASK 0x00f00000UL
#define VPDSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT2_GAIN_MASK 0x0f000000UL
#define VPDSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_ROC_GAIN_MASK 0xf0000000UL

// VPDSCL_EASF_H_BF_FINAL_MAX_MIN
#define VPDSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXA_MASK 0x0000003fUL
#define VPDSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXB_MASK 0x00003f00UL
#define VPDSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINA_MASK 0x003f0000UL
#define VPDSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINB_MASK 0x3f000000UL

// VPDSCL_EASF_V_BF_CNTL
#define VPDSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF1_EN_MASK      0x00000001UL
#define VPDSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_MODE_MASK    0x00000f00UL
#define VPDSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF3_MODE_MASK    0x00030000UL
#define VPDSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT1_GAIN_MASK 0x00f00000UL
#define VPDSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT2_GAIN_MASK 0x0f000000UL
#define VPDSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_ROC_GAIN_MASK 0xf0000000UL

// VPDSCL_EASF_H_BF1_PWL_SEG0
#define VPDSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_IN_SEG0_MASK 0x000007ffUL
#define VPDSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_BASE_SEG0_MASK 0x0003f000UL
#define VPDSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_SLOPE_SEG0_MASK 0x7ff00000UL

// VPDSCL_EASF_H_BF1_PWL_SEG1
#define VPDSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_IN_SEG1_MASK 0x000007ffUL
#define VPDSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_BASE_SEG1_MASK 0x0003f000UL
#define VPDSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_SLOPE_SEG1_MASK 0x7ff00000UL

// VPDSCL_EASF_H_BF1_PWL_SEG2
#define VPDSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_IN_SEG2_MASK 0x000007ffUL
#define VPDSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_BASE_SEG2_MASK 0x0003f000UL
#define VPDSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_SLOPE_SEG2_MASK 0x7ff00000UL

// VPDSCL_EASF_H_BF1_PWL_SEG3
#define VPDSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_IN_SEG3_MASK 0x000007ffUL
#define VPDSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_BASE_SEG3_MASK 0x0003f000UL
#define VPDSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_SLOPE_SEG3_MASK 0x7ff00000UL

// VPDSCL_EASF_H_BF1_PWL_SEG4
#define VPDSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_IN_SEG4_MASK 0x000007ffUL
#define VPDSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_BASE_SEG4_MASK 0x0003f000UL
#define VPDSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_SLOPE_SEG4_MASK 0x7ff00000UL

// VPDSCL_EASF_H_BF1_PWL_SEG5
#define VPDSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_IN_SEG5_MASK 0x000007ffUL
#define VPDSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_BASE_SEG5_MASK 0x0003f000UL
#define VPDSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_SLOPE_SEG5_MASK 0x7ff00000UL

// VPDSCL_EASF_H_BF1_PWL_SEG6
#define VPDSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_IN_SEG6_MASK 0x000007ffUL
#define VPDSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_BASE_SEG6_MASK 0x0003f000UL
#define VPDSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_SLOPE_SEG6_MASK 0x7ff00000UL

// VPDSCL_EASF_H_BF1_PWL_SEG7
#define VPDSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_IN_SEG7_MASK 0x000007ffUL
#define VPDSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_BASE_SEG7_MASK 0x0003f000UL

// VPDSCL_EASF_V_BF1_PWL_SEG0
#define VPDSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_IN_SEG0_MASK 0x000007ffUL
#define VPDSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_BASE_SEG0_MASK 0x0003f000UL
#define VPDSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_SLOPE_SEG0_MASK 0x7ff00000UL

// VPDSCL_EASF_V_BF1_PWL_SEG1
#define VPDSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_IN_SEG1_MASK 0x000007ffUL
#define VPDSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_BASE_SEG1_MASK 0x0003f000UL
#define VPDSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_SLOPE_SEG1_MASK 0x7ff00000UL

// VPDSCL_EASF_V_BF1_PWL_SEG2
#define VPDSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_IN_SEG2_MASK 0x000007ffUL
#define VPDSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_BASE_SEG2_MASK 0x0003f000UL
#define VPDSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_SLOPE_SEG2_MASK 0x7ff00000UL

// VPDSCL_EASF_V_BF1_PWL_SEG3
#define VPDSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_IN_SEG3_MASK 0x000007ffUL
#define VPDSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_BASE_SEG3_MASK 0x0003f000UL
#define VPDSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_SLOPE_SEG3_MASK 0x7ff00000UL

// VPDSCL_EASF_V_BF1_PWL_SEG4
#define VPDSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_IN_SEG4_MASK 0x000007ffUL
#define VPDSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_BASE_SEG4_MASK 0x0003f000UL
#define VPDSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_SLOPE_SEG4_MASK 0x7ff00000UL

// VPDSCL_EASF_V_BF1_PWL_SEG5
#define VPDSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_IN_SEG5_MASK 0x000007ffUL
#define VPDSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_BASE_SEG5_MASK 0x0003f000UL
#define VPDSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_SLOPE_SEG5_MASK 0x7ff00000UL

// VPDSCL_EASF_V_BF1_PWL_SEG6
#define VPDSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_IN_SEG6_MASK 0x000007ffUL
#define VPDSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_BASE_SEG6_MASK 0x0003f000UL
#define VPDSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_SLOPE_SEG6_MASK 0x7ff00000UL

// VPDSCL_EASF_V_BF1_PWL_SEG7
#define VPDSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_IN_SEG7_MASK 0x000007ffUL
#define VPDSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_BASE_SEG7_MASK 0x0003f000UL

// VPDSCL_EASF_H_BF3_PWL_SEG0
#define VPDSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_IN_SEG0_MASK 0x00000fffUL
#define VPDSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_BASE_SEG0_MASK 0x0007f000UL
#define VPDSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_SLOPE_SEG0_MASK 0xfff80000UL

// VPDSCL_EASF_H_BF3_PWL_SEG1
#define VPDSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_IN_SEG1_MASK 0x00000fffUL
#define VPDSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_BASE_SEG1_MASK 0x0007f000UL
#define VPDSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_SLOPE_SEG1_MASK 0xfff80000UL

// VPDSCL_EASF_H_BF3_PWL_SEG2
#define VPDSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_IN_SEG2_MASK 0x00000fffUL
#define VPDSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_BASE_SEG2_MASK 0x0007f000UL
#define VPDSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_SLOPE_SEG2_MASK 0xfff80000UL

// VPDSCL_EASF_H_BF3_PWL_SEG3
#define VPDSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_IN_SEG3_MASK 0x00000fffUL
#define VPDSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_BASE_SEG3_MASK 0x0007f000UL
#define VPDSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_SLOPE_SEG3_MASK 0xfff80000UL

// VPDSCL_EASF_H_BF3_PWL_SEG4
#define VPDSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_IN_SEG4_MASK 0x00000fffUL
#define VPDSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_BASE_SEG4_MASK 0x0007f000UL
#define VPDSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_SLOPE_SEG4_MASK 0xfff80000UL

// VPDSCL_EASF_H_BF3_PWL_SEG5
#define VPDSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_IN_SEG5_MASK 0x00000fffUL
#define VPDSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_BASE_SEG5_MASK 0x0007f000UL

// VPDSCL_EASF_V_BF3_PWL_SEG0
#define VPDSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_IN_SEG0_MASK 0x00000fffUL
#define VPDSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_BASE_SEG0_MASK 0x0007f000UL
#define VPDSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_SLOPE_SEG0_MASK 0xfff80000UL

// VPDSCL_EASF_V_BF3_PWL_SEG1
#define VPDSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_IN_SEG1_MASK 0x00000fffUL
#define VPDSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_BASE_SEG1_MASK 0x0007f000UL
#define VPDSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_SLOPE_SEG1_MASK 0xfff80000UL

// VPDSCL_EASF_V_BF3_PWL_SEG2
#define VPDSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_IN_SEG2_MASK 0x00000fffUL
#define VPDSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_BASE_SEG2_MASK 0x0007f000UL
#define VPDSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_SLOPE_SEG2_MASK 0xfff80000UL

// VPDSCL_EASF_V_BF3_PWL_SEG3
#define VPDSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_IN_SEG3_MASK 0x00000fffUL
#define VPDSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_BASE_SEG3_MASK 0x0007f000UL
#define VPDSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_SLOPE_SEG3_MASK 0xfff80000UL

// VPDSCL_EASF_V_BF3_PWL_SEG4
#define VPDSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_IN_SEG4_MASK 0x00000fffUL
#define VPDSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_BASE_SEG4_MASK 0x0007f000UL
#define VPDSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_SLOPE_SEG4_MASK 0xfff80000UL

// VPDSCL_EASF_V_BF3_PWL_SEG5
#define VPDSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_IN_SEG5_MASK 0x00000fffUL
#define VPDSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_BASE_SEG5_MASK 0x0007f000UL

// VPISHARP_MODE
#define VPISHARP_MODE__ISHARP_EN_MASK                      0x00000001UL
#define VPISHARP_MODE__ISHARP_NOISEDET_EN_MASK             0x00000010UL
#define VPISHARP_MODE__ISHARP_NOISEDET_MODE_MASK           0x00000060UL
#define VPISHARP_MODE__ISHARP_LBA_MODE_MASK                0x00000200UL
#define VPISHARP_MODE__ISHARP_FMT_MODE_MASK                0x00000800UL
#define VPISHARP_MODE__ISHARP_FMT_NORM_MASK                0x0ffff000UL
#define VPISHARP_MODE__ISHARP_DELTA_LUT_SELECT_CURRENT_MASK 0x10000000UL

// VPISHARP_DELTA_CTRL
#define VPISHARP_DELTA_CTRL__ISHARP_DELTA_LUT_HOST_SELECT_MASK 0x00000001UL

// VPISHARP_DELTA_INDEX
#define VPISHARP_DELTA_INDEX__ISHARP_DELTA_INDEX_MASK      0x0000001fUL

// VPISHARP_DELTA_DATA
#define VPISHARP_DELTA_DATA__ISHARP_DELTA_DATA_MASK        0xffffffffUL

// VPISHARP_NLDELTA_SOFT_CLIP
#define VPISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_P_MASK 0x00000001UL
#define VPISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_P_MASK 0x000000feUL
#define VPISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_P_MASK 0x0000ff00UL
#define VPISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_N_MASK 0x00010000UL
#define VPISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_N_MASK 0x00fe0000UL
#define VPISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_N_MASK 0xff000000UL

// VPISHARP_NOISEDET_THRESHOLD
#define VPISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_UTHRE_MASK 0x000003ffUL
#define VPISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_DTHRE_MASK 0x03ff0000UL

// VPISHARP_NOISE_GAIN_PWL
#define VPISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_START_IN_MASK 0x0000001fUL
#define VPISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_END_IN_MASK 0x00001f00UL
#define VPISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_SLOPE_MASK 0x3fff0000UL

// VPISHARP_LBA_PWL_SEG0
#define VPISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_IN_SEG0_MASK 0x000003ffUL
#define VPISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_BASE_SEG0_MASK 0x0003f000UL
#define VPISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_SLOPE_SEG0_MASK 0x1ff00000UL

// VPISHARP_LBA_PWL_SEG1
#define VPISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_IN_SEG1_MASK 0x000003ffUL
#define VPISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_BASE_SEG1_MASK 0x0003f000UL
#define VPISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_SLOPE_SEG1_MASK 0x1ff00000UL

// VPISHARP_LBA_PWL_SEG2
#define VPISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_IN_SEG2_MASK 0x000003ffUL
#define VPISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_BASE_SEG2_MASK 0x0003f000UL
#define VPISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_SLOPE_SEG2_MASK 0x1ff00000UL

// VPISHARP_LBA_PWL_SEG3
#define VPISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_IN_SEG3_MASK 0x000003ffUL
#define VPISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_BASE_SEG3_MASK 0x0003f000UL
#define VPISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_SLOPE_SEG3_MASK 0x1ff00000UL

// VPISHARP_LBA_PWL_SEG4
#define VPISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_IN_SEG4_MASK 0x000003ffUL
#define VPISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_BASE_SEG4_MASK 0x0003f000UL
#define VPISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_SLOPE_SEG4_MASK 0x1ff00000UL

// VPISHARP_LBA_PWL_SEG5
#define VPISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_IN_SEG5_MASK 0x000003ffUL
#define VPISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_BASE_SEG5_MASK 0x0003f000UL

// VPISHARP_DELTA_LUT_MEM_PWR_CTRL
#define VPISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_FORCE_MASK 0x00000003UL
#define VPISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_DIS_MASK 0x00000004UL
#define VPISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_STATE_MASK 0x00000030UL

// VPCM_CONTROL
#define VPCM_CONTROL__VPCM_BYPASS_MASK                     0x00000001UL
#define VPCM_CONTROL__VPCM_UPDATE_PENDING_MASK             0x00000100UL

// VPCM_POST_CSC_CONTROL
#define VPCM_POST_CSC_CONTROL__VPCM_POST_CSC_MODE_MASK     0x00000001UL
#define VPCM_POST_CSC_CONTROL__VPCM_POST_CSC_MODE_CURRENT_MASK 0x00000004UL

// VPCM_POST_CSC_C11_C12
#define VPCM_POST_CSC_C11_C12__VPCM_POST_CSC_C11_MASK      0x0000ffffUL
#define VPCM_POST_CSC_C11_C12__VPCM_POST_CSC_C12_MASK      0xffff0000UL

// VPCM_POST_CSC_C13_C14
#define VPCM_POST_CSC_C13_C14__VPCM_POST_CSC_C13_MASK      0x0000ffffUL
#define VPCM_POST_CSC_C13_C14__VPCM_POST_CSC_C14_MASK      0xffff0000UL

// VPCM_POST_CSC_C21_C22
#define VPCM_POST_CSC_C21_C22__VPCM_POST_CSC_C21_MASK      0x0000ffffUL
#define VPCM_POST_CSC_C21_C22__VPCM_POST_CSC_C22_MASK      0xffff0000UL

// VPCM_POST_CSC_C23_C24
#define VPCM_POST_CSC_C23_C24__VPCM_POST_CSC_C23_MASK      0x0000ffffUL
#define VPCM_POST_CSC_C23_C24__VPCM_POST_CSC_C24_MASK      0xffff0000UL

// VPCM_POST_CSC_C31_C32
#define VPCM_POST_CSC_C31_C32__VPCM_POST_CSC_C31_MASK      0x0000ffffUL
#define VPCM_POST_CSC_C31_C32__VPCM_POST_CSC_C32_MASK      0xffff0000UL

// VPCM_POST_CSC_C33_C34
#define VPCM_POST_CSC_C33_C34__VPCM_POST_CSC_C33_MASK      0x0000ffffUL
#define VPCM_POST_CSC_C33_C34__VPCM_POST_CSC_C34_MASK      0xffff0000UL

// VPCM_BIAS_CR_R
#define VPCM_BIAS_CR_R__VPCM_BIAS_CR_R_MASK                0x0000ffffUL

// VPCM_BIAS_Y_G_CB_B
#define VPCM_BIAS_Y_G_CB_B__VPCM_BIAS_Y_G_MASK             0x0000ffffUL
#define VPCM_BIAS_Y_G_CB_B__VPCM_BIAS_CB_B_MASK            0xffff0000UL

// VPCM_GAMCOR_CONTROL
#define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_MODE_MASK         0x00000003UL
#define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_PWL_DISABLE_MASK  0x00000008UL
#define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_MODE_CURRENT_MASK 0x00000030UL
#define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_SELECT_CURRENT_MASK 0x00000040UL

// VPCM_GAMCOR_LUT_INDEX
#define VPCM_GAMCOR_LUT_INDEX__VPCM_GAMCOR_LUT_INDEX_MASK  0x000001ffUL

// VPCM_GAMCOR_LUT_DATA
#define VPCM_GAMCOR_LUT_DATA__VPCM_GAMCOR_LUT_DATA_MASK    0x0003ffffUL

// VPCM_GAMCOR_LUT_CONTROL
#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK 0x00000007UL
#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_READ_COLOR_SEL_MASK 0x00000018UL
#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_READ_DBG_MASK 0x00000020UL
#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_HOST_SEL_MASK 0x00000040UL
#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_CONFIG_MODE_MASK 0x00000080UL

// VPCM_GAMCOR_RAMA_START_CNTL_B
#define VPCM_GAMCOR_RAMA_START_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_B_MASK 0x0003ffffUL
#define VPCM_GAMCOR_RAMA_START_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07f00000UL

// VPCM_GAMCOR_RAMA_START_CNTL_G
#define VPCM_GAMCOR_RAMA_START_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_G_MASK 0x0003ffffUL
#define VPCM_GAMCOR_RAMA_START_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07f00000UL

// VPCM_GAMCOR_RAMA_START_CNTL_R
#define VPCM_GAMCOR_RAMA_START_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_R_MASK 0x0003ffffUL
#define VPCM_GAMCOR_RAMA_START_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07f00000UL

// VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B
#define VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003ffffUL

// VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G
#define VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003ffffUL

// VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R
#define VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003ffffUL

// VPCM_GAMCOR_RAMA_START_BASE_CNTL_B
#define VPCM_GAMCOR_RAMA_START_BASE_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003ffffUL

// VPCM_GAMCOR_RAMA_START_BASE_CNTL_G
#define VPCM_GAMCOR_RAMA_START_BASE_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003ffffUL

// VPCM_GAMCOR_RAMA_START_BASE_CNTL_R
#define VPCM_GAMCOR_RAMA_START_BASE_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003ffffUL

// VPCM_GAMCOR_RAMA_END_CNTL1_B
#define VPCM_GAMCOR_RAMA_END_CNTL1_B__VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003ffffUL

// VPCM_GAMCOR_RAMA_END_CNTL2_B
#define VPCM_GAMCOR_RAMA_END_CNTL2_B__VPCM_GAMCOR_RAMA_EXP_REGION_END_B_MASK 0x0000ffffUL
#define VPCM_GAMCOR_RAMA_END_CNTL2_B__VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xffff0000UL

// VPCM_GAMCOR_RAMA_END_CNTL1_G
#define VPCM_GAMCOR_RAMA_END_CNTL1_G__VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003ffffUL

// VPCM_GAMCOR_RAMA_END_CNTL2_G
#define VPCM_GAMCOR_RAMA_END_CNTL2_G__VPCM_GAMCOR_RAMA_EXP_REGION_END_G_MASK 0x0000ffffUL
#define VPCM_GAMCOR_RAMA_END_CNTL2_G__VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xffff0000UL

// VPCM_GAMCOR_RAMA_END_CNTL1_R
#define VPCM_GAMCOR_RAMA_END_CNTL1_R__VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003ffffUL

// VPCM_GAMCOR_RAMA_END_CNTL2_R
#define VPCM_GAMCOR_RAMA_END_CNTL2_R__VPCM_GAMCOR_RAMA_EXP_REGION_END_R_MASK 0x0000ffffUL
#define VPCM_GAMCOR_RAMA_END_CNTL2_R__VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xffff0000UL

// VPCM_GAMCOR_RAMA_OFFSET_B
#define VPCM_GAMCOR_RAMA_OFFSET_B__VPCM_GAMCOR_RAMA_OFFSET_B_MASK 0x0007ffffUL

// VPCM_GAMCOR_RAMA_OFFSET_G
#define VPCM_GAMCOR_RAMA_OFFSET_G__VPCM_GAMCOR_RAMA_OFFSET_G_MASK 0x0007ffffUL

// VPCM_GAMCOR_RAMA_OFFSET_R
#define VPCM_GAMCOR_RAMA_OFFSET_R__VPCM_GAMCOR_RAMA_OFFSET_R_MASK 0x0007ffffUL

// VPCM_GAMCOR_RAMA_REGION_0_1
#define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001ffUL
#define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000UL
#define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01ff0000UL
#define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000UL

// VPCM_GAMCOR_RAMA_REGION_2_3
#define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001ffUL
#define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000UL
#define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01ff0000UL
#define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000UL

// VPCM_GAMCOR_RAMA_REGION_4_5
#define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001ffUL
#define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000UL
#define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01ff0000UL
#define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000UL

// VPCM_GAMCOR_RAMA_REGION_6_7
#define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001ffUL
#define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000UL
#define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01ff0000UL
#define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000UL

// VPCM_GAMCOR_RAMA_REGION_8_9
#define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001ffUL
#define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000UL
#define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01ff0000UL
#define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000UL

// VPCM_GAMCOR_RAMA_REGION_10_11
#define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001ffUL
#define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000UL
#define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01ff0000UL
#define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000UL

// VPCM_GAMCOR_RAMA_REGION_12_13
#define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001ffUL
#define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000UL
#define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01ff0000UL
#define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000UL

// VPCM_GAMCOR_RAMA_REGION_14_15
#define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001ffUL
#define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000UL
#define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01ff0000UL
#define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000UL

// VPCM_GAMCOR_RAMA_REGION_16_17
#define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001ffUL
#define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000UL
#define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01ff0000UL
#define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000UL

// VPCM_GAMCOR_RAMA_REGION_18_19
#define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001ffUL
#define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000UL
#define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01ff0000UL
#define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000UL

// VPCM_GAMCOR_RAMA_REGION_20_21
#define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001ffUL
#define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000UL
#define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01ff0000UL
#define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000UL

// VPCM_GAMCOR_RAMA_REGION_22_23
#define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001ffUL
#define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000UL
#define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01ff0000UL
#define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000UL

// VPCM_GAMCOR_RAMA_REGION_24_25
#define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001ffUL
#define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000UL
#define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01ff0000UL
#define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000UL

// VPCM_GAMCOR_RAMA_REGION_26_27
#define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001ffUL
#define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000UL
#define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01ff0000UL
#define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000UL

// VPCM_GAMCOR_RAMA_REGION_28_29
#define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001ffUL
#define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000UL
#define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01ff0000UL
#define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000UL

// VPCM_GAMCOR_RAMA_REGION_30_31
#define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001ffUL
#define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000UL
#define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01ff0000UL
#define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000UL

// VPCM_GAMCOR_RAMA_REGION_32_33
#define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001ffUL
#define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000UL
#define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01ff0000UL
#define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000UL

// VPCM_HDR_MULT_COEF
#define VPCM_HDR_MULT_COEF__VPCM_HDR_MULT_COEF_MASK        0x0007ffffUL

// VPCM_MEM_PWR_CTRL
#define VPCM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK       0x00000003UL
#define VPCM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK         0x00000004UL

// VPCM_MEM_PWR_STATUS
#define VPCM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK     0x00000003UL

// VPCM_DEALPHA
#define VPCM_DEALPHA__VPCM_DEALPHA_EN_MASK                 0x00000001UL
#define VPCM_DEALPHA__VPCM_DEALPHA_ABLND_MASK              0x00000002UL

// VPCM_COEF_FORMAT
#define VPCM_COEF_FORMAT__VPCM_BIAS_FORMAT_MASK            0x00000001UL
#define VPCM_COEF_FORMAT__VPCM_POST_CSC_COEF_FORMAT_MASK   0x00000010UL

// VPCM_HIST_CNTL
#define VPCM_HIST_CNTL__VPCM_HIST_SEL_MASK                 0x00000003UL
#define VPCM_HIST_CNTL__VPCM_HIST_CH_EN_MASK               0x0000000cUL
#define VPCM_HIST_CNTL__VPCM_HIST_SRC1_SEL_MASK            0x00000010UL
#define VPCM_HIST_CNTL__VPCM_HIST_SRC2_SEL_MASK            0x00000020UL
#define VPCM_HIST_CNTL__VPCM_HIST_SRC3_SEL_MASK            0x00000040UL
#define VPCM_HIST_CNTL__VPCM_HIST_CH1_XBAR_MASK            0x00000180UL
#define VPCM_HIST_CNTL__VPCM_HIST_CH2_XBAR_MASK            0x00000600UL
#define VPCM_HIST_CNTL__VPCM_HIST_CH3_XBAR_MASK            0x00001800UL
#define VPCM_HIST_CNTL__VPCM_HIST_FORMAT_MASK              0x00006000UL
#define VPCM_HIST_CNTL__VPCM_HIST_READ_CHANNEL_MASK_MASK   0x00038000UL

// VPCM_HIST_SCALE_SRC1
#define VPCM_HIST_SCALE_SRC1__VPCM_HIST_SCALE_SRC1_MASK    0x0007ffffUL

// VPCM_HIST_COEFA_SRC2
#define VPCM_HIST_COEFA_SRC2__VPCM_HIST_COEFA_SRC2_MASK    0x0007ffffUL

// VPCM_HIST_COEFB_SRC2
#define VPCM_HIST_COEFB_SRC2__VPCM_HIST_COEFB_SRC2_MASK    0x0007ffffUL

// VPCM_HIST_COEFC_SRC2
#define VPCM_HIST_COEFC_SRC2__VPCM_HIST_COEFC_SRC2_MASK    0x0007ffffUL

// VPCM_HIST_SCALE_SRC3
#define VPCM_HIST_SCALE_SRC3__VPCM_HIST_SCALE_SRC3_MASK    0x0007ffffUL

// VPCM_HIST_BIAS_SRC1
#define VPCM_HIST_BIAS_SRC1__VPCM_HIST_BIAS_SRC1_MASK      0x0007ffffUL

// VPCM_HIST_BIAS_SRC2
#define VPCM_HIST_BIAS_SRC2__VPCM_HIST_BIAS_SRC2_MASK      0x0007ffffUL

// VPCM_HIST_BIAS_SRC3
#define VPCM_HIST_BIAS_SRC3__VPCM_HIST_BIAS_SRC3_MASK      0x0007ffffUL

// VPDPP_CONTROL
#define VPDPP_CONTROL__VPECLK_G_GATE_DISABLE_MASK          0x00000100UL
#define VPDPP_CONTROL__VPECLK_G_VPDSCL_GATE_DISABLE_MASK   0x00001000UL
#define VPDPP_CONTROL__VPDPP_FGCG_REP_DIS_MASK             0x01000000UL

// VPDPP_CRC_CTRL
#define VPDPP_CRC_CTRL__VPDPP_CRC_EN_MASK                  0x00000001UL
#define VPDPP_CRC_CTRL__VPDPP_CRC_CONT_EN_MASK             0x00000002UL
#define VPDPP_CRC_CTRL__VPDPP_CRC_420_COMP_SEL_MASK        0x00000008UL
#define VPDPP_CRC_CTRL__VPDPP_CRC_SRC_SEL_MASK             0x00000030UL
#define VPDPP_CRC_CTRL__VPDPP_CRC_PIX_FORMAT_SEL_MASK      0x00003800UL
#define VPDPP_CRC_CTRL__VPDPP_CRC_MASK_MASK                0xffff0000UL

// VPMPC_CLOCK_CONTROL
#define VPMPC_CLOCK_CONTROL__VPECLK_R_GATE_DISABLE_MASK    0x00000002UL

// VPMPC_SOFT_RESET
#define VPMPC_SOFT_RESET__VPMPCC0_SOFT_RESET_MASK          0x00000001UL
#define VPMPC_SOFT_RESET__VPMPC_SFR0_SOFT_RESET_MASK       0x00000400UL
#define VPMPC_SOFT_RESET__VPMPC_SFT0_SOFT_RESET_MASK       0x00100000UL
#define VPMPC_SOFT_RESET__VPMPC_SOFT_RESET_MASK            0x80000000UL

// VPMPC_CRC_CTRL
#define VPMPC_CRC_CTRL__VPMPC_CRC_EN_MASK                  0x00000001UL
#define VPMPC_CRC_CTRL__VPMPC_CRC_CONT_EN_MASK             0x00000010UL
#define VPMPC_CRC_CTRL__VPMPC_CRC_SRC_SEL_MASK             0x03000000UL
#define VPMPC_CRC_CTRL__VPMPC_CRC_ONE_SHOT_PENDING_MASK    0x10000000UL
#define VPMPC_CRC_CTRL__VPMPC_CRC_UPDATE_ENABLED_MASK      0x40000000UL
#define VPMPC_CRC_CTRL__VPMPC_CRC_UPDATE_LOCK_MASK         0x80000000UL

// VPMPC_CRC_SEL_CONTROL
#define VPMPC_CRC_SEL_CONTROL__VPMPC_CRC_VPDPP_SEL_MASK    0x0000000fUL
#define VPMPC_CRC_SEL_CONTROL__VPMPC_CRC_VPOPP_SEL_MASK    0x000000f0UL
#define VPMPC_CRC_SEL_CONTROL__VPMPC_CRC_MASK_MASK         0xffff0000UL

// VPMPC_CRC_RESULT_AR
#define VPMPC_CRC_RESULT_AR__VPMPC_CRC_RESULT_A_MASK       0x0000ffffUL
#define VPMPC_CRC_RESULT_AR__VPMPC_CRC_RESULT_R_MASK       0xffff0000UL

// VPMPC_CRC_RESULT_GB
#define VPMPC_CRC_RESULT_GB__VPMPC_CRC_RESULT_G_MASK       0x0000ffffUL
#define VPMPC_CRC_RESULT_GB__VPMPC_CRC_RESULT_B_MASK       0xffff0000UL

// VPMPC_CRC_RESULT_C
#define VPMPC_CRC_RESULT_C__VPMPC_CRC_RESULT_C_MASK        0x0000ffffUL

// VPMPC_BYPASS_BG_AR
#define VPMPC_BYPASS_BG_AR__VPMPC_BYPASS_BG_ALPHA_MASK     0x0000ffffUL
#define VPMPC_BYPASS_BG_AR__VPMPC_BYPASS_BG_R_CR_MASK      0xffff0000UL

// VPMPC_BYPASS_BG_GB
#define VPMPC_BYPASS_BG_GB__VPMPC_BYPASS_BG_G_Y_MASK       0x0000ffffUL
#define VPMPC_BYPASS_BG_GB__VPMPC_BYPASS_BG_B_CB_MASK      0xffff0000UL

// VPMPC_HOST_READ_CONTROL
#define VPMPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000ffUL

// VPMPC_PENDING_STATUS_MISC
#define VPMPC_PENDING_STATUS_MISC__VPMPCC0_CONFIG_UPDATE_PENDING_MASK 0x00000100UL

// VPMPC_VPCDC0_3DLUT_FL_CONFIG
#define VPMPC_VPCDC0_3DLUT_FL_CONFIG__VPCDC0_3DLUT_FL_MODE_MASK 0x00000003UL
#define VPMPC_VPCDC0_3DLUT_FL_CONFIG__VPCDC0_3DLUT_FL_FORMAT_MASK 0x00000030UL

// VPMPC_VPCDC0_3DLUT_FL_BIAS_SCALE
#define VPMPC_VPCDC0_3DLUT_FL_BIAS_SCALE__VPCDC0_3DLUT_FL_BIAS_MASK 0x0000ffffUL
#define VPMPC_VPCDC0_3DLUT_FL_BIAS_SCALE__VPCDC0_3DLUT_FL_SCALE_MASK 0xffff0000UL

// VPMPC_OUT0_MUX
#define VPMPC_OUT0_MUX__VPMPC_OUT_MUX_MASK                 0x0000000fUL

// VPMPC_OUT0_FLOAT_CONTROL
#define VPMPC_OUT0_FLOAT_CONTROL__VPMPC_OUT_FLOAT_EN_MASK  0x00000001UL

// VPMPC_OUT0_DENORM_CONTROL
#define VPMPC_OUT0_DENORM_CONTROL__VPMPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000fffUL
#define VPMPC_OUT0_DENORM_CONTROL__VPMPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00fff000UL
#define VPMPC_OUT0_DENORM_CONTROL__VPMPC_OUT_DENORM_MODE_MASK 0x07000000UL

// VPMPC_OUT0_DENORM_CLAMP_G_Y
#define VPMPC_OUT0_DENORM_CLAMP_G_Y__VPMPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000fffUL
#define VPMPC_OUT0_DENORM_CLAMP_G_Y__VPMPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00fff000UL

// VPMPC_OUT0_DENORM_CLAMP_B_CB
#define VPMPC_OUT0_DENORM_CLAMP_B_CB__VPMPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000fffUL
#define VPMPC_OUT0_DENORM_CLAMP_B_CB__VPMPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00fff000UL

// VPMPC_OUT_CSC_COEF_FORMAT
#define VPMPC_OUT_CSC_COEF_FORMAT__VPMPC_OCSC0_COEF_FORMAT_MASK 0x00000001UL

// VPMPC_OUT0_CSC_MODE
#define VPMPC_OUT0_CSC_MODE__VPMPC_OCSC_MODE_MASK          0x00000001UL
#define VPMPC_OUT0_CSC_MODE__VPMPC_OCSC_MODE_CURRENT_MASK  0x00000080UL

// VPMPC_OUT0_CSC_C11_C12_A
#define VPMPC_OUT0_CSC_C11_C12_A__VPMPC_OCSC_C11_A_MASK    0x0000ffffUL
#define VPMPC_OUT0_CSC_C11_C12_A__VPMPC_OCSC_C12_A_MASK    0xffff0000UL

// VPMPC_OUT0_CSC_C13_C14_A
#define VPMPC_OUT0_CSC_C13_C14_A__VPMPC_OCSC_C13_A_MASK    0x0000ffffUL
#define VPMPC_OUT0_CSC_C13_C14_A__VPMPC_OCSC_C14_A_MASK    0xffff0000UL

// VPMPC_OUT0_CSC_C21_C22_A
#define VPMPC_OUT0_CSC_C21_C22_A__VPMPC_OCSC_C21_A_MASK    0x0000ffffUL
#define VPMPC_OUT0_CSC_C21_C22_A__VPMPC_OCSC_C22_A_MASK    0xffff0000UL

// VPMPC_OUT0_CSC_C23_C24_A
#define VPMPC_OUT0_CSC_C23_C24_A__VPMPC_OCSC_C23_A_MASK    0x0000ffffUL
#define VPMPC_OUT0_CSC_C23_C24_A__VPMPC_OCSC_C24_A_MASK    0xffff0000UL

// VPMPC_OUT0_CSC_C31_C32_A
#define VPMPC_OUT0_CSC_C31_C32_A__VPMPC_OCSC_C31_A_MASK    0x0000ffffUL
#define VPMPC_OUT0_CSC_C31_C32_A__VPMPC_OCSC_C32_A_MASK    0xffff0000UL

// VPMPC_OUT0_CSC_C33_C34_A
#define VPMPC_OUT0_CSC_C33_C34_A__VPMPC_OCSC_C33_A_MASK    0x0000ffffUL
#define VPMPC_OUT0_CSC_C33_C34_A__VPMPC_OCSC_C34_A_MASK    0xffff0000UL

// VPMPCC_TOP_SEL
#define VPMPCC_TOP_SEL__VPMPCC_TOP_SEL_MASK                0x0000000fUL

// VPMPCC_BOT_SEL
#define VPMPCC_BOT_SEL__VPMPCC_BOT_SEL_MASK                0x0000000fUL

// VPMPCC_VPOPP_ID
#define VPMPCC_VPOPP_ID__VPMPCC_VPOPP_ID_MASK              0x0000000fUL

// VPMPCC_CONTROL
#define VPMPCC_CONTROL__VPMPCC_MODE_MASK                   0x00000003UL
#define VPMPCC_CONTROL__VPMPCC_ALPHA_BLND_MODE_MASK        0x00000030UL
#define VPMPCC_CONTROL__VPMPCC_ALPHA_MULTIPLIED_MODE_MASK  0x00000040UL
#define VPMPCC_CONTROL__VPMPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080UL
#define VPMPCC_CONTROL__VPMPCC_BOT_GAIN_MODE_MASK          0x00000800UL

// VPMPCC_CONTROL2
#define VPMPCC_CONTROL2__VPMPCC_GLOBAL_ALPHA_MASK          0x00000fffUL
#define VPMPCC_CONTROL2__VPMPCC_GLOBAL_GAIN_MASK           0x0fff0000UL

// VPMPCC_TOP_GAIN
#define VPMPCC_TOP_GAIN__VPMPCC_TOP_GAIN_MASK              0x0007ffffUL

// VPMPCC_BOT_GAIN_INSIDE
#define VPMPCC_BOT_GAIN_INSIDE__VPMPCC_BOT_GAIN_INSIDE_MASK 0x0007ffffUL

// VPMPCC_BOT_GAIN_OUTSIDE
#define VPMPCC_BOT_GAIN_OUTSIDE__VPMPCC_BOT_GAIN_OUTSIDE_MASK 0x0007ffffUL

// VPMPCC_MOVABLE_CM_LOCATION_CONTROL
#define VPMPCC_MOVABLE_CM_LOCATION_CONTROL__VPMPCC_MOVABLE_CM_LOCATION_CNTL_MASK 0x00000001UL
#define VPMPCC_MOVABLE_CM_LOCATION_CONTROL__VPMPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK 0x00000010UL

// VPMPCC_BG_R_CR
#define VPMPCC_BG_R_CR__VPMPCC_BG_R_CR_MASK                0x0007ffffUL

// VPMPCC_BG_G_Y
#define VPMPCC_BG_G_Y__VPMPCC_BG_G_Y_MASK                  0x0007ffffUL

// VPMPCC_BG_B_CB
#define VPMPCC_BG_B_CB__VPMPCC_BG_B_CB_MASK                0x0007ffffUL

// VPMPCC_MEM_PWR_CTRL
#define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003UL
#define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_PWR_DIS_MASK  0x00000004UL
#define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_LOW_PWR_MODE_MASK 0x00000030UL
#define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_PWR_STATE_MASK 0x00000300UL

// VPMPCC_STATUS
#define VPMPCC_STATUS__VPMPCC_IDLE_MASK                    0x00000001UL
#define VPMPCC_STATUS__VPMPCC_BUSY_MASK                    0x00000002UL
#define VPMPCC_STATUS__VPMPCC_DISABLED_MASK                0x00000004UL

// VPMPCC_OGAM_CONTROL
#define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_MODE_MASK         0x00000003UL
#define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_PWL_DISABLE_MASK  0x00000008UL
#define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_MODE_CURRENT_MASK 0x00000180UL
#define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_SELECT_CURRENT_MASK 0x00000200UL

// VPMPCC_OGAM_LUT_INDEX
#define VPMPCC_OGAM_LUT_INDEX__VPMPCC_OGAM_LUT_INDEX_MASK  0x000001ffUL

// VPMPCC_OGAM_LUT_DATA
#define VPMPCC_OGAM_LUT_DATA__VPMPCC_OGAM_LUT_DATA_MASK    0x0003ffffUL

// VPMPCC_OGAM_LUT_CONTROL
#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007UL
#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_READ_COLOR_SEL_MASK 0x00000018UL
#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_READ_DBG_MASK 0x00000020UL
#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_HOST_SEL_MASK 0x00000040UL
#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_CONFIG_MODE_MASK 0x00000080UL

// VPMPCC_OGAM_RAMA_START_CNTL_B
#define VPMPCC_OGAM_RAMA_START_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003ffffUL
#define VPMPCC_OGAM_RAMA_START_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07f00000UL

// VPMPCC_OGAM_RAMA_START_CNTL_G
#define VPMPCC_OGAM_RAMA_START_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003ffffUL
#define VPMPCC_OGAM_RAMA_START_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07f00000UL

// VPMPCC_OGAM_RAMA_START_CNTL_R
#define VPMPCC_OGAM_RAMA_START_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003ffffUL
#define VPMPCC_OGAM_RAMA_START_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07f00000UL

// VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B
#define VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003ffffUL

// VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G
#define VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003ffffUL

// VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R
#define VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003ffffUL

// VPMPCC_OGAM_RAMA_START_BASE_CNTL_B
#define VPMPCC_OGAM_RAMA_START_BASE_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003ffffUL

// VPMPCC_OGAM_RAMA_START_BASE_CNTL_G
#define VPMPCC_OGAM_RAMA_START_BASE_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003ffffUL

// VPMPCC_OGAM_RAMA_START_BASE_CNTL_R
#define VPMPCC_OGAM_RAMA_START_BASE_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003ffffUL

// VPMPCC_OGAM_RAMA_END_CNTL1_B
#define VPMPCC_OGAM_RAMA_END_CNTL1_B__VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003ffffUL

// VPMPCC_OGAM_RAMA_END_CNTL2_B
#define VPMPCC_OGAM_RAMA_END_CNTL2_B__VPMPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000ffffUL
#define VPMPCC_OGAM_RAMA_END_CNTL2_B__VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xffff0000UL

// VPMPCC_OGAM_RAMA_END_CNTL1_G
#define VPMPCC_OGAM_RAMA_END_CNTL1_G__VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003ffffUL

// VPMPCC_OGAM_RAMA_END_CNTL2_G
#define VPMPCC_OGAM_RAMA_END_CNTL2_G__VPMPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000ffffUL
#define VPMPCC_OGAM_RAMA_END_CNTL2_G__VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xffff0000UL

// VPMPCC_OGAM_RAMA_END_CNTL1_R
#define VPMPCC_OGAM_RAMA_END_CNTL1_R__VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003ffffUL

// VPMPCC_OGAM_RAMA_END_CNTL2_R
#define VPMPCC_OGAM_RAMA_END_CNTL2_R__VPMPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000ffffUL
#define VPMPCC_OGAM_RAMA_END_CNTL2_R__VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xffff0000UL

// VPMPCC_OGAM_RAMA_OFFSET_B
#define VPMPCC_OGAM_RAMA_OFFSET_B__VPMPCC_OGAM_RAMA_OFFSET_B_MASK 0x0007ffffUL

// VPMPCC_OGAM_RAMA_OFFSET_G
#define VPMPCC_OGAM_RAMA_OFFSET_G__VPMPCC_OGAM_RAMA_OFFSET_G_MASK 0x0007ffffUL

// VPMPCC_OGAM_RAMA_OFFSET_R
#define VPMPCC_OGAM_RAMA_OFFSET_R__VPMPCC_OGAM_RAMA_OFFSET_R_MASK 0x0007ffffUL

// VPMPCC_OGAM_RAMA_REGION_0_1
#define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_OGAM_RAMA_REGION_2_3
#define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_OGAM_RAMA_REGION_4_5
#define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_OGAM_RAMA_REGION_6_7
#define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_OGAM_RAMA_REGION_8_9
#define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_OGAM_RAMA_REGION_10_11
#define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_OGAM_RAMA_REGION_12_13
#define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_OGAM_RAMA_REGION_14_15
#define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_OGAM_RAMA_REGION_16_17
#define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_OGAM_RAMA_REGION_18_19
#define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_OGAM_RAMA_REGION_20_21
#define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_OGAM_RAMA_REGION_22_23
#define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_OGAM_RAMA_REGION_24_25
#define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_OGAM_RAMA_REGION_26_27
#define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_OGAM_RAMA_REGION_28_29
#define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_OGAM_RAMA_REGION_30_31
#define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_OGAM_RAMA_REGION_32_33
#define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_GAMUT_REMAP_COEF_FORMAT
#define VPMPCC_GAMUT_REMAP_COEF_FORMAT__VPMPCC_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001UL

// VPMPCC_GAMUT_REMAP_MODE
#define VPMPCC_GAMUT_REMAP_MODE__VPMPCC_GAMUT_REMAP_MODE_MASK 0x00000001UL
#define VPMPCC_GAMUT_REMAP_MODE__VPMPCC_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000080UL

// VPMPC_GAMUT_REMAP_C11_C12_A
#define VPMPC_GAMUT_REMAP_C11_C12_A__VPMPCC_GAMUT_REMAP_C11_A_MASK 0x0000ffffUL
#define VPMPC_GAMUT_REMAP_C11_C12_A__VPMPCC_GAMUT_REMAP_C12_A_MASK 0xffff0000UL

// VPMPC_GAMUT_REMAP_C13_C14_A
#define VPMPC_GAMUT_REMAP_C13_C14_A__VPMPCC_GAMUT_REMAP_C13_A_MASK 0x0000ffffUL
#define VPMPC_GAMUT_REMAP_C13_C14_A__VPMPCC_GAMUT_REMAP_C14_A_MASK 0xffff0000UL

// VPMPC_GAMUT_REMAP_C21_C22_A
#define VPMPC_GAMUT_REMAP_C21_C22_A__VPMPCC_GAMUT_REMAP_C21_A_MASK 0x0000ffffUL
#define VPMPC_GAMUT_REMAP_C21_C22_A__VPMPCC_GAMUT_REMAP_C22_A_MASK 0xffff0000UL

// VPMPC_GAMUT_REMAP_C23_C24_A
#define VPMPC_GAMUT_REMAP_C23_C24_A__VPMPCC_GAMUT_REMAP_C23_A_MASK 0x0000ffffUL
#define VPMPC_GAMUT_REMAP_C23_C24_A__VPMPCC_GAMUT_REMAP_C24_A_MASK 0xffff0000UL

// VPMPC_GAMUT_REMAP_C31_C32_A
#define VPMPC_GAMUT_REMAP_C31_C32_A__VPMPCC_GAMUT_REMAP_C31_A_MASK 0x0000ffffUL
#define VPMPC_GAMUT_REMAP_C31_C32_A__VPMPCC_GAMUT_REMAP_C32_A_MASK 0xffff0000UL

// VPMPC_GAMUT_REMAP_C33_C34_A
#define VPMPC_GAMUT_REMAP_C33_C34_A__VPMPCC_GAMUT_REMAP_C33_A_MASK 0x0000ffffUL
#define VPMPC_GAMUT_REMAP_C33_C34_A__VPMPCC_GAMUT_REMAP_C34_A_MASK 0xffff0000UL

// VPMPCC_MCM_1DLUT_CONTROL
#define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_MODE_MASK 0x00000003UL
#define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_PWL_DISABLE_MASK 0x00000008UL
#define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_MODE_CURRENT_MASK 0x00000030UL
#define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_SELECT_CURRENT_MASK 0x00000040UL

// VPMPCC_MCM_1DLUT_LUT_INDEX
#define VPMPCC_MCM_1DLUT_LUT_INDEX__VPMPCC_MCM_1DLUT_LUT_INDEX_MASK 0x000001ffUL

// VPMPCC_MCM_1DLUT_LUT_DATA
#define VPMPCC_MCM_1DLUT_LUT_DATA__VPMPCC_MCM_1DLUT_LUT_DATA_MASK 0x0003ffffUL

// VPMPCC_MCM_1DLUT_LUT_CONTROL
#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK 0x00000007UL
#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK 0x00000018UL
#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_READ_DBG_MASK 0x00000020UL
#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_HOST_SEL_MASK 0x00000040UL
#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK 0x00000080UL

// VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B
#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK 0x0003ffffUL
#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07f00000UL

// VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G
#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK 0x0003ffffUL
#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07f00000UL

// VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R
#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK 0x0003ffffUL
#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07f00000UL

// VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B
#define VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003ffffUL

// VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G
#define VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003ffffUL

// VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R
#define VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003ffffUL

// VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B
#define VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003ffffUL

// VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G
#define VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003ffffUL

// VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R
#define VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003ffffUL

// VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B
#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003ffffUL

// VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B
#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK 0x0000ffffUL
#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xffff0000UL

// VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G
#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003ffffUL

// VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G
#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK 0x0000ffffUL
#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xffff0000UL

// VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R
#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003ffffUL

// VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R
#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK 0x0000ffffUL
#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xffff0000UL

// VPMPCC_MCM_1DLUT_RAMA_OFFSET_B
#define VPMPCC_MCM_1DLUT_RAMA_OFFSET_B__VPMPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK 0x0007ffffUL

// VPMPCC_MCM_1DLUT_RAMA_OFFSET_G
#define VPMPCC_MCM_1DLUT_RAMA_OFFSET_G__VPMPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK 0x0007ffffUL

// VPMPCC_MCM_1DLUT_RAMA_OFFSET_R
#define VPMPCC_MCM_1DLUT_RAMA_OFFSET_R__VPMPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK 0x0007ffffUL

// VPMPCC_MCM_1DLUT_RAMA_REGION_0_1
#define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_MCM_1DLUT_RAMA_REGION_2_3
#define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_MCM_1DLUT_RAMA_REGION_4_5
#define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_MCM_1DLUT_RAMA_REGION_6_7
#define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_MCM_1DLUT_RAMA_REGION_8_9
#define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_MCM_1DLUT_RAMA_REGION_10_11
#define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_MCM_1DLUT_RAMA_REGION_12_13
#define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_MCM_1DLUT_RAMA_REGION_14_15
#define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_MCM_1DLUT_RAMA_REGION_16_17
#define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_MCM_1DLUT_RAMA_REGION_18_19
#define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_MCM_1DLUT_RAMA_REGION_20_21
#define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_MCM_1DLUT_RAMA_REGION_22_23
#define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_MCM_1DLUT_RAMA_REGION_24_25
#define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_MCM_1DLUT_RAMA_REGION_26_27
#define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_MCM_1DLUT_RAMA_REGION_28_29
#define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_MCM_1DLUT_RAMA_REGION_30_31
#define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_MCM_1DLUT_RAMA_REGION_32_33
#define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT
#define VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001UL

// VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE
#define VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE__VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE_MASK 0x00000003UL
#define VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE__VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180UL

// VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA
#define VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C11_SETA_MASK 0x0000ffffUL
#define VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C12_SETA_MASK 0xffff0000UL

// VPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA
#define VPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C13_SETA_MASK 0x0000ffffUL
#define VPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C14_SETA_MASK 0xffff0000UL

// VPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA
#define VPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C21_SETA_MASK 0x0000ffffUL
#define VPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C22_SETA_MASK 0xffff0000UL

// VPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA
#define VPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C23_SETA_MASK 0x0000ffffUL
#define VPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C24_SETA_MASK 0xffff0000UL

// VPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA
#define VPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C31_SETA_MASK 0x0000ffffUL
#define VPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C32_SETA_MASK 0xffff0000UL

// VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA
#define VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C33_SETA_MASK 0x0000ffffUL
#define VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C34_SETA_MASK 0xffff0000UL

// VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT
#define VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001UL

// VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE
#define VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE__VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE_MASK 0x00000003UL
#define VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE__VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180UL

// VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA
#define VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C11_SETA_MASK 0x0000ffffUL
#define VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C12_SETA_MASK 0xffff0000UL

// VPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA
#define VPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C13_SETA_MASK 0x0000ffffUL
#define VPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C14_SETA_MASK 0xffff0000UL

// VPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA
#define VPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C21_SETA_MASK 0x0000ffffUL
#define VPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C22_SETA_MASK 0xffff0000UL

// VPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA
#define VPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C23_SETA_MASK 0x0000ffffUL
#define VPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C24_SETA_MASK 0xffff0000UL

// VPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA
#define VPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C31_SETA_MASK 0x0000ffffUL
#define VPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C32_SETA_MASK 0xffff0000UL

// VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA
#define VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C33_SETA_MASK 0x0000ffffUL
#define VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C34_SETA_MASK 0xffff0000UL

// VPMPCC_MCM_MEM_PWR_CTRL
#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK 0x00030000UL
#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_PWR_DIS_MASK 0x00040000UL
#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK 0x00300000UL
#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_PWR_STATE_MASK 0x30000000UL

// VPMPC_RMCM_SHAPER_CONTROL
#define VPMPC_RMCM_SHAPER_CONTROL__VPMPC_RMCM_SHAPER_LUT_MODE_MASK 0x00000003UL
#define VPMPC_RMCM_SHAPER_CONTROL__VPMPC_RMCM_SHAPER_MODE_CURRENT_MASK 0x0000000cUL
#define VPMPC_RMCM_SHAPER_CONTROL__VPMPC_RMCM_SHAPER_SELECT_CURRENT_MASK 0x00000010UL

// VPMPC_RMCM_SHAPER_OFFSET_R
#define VPMPC_RMCM_SHAPER_OFFSET_R__VPMPC_RMCM_SHAPER_OFFSET_R_MASK 0x0007ffffUL

// VPMPC_RMCM_SHAPER_OFFSET_G
#define VPMPC_RMCM_SHAPER_OFFSET_G__VPMPC_RMCM_SHAPER_OFFSET_G_MASK 0x0007ffffUL

// VPMPC_RMCM_SHAPER_OFFSET_B
#define VPMPC_RMCM_SHAPER_OFFSET_B__VPMPC_RMCM_SHAPER_OFFSET_B_MASK 0x0007ffffUL

// VPMPC_RMCM_SHAPER_SCALE_R
#define VPMPC_RMCM_SHAPER_SCALE_R__VPMPC_RMCM_SHAPER_SCALE_R_MASK 0x0000ffffUL

// VPMPC_RMCM_SHAPER_SCALE_G_B
#define VPMPC_RMCM_SHAPER_SCALE_G_B__VPMPC_RMCM_SHAPER_SCALE_G_MASK 0x0000ffffUL
#define VPMPC_RMCM_SHAPER_SCALE_G_B__VPMPC_RMCM_SHAPER_SCALE_B_MASK 0xffff0000UL

// VPMPC_RMCM_SHAPER_LUT_INDEX
#define VPMPC_RMCM_SHAPER_LUT_INDEX__VPMPC_RMCM_SHAPER_LUT_INDEX_MASK 0x000000ffUL

// VPMPC_RMCM_SHAPER_LUT_DATA
#define VPMPC_RMCM_SHAPER_LUT_DATA__VPMPC_RMCM_SHAPER_LUT_DATA_MASK 0x00ffffffUL

// VPMPC_RMCM_SHAPER_LUT_WRITE_EN_MASK
#define VPMPC_RMCM_SHAPER_LUT_WRITE_EN_MASK__VPMPC_RMCM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007UL
#define VPMPC_RMCM_SHAPER_LUT_WRITE_EN_MASK__VPMPC_RMCM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010UL

// VPMPC_RMCM_SHAPER_RAMA_START_CNTL_B
#define VPMPC_RMCM_SHAPER_RAMA_START_CNTL_B__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003ffffUL
#define VPMPC_RMCM_SHAPER_RAMA_START_CNTL_B__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07f00000UL

// VPMPC_RMCM_SHAPER_RAMA_START_CNTL_G
#define VPMPC_RMCM_SHAPER_RAMA_START_CNTL_G__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003ffffUL
#define VPMPC_RMCM_SHAPER_RAMA_START_CNTL_G__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07f00000UL

// VPMPC_RMCM_SHAPER_RAMA_START_CNTL_R
#define VPMPC_RMCM_SHAPER_RAMA_START_CNTL_R__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003ffffUL
#define VPMPC_RMCM_SHAPER_RAMA_START_CNTL_R__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07f00000UL

// VPMPC_RMCM_SHAPER_RAMA_END_CNTL_B
#define VPMPC_RMCM_SHAPER_RAMA_END_CNTL_B__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000ffffUL
#define VPMPC_RMCM_SHAPER_RAMA_END_CNTL_B__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3fff0000UL

// VPMPC_RMCM_SHAPER_RAMA_END_CNTL_G
#define VPMPC_RMCM_SHAPER_RAMA_END_CNTL_G__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000ffffUL
#define VPMPC_RMCM_SHAPER_RAMA_END_CNTL_G__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3fff0000UL

// VPMPC_RMCM_SHAPER_RAMA_END_CNTL_R
#define VPMPC_RMCM_SHAPER_RAMA_END_CNTL_R__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000ffffUL
#define VPMPC_RMCM_SHAPER_RAMA_END_CNTL_R__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3fff0000UL

// VPMPC_RMCM_SHAPER_RAMA_REGION_0_1
#define VPMPC_RMCM_SHAPER_RAMA_REGION_0_1__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_0_1__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_0_1__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_0_1__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPC_RMCM_SHAPER_RAMA_REGION_2_3
#define VPMPC_RMCM_SHAPER_RAMA_REGION_2_3__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_2_3__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_2_3__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_2_3__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPC_RMCM_SHAPER_RAMA_REGION_4_5
#define VPMPC_RMCM_SHAPER_RAMA_REGION_4_5__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_4_5__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_4_5__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_4_5__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPC_RMCM_SHAPER_RAMA_REGION_6_7
#define VPMPC_RMCM_SHAPER_RAMA_REGION_6_7__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_6_7__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_6_7__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_6_7__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPC_RMCM_SHAPER_RAMA_REGION_8_9
#define VPMPC_RMCM_SHAPER_RAMA_REGION_8_9__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_8_9__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_8_9__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_8_9__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPC_RMCM_SHAPER_RAMA_REGION_10_11
#define VPMPC_RMCM_SHAPER_RAMA_REGION_10_11__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_10_11__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_10_11__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_10_11__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPC_RMCM_SHAPER_RAMA_REGION_12_13
#define VPMPC_RMCM_SHAPER_RAMA_REGION_12_13__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_12_13__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_12_13__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_12_13__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPC_RMCM_SHAPER_RAMA_REGION_14_15
#define VPMPC_RMCM_SHAPER_RAMA_REGION_14_15__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_14_15__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_14_15__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_14_15__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPC_RMCM_SHAPER_RAMA_REGION_16_17
#define VPMPC_RMCM_SHAPER_RAMA_REGION_16_17__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_16_17__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_16_17__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_16_17__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPC_RMCM_SHAPER_RAMA_REGION_18_19
#define VPMPC_RMCM_SHAPER_RAMA_REGION_18_19__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_18_19__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_18_19__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_18_19__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPC_RMCM_SHAPER_RAMA_REGION_20_21
#define VPMPC_RMCM_SHAPER_RAMA_REGION_20_21__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_20_21__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_20_21__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_20_21__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPC_RMCM_SHAPER_RAMA_REGION_22_23
#define VPMPC_RMCM_SHAPER_RAMA_REGION_22_23__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_22_23__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_22_23__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_22_23__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPC_RMCM_SHAPER_RAMA_REGION_24_25
#define VPMPC_RMCM_SHAPER_RAMA_REGION_24_25__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_24_25__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_24_25__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_24_25__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPC_RMCM_SHAPER_RAMA_REGION_26_27
#define VPMPC_RMCM_SHAPER_RAMA_REGION_26_27__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_26_27__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_26_27__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_26_27__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPC_RMCM_SHAPER_RAMA_REGION_28_29
#define VPMPC_RMCM_SHAPER_RAMA_REGION_28_29__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_28_29__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_28_29__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_28_29__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPC_RMCM_SHAPER_RAMA_REGION_30_31
#define VPMPC_RMCM_SHAPER_RAMA_REGION_30_31__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_30_31__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_30_31__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_30_31__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPC_RMCM_SHAPER_RAMA_REGION_32_33
#define VPMPC_RMCM_SHAPER_RAMA_REGION_32_33__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_32_33__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_32_33__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_32_33__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPC_RMCM_3DLUT_MODE
#define VPMPC_RMCM_3DLUT_MODE__VPMPC_RMCM_3DLUT_MODE_MASK  0x00000003UL
#define VPMPC_RMCM_3DLUT_MODE__VPMPC_RMCM_3DLUT_SIZE_MASK  0x00000030UL
#define VPMPC_RMCM_3DLUT_MODE__VPMPC_RMCM_3DLUT_MODE_CURRENT_MASK 0x00000300UL
#define VPMPC_RMCM_3DLUT_MODE__VPMPC_RMCM_3DLUT_SELECT_CURRENT_MASK 0x00000400UL

// VPMPC_RMCM_3DLUT_INDEX
#define VPMPC_RMCM_3DLUT_INDEX__VPMPC_RMCM_3DLUT_INDEX_MASK 0x00003fffUL

// VPMPC_RMCM_3DLUT_DATA
#define VPMPC_RMCM_3DLUT_DATA__VPMPC_RMCM_3DLUT_DATA0_MASK 0x0000ffffUL
#define VPMPC_RMCM_3DLUT_DATA__VPMPC_RMCM_3DLUT_DATA1_MASK 0xffff0000UL

// VPMPC_RMCM_3DLUT_DATA_30BIT
#define VPMPC_RMCM_3DLUT_DATA_30BIT__VPMPC_RMCM_3DLUT_DATA_30BIT_MASK 0xfffffffcUL

// VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL
#define VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL__VPMPC_RMCM_3DLUT_WRITE_EN_MASK_MASK 0x0000000fUL
#define VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL__VPMPC_RMCM_3DLUT_RAM_SEL_MASK 0x00000010UL
#define VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL__VPMPC_RMCM_3DLUT_30BIT_EN_MASK 0x00000100UL
#define VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL__VPMPC_RMCM_3DLUT_READ_SEL_MASK 0x00030000UL

// VPMPC_RMCM_3DLUT_OUT_NORM_FACTOR
#define VPMPC_RMCM_3DLUT_OUT_NORM_FACTOR__VPMPC_RMCM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000ffffUL

// VPMPC_RMCM_3DLUT_OUT_OFFSET_R
#define VPMPC_RMCM_3DLUT_OUT_OFFSET_R__VPMPC_RMCM_3DLUT_OUT_OFFSET_R_MASK 0x0000ffffUL
#define VPMPC_RMCM_3DLUT_OUT_OFFSET_R__VPMPC_RMCM_3DLUT_OUT_SCALE_R_MASK 0xffff0000UL

// VPMPC_RMCM_3DLUT_OUT_OFFSET_G
#define VPMPC_RMCM_3DLUT_OUT_OFFSET_G__VPMPC_RMCM_3DLUT_OUT_OFFSET_G_MASK 0x0000ffffUL
#define VPMPC_RMCM_3DLUT_OUT_OFFSET_G__VPMPC_RMCM_3DLUT_OUT_SCALE_G_MASK 0xffff0000UL

// VPMPC_RMCM_3DLUT_OUT_OFFSET_B
#define VPMPC_RMCM_3DLUT_OUT_OFFSET_B__VPMPC_RMCM_3DLUT_OUT_OFFSET_B_MASK 0x0000ffffUL
#define VPMPC_RMCM_3DLUT_OUT_OFFSET_B__VPMPC_RMCM_3DLUT_OUT_SCALE_B_MASK 0xffff0000UL

// VPMPC_RMCM_GAMUT_REMAP_COEF_FORMAT
#define VPMPC_RMCM_GAMUT_REMAP_COEF_FORMAT__VPMPC_RMCM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001UL

// VPMPC_RMCM_GAMUT_REMAP_MODE
#define VPMPC_RMCM_GAMUT_REMAP_MODE__VPMPC_RMCM_GAMUT_REMAP_MODE_MASK 0x00000003UL
#define VPMPC_RMCM_GAMUT_REMAP_MODE__VPMPC_RMCM_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180UL

// VPMPC_RMCM_GAMUT_REMAP_C11_C12_SETA
#define VPMPC_RMCM_GAMUT_REMAP_C11_C12_SETA__VPMPC_RMCM_GAMUT_REMAP_C11_SETA_MASK 0x0000ffffUL
#define VPMPC_RMCM_GAMUT_REMAP_C11_C12_SETA__VPMPC_RMCM_GAMUT_REMAP_C12_SETA_MASK 0xffff0000UL

// VPMPC_RMCM_GAMUT_REMAP_C13_C14_SETA
#define VPMPC_RMCM_GAMUT_REMAP_C13_C14_SETA__VPMPC_RMCM_GAMUT_REMAP_C13_SETA_MASK 0x0000ffffUL
#define VPMPC_RMCM_GAMUT_REMAP_C13_C14_SETA__VPMPC_RMCM_GAMUT_REMAP_C14_SETA_MASK 0xffff0000UL

// VPMPC_RMCM_GAMUT_REMAP_C21_C22_SETA
#define VPMPC_RMCM_GAMUT_REMAP_C21_C22_SETA__VPMPC_RMCM_GAMUT_REMAP_C21_SETA_MASK 0x0000ffffUL
#define VPMPC_RMCM_GAMUT_REMAP_C21_C22_SETA__VPMPC_RMCM_GAMUT_REMAP_C22_SETA_MASK 0xffff0000UL

// VPMPC_RMCM_GAMUT_REMAP_C23_C24_SETA
#define VPMPC_RMCM_GAMUT_REMAP_C23_C24_SETA__VPMPC_RMCM_GAMUT_REMAP_C23_SETA_MASK 0x0000ffffUL
#define VPMPC_RMCM_GAMUT_REMAP_C23_C24_SETA__VPMPC_RMCM_GAMUT_REMAP_C24_SETA_MASK 0xffff0000UL

// VPMPC_RMCM_GAMUT_REMAP_C31_C32_SETA
#define VPMPC_RMCM_GAMUT_REMAP_C31_C32_SETA__VPMPC_RMCM_GAMUT_REMAP_C31_SETA_MASK 0x0000ffffUL
#define VPMPC_RMCM_GAMUT_REMAP_C31_C32_SETA__VPMPC_RMCM_GAMUT_REMAP_C32_SETA_MASK 0xffff0000UL

// VPMPC_RMCM_GAMUT_REMAP_C33_C34_SETA
#define VPMPC_RMCM_GAMUT_REMAP_C33_C34_SETA__VPMPC_RMCM_GAMUT_REMAP_C33_SETA_MASK 0x0000ffffUL
#define VPMPC_RMCM_GAMUT_REMAP_C33_C34_SETA__VPMPC_RMCM_GAMUT_REMAP_C34_SETA_MASK 0xffff0000UL

// VPMPC_RMCM_MEM_PWR_CTRL
#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_SHAPER_MEM_PWR_FORCE_MASK 0x00000003UL
#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_SHAPER_MEM_PWR_DIS_MASK 0x00000004UL
#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_SHAPER_MEM_LOW_PWR_MODE_MASK 0x00000030UL
#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_3DLUT_MEM_PWR_FORCE_MASK 0x00000300UL
#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_3DLUT_MEM_PWR_DIS_MASK 0x00000400UL
#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_3DLUT_MEM_LOW_PWR_MODE_MASK 0x00003000UL
#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_SHAPER_MEM_PWR_STATE_MASK 0x03000000UL
#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_3DLUT_MEM_PWR_STATE_MASK 0x0c000000UL

// VPMPC_RMCM_3DLUT_FAST_LOAD_SELECT
#define VPMPC_RMCM_3DLUT_FAST_LOAD_SELECT__VPMPC_RMCM_3DLUT_FL_SEL_MASK 0x0000000fUL

// VPMPC_RMCM_CNTL
#define VPMPC_RMCM_CNTL__VPMPC_RMCM_CNTL_MASK              0x0000000fUL

// VPFMT_CLAMP_COMPONENT_R
#define VPFMT_CLAMP_COMPONENT_R__VPFMT_CLAMP_LOWER_R_MASK  0x0000ffffUL
#define VPFMT_CLAMP_COMPONENT_R__VPFMT_CLAMP_UPPER_R_MASK  0xffff0000UL

// VPFMT_CLAMP_COMPONENT_G
#define VPFMT_CLAMP_COMPONENT_G__VPFMT_CLAMP_LOWER_G_MASK  0x0000ffffUL
#define VPFMT_CLAMP_COMPONENT_G__VPFMT_CLAMP_UPPER_G_MASK  0xffff0000UL

// VPFMT_CLAMP_COMPONENT_B
#define VPFMT_CLAMP_COMPONENT_B__VPFMT_CLAMP_LOWER_B_MASK  0x0000ffffUL
#define VPFMT_CLAMP_COMPONENT_B__VPFMT_CLAMP_UPPER_B_MASK  0xffff0000UL

// VPFMT_DYNAMIC_EXP_CNTL
#define VPFMT_DYNAMIC_EXP_CNTL__VPFMT_DYNAMIC_EXP_EN_MASK  0x00000001UL
#define VPFMT_DYNAMIC_EXP_CNTL__VPFMT_DYNAMIC_EXP_MODE_MASK 0x00000010UL

// VPFMT_CONTROL
#define VPFMT_CONTROL__VPFMT_PIXEL_ENCODING_MASK           0x00000003UL
#define VPFMT_CONTROL__VPFMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00000010UL
#define VPFMT_CONTROL__VPFMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000f00UL
#define VPFMT_CONTROL__VPFMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000UL
#define VPFMT_CONTROL__VPFMT_SUBSAMPLE_HTAPS_MASK          0x00030000UL
#define VPFMT_CONTROL__VPFMT_SUBSAMPLE_LEFT_EDGE_MASK      0x00040000UL
#define VPFMT_CONTROL__VPFMT_SUBSAMPLE_RIGHT_EDGE_MASK     0x00080000UL
#define VPFMT_CONTROL__VPFMT_SUBSAMPLE_VTAPS_MASK          0x00300000UL
#define VPFMT_CONTROL__VPFMT_SUBSAMPLE_TOP_EDGE_MASK       0x00400000UL
#define VPFMT_CONTROL__VPFMT_SUBSAMPLE_BOTTOM_EDGE_MASK    0x00800000UL
#define VPFMT_CONTROL__VPFMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000UL

// VPFMT_BIT_DEPTH_CONTROL
#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_TRUNCATE_EN_MASK    0x00000001UL
#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_TRUNCATE_MODE_MASK  0x00000002UL
#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_TRUNCATE_DEPTH_MASK 0x00000030UL
#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_SPATIAL_DITHER_EN_MASK 0x00000100UL
#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_SPATIAL_DITHER_MODE_MASK 0x00000600UL
#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800UL
#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_FRAME_RANDOM_ENABLE_MASK 0x00002000UL
#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_RGB_RANDOM_ENABLE_MASK 0x00004000UL
#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000UL

// VPFMT_DITHER_RAND_R_SEED
#define VPFMT_DITHER_RAND_R_SEED__VPFMT_RAND_R_SEED_MASK   0x000000ffUL
#define VPFMT_DITHER_RAND_R_SEED__VPFMT_OFFSET_R_CR_MASK   0xffff0000UL

// VPFMT_DITHER_RAND_G_SEED
#define VPFMT_DITHER_RAND_G_SEED__VPFMT_RAND_G_SEED_MASK   0x000000ffUL
#define VPFMT_DITHER_RAND_G_SEED__VPFMT_OFFSET_G_Y_MASK    0xffff0000UL

// VPFMT_DITHER_RAND_B_SEED
#define VPFMT_DITHER_RAND_B_SEED__VPFMT_RAND_B_SEED_MASK   0x000000ffUL
#define VPFMT_DITHER_RAND_B_SEED__VPFMT_OFFSET_B_CB_MASK   0xffff0000UL

// VPFMT_CLAMP_CNTL
#define VPFMT_CLAMP_CNTL__VPFMT_CLAMP_DATA_EN_MASK         0x00000001UL
#define VPFMT_CLAMP_CNTL__VPFMT_CLAMP_COLOR_FORMAT_MASK    0x00070000UL

// VPFMT_SUBSAMPLER_MEMORY_CONTROL
#define VPFMT_SUBSAMPLER_MEMORY_CONTROL__VPFMT_SUBSAMPLER_MEM_PWR_FORCE_MASK 0x00000003UL
#define VPFMT_SUBSAMPLER_MEMORY_CONTROL__VPFMT_SUBSAMPLER_MEM_PWR_DIS_MASK 0x00000010UL
#define VPFMT_SUBSAMPLER_MEMORY_CONTROL__VPFMT_SUBSAMPLER_MEM_PWR_STATE_MASK 0x00000300UL
#define VPFMT_SUBSAMPLER_MEMORY_CONTROL__VPFMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000UL

// VPOPP_PIPE_CONTROL
#define VPOPP_PIPE_CONTROL__VPOPP_PIPE_CLOCK_ON_MASK       0x00000002UL
#define VPOPP_PIPE_CONTROL__VPOPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010UL
#define VPOPP_PIPE_CONTROL__VPOPP_PIPE_ALPHA_SEL_MASK      0x00000020UL
#define VPOPP_PIPE_CONTROL__VPOPP_PIPE_ALPHA_MASK          0xffff0000UL

// VPOPP_PIPE_OUTBG_EXT1
#define VPOPP_PIPE_OUTBG_EXT1__OUTBG_EXT_TOP_MASK          0x00003fffUL
#define VPOPP_PIPE_OUTBG_EXT1__OUTBG_EXT_BOT_MASK          0x0fffc000UL

// VPOPP_PIPE_OUTBG_EXT2
#define VPOPP_PIPE_OUTBG_EXT2__OUTBG_EXT_LEFT_MASK         0x000007ffUL
#define VPOPP_PIPE_OUTBG_EXT2__OUTBG_EXT_RIGHT_MASK        0x003ff800UL

// VPOPP_PIPE_OUTBG_COL1
#define VPOPP_PIPE_OUTBG_COL1__OUTBG_R_CR_MASK             0x0000ffffUL
#define VPOPP_PIPE_OUTBG_COL1__OUTBG_B_CB_MASK             0xffff0000UL

// VPOPP_PIPE_OUTBG_COL2
#define VPOPP_PIPE_OUTBG_COL2__OUTBG_Y_MASK                0x0000ffffUL

// VPOPP_TOP_CLK_CONTROL
#define VPOPP_TOP_CLK_CONTROL__VPOPP_VPECLK_R_GATE_DIS_MASK 0x00000001UL
#define VPOPP_TOP_CLK_CONTROL__VPOPP_VPECLK_G_GATE_DIS_MASK 0x00000002UL

// VPOPP_CRC_CONTROL
#define VPOPP_CRC_CONTROL__VPOPP_CRC_EN_MASK               0x00000001UL
#define VPOPP_CRC_CONTROL__VPOPP_CRC_CONT_EN_MASK          0x00000002UL
#define VPOPP_CRC_CONTROL__VPOPP_CRC_PIXEL_SELECT_MASK     0x0000000cUL
#define VPOPP_CRC_CONTROL__VPOPP_CRC_SOURCE_SELECT_MASK    0x00000030UL
#define VPOPP_CRC_CONTROL__VPOPP_CRC_PIPE_SELECT_MASK      0x00000040UL
#define VPOPP_CRC_CONTROL__VPOPP_CRC_MASK_MASK             0x00ffff00UL
#define VPOPP_CRC_CONTROL__VPOPP_CRC_ONE_SHOT_PENDING_MASK 0x80000000UL

// VPOPP_CRC_RESULT_RG
#define VPOPP_CRC_RESULT_RG__VPOPP_CRC_RESULT_R_MASK       0x0000ffffUL
#define VPOPP_CRC_RESULT_RG__VPOPP_CRC_RESULT_G_MASK       0xffff0000UL

// VPOPP_CRC_RESULT_BC
#define VPOPP_CRC_RESULT_BC__VPOPP_CRC_RESULT_B_MASK       0x0000ffffUL
#define VPOPP_CRC_RESULT_BC__VPOPP_CRC_RESULT_C_MASK       0xffff0000UL

// VPOPP_FROD_CONTROL
#define VPOPP_FROD_CONTROL__FROD_EN_MASK                   0x00000001UL

// VPOPP_FROD_MEM_PWR_CONTROL
#define VPOPP_FROD_MEM_PWR_CONTROL__FROD_MEM_PWR_FORCE_MASK 0x00000003UL
#define VPOPP_FROD_MEM_PWR_CONTROL__FROD_MEM_PWR_DIS_MASK  0x00000010UL
#define VPOPP_FROD_MEM_PWR_CONTROL__FROD_MEM_PWR_STATE_MASK 0x00000300UL
#define VPOPP_FROD_MEM_PWR_CONTROL__FROD_MEM_DEFAULT_LOW_PWR_STATE_MASK 0x00003000UL

#endif
