/* Copyright 2024 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#ifndef _vpe20_MASK_HEADER
#define _vpe20_MASK_HEADER

// VPEC_DEC_START
#define VPEC_DEC_START__START_MASK                         0xffffffffUL

// VPEC_UCODE_ADDR
#define VPEC_UCODE_ADDR__VALUE_MASK                        0x00001fffUL
#define VPEC_UCODE_ADDR__THID_MASK                         0x00008000UL

// VPEC_UCODE_DATA
#define VPEC_UCODE_DATA__VALUE_MASK                        0xffffffffUL

// VPEC_F32_CNTL
#define VPEC_F32_CNTL__HALT_MASK                           0x00000001UL
#define VPEC_F32_CNTL__DBG_SELECT_BITS_MASK                0x000000fcUL
#define VPEC_F32_CNTL__TH0_CHECKSUM_CLR_MASK               0x00000100UL
#define VPEC_F32_CNTL__TH0_RESET_MASK                      0x00000200UL
#define VPEC_F32_CNTL__TH0_ENABLE_MASK                     0x00000400UL
#define VPEC_F32_CNTL__TH1_CHECKSUM_CLR_MASK               0x00001000UL
#define VPEC_F32_CNTL__TH1_RESET_MASK                      0x00002000UL
#define VPEC_F32_CNTL__TH1_ENABLE_MASK                     0x00004000UL
#define VPEC_F32_CNTL__TH0_PRIORITY_MASK                   0x00ff0000UL
#define VPEC_F32_CNTL__TH1_PRIORITY_MASK                   0xff000000UL

// VPEC_MMHUB_CNTL
#define VPEC_MMHUB_CNTL__UNIT_ID_MASK                      0x0000003fUL

// VPEC_MMHUB_TRUSTLVL
#define VPEC_MMHUB_TRUSTLVL__SECLVL0_MASK                  0x0000000fUL
#define VPEC_MMHUB_TRUSTLVL__SECLVL1_MASK                  0x000000f0UL
#define VPEC_MMHUB_TRUSTLVL__SECLVL2_MASK                  0x00000f00UL
#define VPEC_MMHUB_TRUSTLVL__SECLVL3_MASK                  0x0000f000UL
#define VPEC_MMHUB_TRUSTLVL__SECLVL4_MASK                  0x000f0000UL
#define VPEC_MMHUB_TRUSTLVL__SECLVL5_MASK                  0x00f00000UL
#define VPEC_MMHUB_TRUSTLVL__SECLVL6_MASK                  0x0f000000UL
#define VPEC_MMHUB_TRUSTLVL__SECLVL7_MASK                  0xf0000000UL

// VPEC_VPEP_CTRL
#define VPEC_VPEP_CTRL__VPEP_SOCCLK_EN_MASK                0x00000001UL
#define VPEC_VPEP_CTRL__VPEP_SW_RESETB_MASK                0x00000002UL
#define VPEC_VPEP_CTRL__RESERVED_MASK                      0x003ffffcUL
#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S0P0_MASK    0x00400000UL
#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S0P1_MASK    0x00800000UL
#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S0P2_MASK    0x01000000UL
#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S1P0_MASK    0x02000000UL
#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S1P1_MASK    0x04000000UL
#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S1P2_MASK    0x08000000UL
#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_3DLUT_MASK   0x10000000UL
#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPEC_VPEP_REG_FGCLKEN_MASK 0x20000000UL
#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPEP_SOCCLK_MASK     0x40000000UL
#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPECLK_MASK          0x80000000UL

// VPEC_CLK_CTRL
#define VPEC_CLK_CTRL__VPECLK_EN_MASK                      0x00000002UL
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE0_CLK_MASK     0x00000100UL
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE1_CLK_MASK     0x00000200UL
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE2_CLK_MASK     0x00000400UL
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE3_CLK_MASK     0x00000800UL
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE4_CLK_MASK     0x00001000UL
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE5_CLK_MASK     0x00002000UL
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE0_CLK_MASK     0x00010000UL
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE1_CLK_MASK     0x00020000UL
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE2_CLK_MASK     0x00040000UL
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE3_CLK_MASK     0x00080000UL
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE4_CLK_MASK     0x00100000UL
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE5_CLK_MASK     0x00200000UL
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE6_CLK_MASK     0x00400000UL
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE7_CLK_MASK     0x00800000UL
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE8_CLK_MASK     0x01000000UL
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE9_CLK_MASK     0x02000000UL
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_PERF_CLK_MASK         0x08000000UL
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_CE_CLK_MASK           0x10000000UL
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_F32_CLK_MASK          0x20000000UL
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_DYN_CLK_MASK          0x40000000UL
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_REG_CLK_MASK          0x80000000UL

// VPEC_COLLABORATE_CNTL
#define VPEC_COLLABORATE_CNTL__COLLABORATE_MODE_EN_MASK    0x00000001UL

// VPEC_COLLABORATE_CFG
#define VPEC_COLLABORATE_CFG__MASTER_ID_MASK               0x00000007UL
#define VPEC_COLLABORATE_CFG__MASTER_EN_MASK               0x00000008UL
#define VPEC_COLLABORATE_CFG__SLAVE0_ID_MASK               0x00000070UL
#define VPEC_COLLABORATE_CFG__SLAVE0_EN_MASK               0x00000080UL

// VPEC_POWER_CNTL
#define VPEC_POWER_CNTL__LS_ENABLE_MASK                    0x00000001UL
#define VPEC_POWER_CNTL__UCODE_SRAM_DS_EN_MASK             0x00000002UL
#define VPEC_POWER_CNTL__FISO_MASK                         0x00000004UL
#define VPEC_POWER_CNTL__UCODE_SRAM_POWER_UP_RECOVER_DELAY_MASK 0x00007f00UL
#define VPEC_POWER_CNTL__UCODE_SRAM_POWER_STATUS_CHANGE_WAKEUP_TIME_MASK 0x00038000UL
#define VPEC_POWER_CNTL__UCODE_SRAM_POWER_STATUS_CHANGE_CLK_FORCE_MASK 0x00040000UL
#define VPEC_POWER_CNTL__SRAM_POWER_LS_CHANGE_DELAY_MASK   0x00700000UL
#define VPEC_POWER_CNTL__SRAM_POWER_LS_CHANGE_CLK_FORCE_MASK 0x00800000UL
#define VPEC_POWER_CNTL__SRAM_POWER_LS_CHANGE_CLK_FORCE_DELAY_MASK 0x03000000UL

// VPEC_ZPR_CNTL
#define VPEC_ZPR_CNTL__CLK_UNGATE_DELAY_MASK               0x000000ffUL
#define VPEC_ZPR_CNTL__RESERVED_MASK                       0xffffff00UL

// VPEC_CNTL
#define VPEC_CNTL__TRAP_ENABLE_MASK                        0x00000001UL
#define VPEC_CNTL__RESERVED_2_2_MASK                       0x00000004UL
#define VPEC_CNTL__DATA_SWAP_MASK                          0x00000018UL
#define VPEC_CNTL__FENCE_SWAP_ENABLE_MASK                  0x00000020UL
#define VPEC_CNTL__MIDCMD_PREEMPT_ENABLE_MASK              0x00000040UL
#define VPEC_CNTL__MIDCMD_EXPIRE_ENABLE_MASK               0x00000200UL
#define VPEC_CNTL__UMSCH_INT_ENABLE_MASK                   0x00000400UL
#define VPEC_CNTL__RESERVED_13_11_MASK                     0x00003800UL
#define VPEC_CNTL__NACK_GEN_ERR_INT_ENABLE_MASK            0x00004000UL
#define VPEC_CNTL__NACK_PRT_INT_ENABLE_MASK                0x00008000UL
#define VPEC_CNTL__RESERVED_16_16_MASK                     0x00010000UL
#define VPEC_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK          0x00020000UL
#define VPEC_CNTL__RESERVED_19_19_MASK                     0x00080000UL
#define VPEC_CNTL__CTXEMPTY_INT_ENABLE_MASK                0x10000000UL
#define VPEC_CNTL__FROZEN_INT_ENABLE_MASK                  0x20000000UL
#define VPEC_CNTL__IB_PREEMPT_INT_ENABLE_MASK              0x40000000UL
#define VPEC_CNTL__RB_PREEMPT_INT_ENABLE_MASK              0x80000000UL

// VPEC_CNTL_DCC
#define VPEC_CNTL_DCC__WDCC_COMP_MODE_MASK                 0x00000003UL
#define VPEC_CNTL_DCC__RESERVED_3_2_MASK                   0x0000000cUL
#define VPEC_CNTL_DCC__WDCC_MICRO_TILE_MODE_MASK           0x00000030UL
#define VPEC_CNTL_DCC__RESERVED_7_6_MASK                   0x000000c0UL
#define VPEC_CNTL_DCC__WDCC_DATA_FORMAT_MASK               0x00001f00UL
#define VPEC_CNTL_DCC__RESERVED_15_13_MASK                 0x0000e000UL
#define VPEC_CNTL_DCC__WDCC_NUM_FORMAT_EN_MASK             0x00010000UL
#define VPEC_CNTL_DCC__RESERVED_19_17_MASK                 0x000e0000UL
#define VPEC_CNTL_DCC__WDCC_NUM_TYPE_MASK                  0x00700000UL
#define VPEC_CNTL_DCC__RESERVED_23_23_MASK                 0x00800000UL
#define VPEC_CNTL_DCC__WDCC_MAX_UNCOMP_SIZE_MASK           0x01000000UL
#define VPEC_CNTL_DCC__WDCC_MAX_COMP_SIZE_MASK             0x06000000UL
#define VPEC_CNTL_DCC__RESERVED_30_27_MASK                 0x78000000UL
#define VPEC_CNTL_DCC__RDCC_COMP_MODE_MASK                 0x80000000UL

// VPEC_CE_OP_MULTI_64B_BURST
#define VPEC_CE_OP_MULTI_64B_BURST__EN_MASK                0x00000001UL
#define VPEC_CE_OP_MULTI_64B_BURST__RESERVED_3_1_MASK      0x0000000eUL
#define VPEC_CE_OP_MULTI_64B_BURST__LAZY_TIMER_DLY_MASK    0x000003f0UL
#define VPEC_CE_OP_MULTI_64B_BURST__NUM_64B_BURST_ALLOWED_MASK 0x00000c00UL
#define VPEC_CE_OP_MULTI_64B_BURST__RESERVED_31_12_MASK    0xfffff000UL

// VPEC_CNTL1
#define VPEC_CNTL1__RESERVED_3_1_MASK                      0x0000000eUL
#define VPEC_CNTL1__SRBM_POLL_RETRYING_MASK                0x00000020UL
#define VPEC_CNTL1__RESERVED_23_10_MASK                    0x00fffc00UL
#define VPEC_CNTL1__CG_STATUS_OUTPUT_MASK                  0x01000000UL
#define VPEC_CNTL1__SW_FREEZE_ENABLE_MASK                  0x02000000UL
#define VPEC_CNTL1__VPEP_CONFIG_INVALID_CHECK_ENABLE_MASK  0x04000000UL
#define VPEC_CNTL1__RSMU_ACCESS_OFF_VPEP_RETURN_ERROR_ENABLE_MASK 0x08000000UL
#define VPEC_CNTL1__RSMU_ACCESS_OFF_VPEP_REPORT_ERROR_ENABLE_MASK 0x10000000UL
#define VPEC_CNTL1__RESERVED_MASK                          0xe0000000UL

// VPEC_CNTL2
#define VPEC_CNTL2__F32_CMD_PROC_DELAY_MASK                0x0000000fUL
#define VPEC_CNTL2__F32_SEND_POSTCODE_EN_MASK              0x00000010UL
#define VPEC_CNTL2__UCODE_BUF_DS_EN_MASK                   0x00000040UL
#define VPEC_CNTL2__UCODE_SELFLOAD_THREAD_OVERLAP_MASK     0x00000080UL
#define VPEC_CNTL2__LUTIB_FIFO_WATERMARK_MASK              0x00000300UL
#define VPEC_CNTL2__CMDIB_FIFO_WATERMARK_MASK              0x00000c00UL
#define VPEC_CNTL2__RESERVED_14_12_MASK                    0x00007000UL
#define VPEC_CNTL2__IMPROVE_CE_IP_ARBITER_MASK             0x00008000UL
#define VPEC_CNTL2__RB_FIFO_WATERMARK_MASK                 0x00030000UL
#define VPEC_CNTL2__IB_FIFO_WATERMARK_MASK                 0x000c0000UL
#define VPEC_CNTL2__RESERVED_22_20_MASK                    0x00700000UL
#define VPEC_CNTL2__CH_RD_WATERMARK_MASK                   0x01800000UL
#define VPEC_CNTL2__CH_WR_WATERMARK_MASK                   0x3e000000UL
#define VPEC_CNTL2__CH_WR_WATERMARK_LSB_MASK               0x40000000UL

// VPEC_GB_ADDR_CONFIG
#define VPEC_GB_ADDR_CONFIG__NUM_PIPES_MASK                0x00000007UL
#define VPEC_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK     0x00000038UL
#define VPEC_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK     0x000000c0UL
#define VPEC_GB_ADDR_CONFIG__NUM_PKRS_MASK                 0x00000700UL
#define VPEC_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK       0x00180000UL
#define VPEC_GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK            0x0c000000UL

// VPEC_GB_ADDR_CONFIG_READ
#define VPEC_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK           0x00000007UL
#define VPEC_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038UL
#define VPEC_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000c0UL
#define VPEC_GB_ADDR_CONFIG_READ__NUM_PKRS_MASK            0x00000700UL
#define VPEC_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK  0x00180000UL
#define VPEC_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK       0x0c000000UL

// VPEC_GB_ADDR_CONFIG_META
#define VPEC_GB_ADDR_CONFIG_META__NUM_PIPES_MASK           0x00000007UL
#define VPEC_GB_ADDR_CONFIG_META__PIPE_INTERLEAVE_SIZE_MASK 0x00000038UL
#define VPEC_GB_ADDR_CONFIG_META__MAX_COMPRESSED_FRAGS_MASK 0x000000c0UL
#define VPEC_GB_ADDR_CONFIG_META__NUM_PKRS_MASK            0x00000700UL
#define VPEC_GB_ADDR_CONFIG_META__NUM_SHADER_ENGINES_MASK  0x00180000UL
#define VPEC_GB_ADDR_CONFIG_META__NUM_RB_PER_SE_MASK       0x0c000000UL

// VPEC_PROCESS_QUANTUM0
#define VPEC_PROCESS_QUANTUM0__PROCESS0_QUANTUM_MASK       0x000000ffUL
#define VPEC_PROCESS_QUANTUM0__PROCESS1_QUANTUM_MASK       0x0000ff00UL
#define VPEC_PROCESS_QUANTUM0__PROCESS2_QUANTUM_MASK       0x00ff0000UL
#define VPEC_PROCESS_QUANTUM0__PROCESS3_QUANTUM_MASK       0xff000000UL

// VPEC_PROCESS_QUANTUM1
#define VPEC_PROCESS_QUANTUM1__PROCESS4_QUANTUM_MASK       0x000000ffUL
#define VPEC_PROCESS_QUANTUM1__PROCESS5_QUANTUM_MASK       0x0000ff00UL
#define VPEC_PROCESS_QUANTUM1__PROCESS6_QUANTUM_MASK       0x00ff0000UL
#define VPEC_PROCESS_QUANTUM1__PROCESS7_QUANTUM_MASK       0xff000000UL

// VPEC_CONTEXT_SWITCH_THRESHOLD
#define VPEC_CONTEXT_SWITCH_THRESHOLD__REALTIME_THRESHOLD_MASK 0x00000003UL
#define VPEC_CONTEXT_SWITCH_THRESHOLD__FOCUS_THRESHOLD_MASK 0x0000000cUL
#define VPEC_CONTEXT_SWITCH_THRESHOLD__NORMAL_THRESHOLD_MASK 0x00000030UL
#define VPEC_CONTEXT_SWITCH_THRESHOLD__IDLE_THRESHOLD_MASK 0x000000c0UL

// VPEC_GLOBAL_QUANTUM
#define VPEC_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM_MASK     0x000000ffUL
#define VPEC_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM_MASK    0x0000ff00UL

// VPEC_HWE_MASK
#define VPEC_HWE_MASK__HWE_MASK_MASK                       0x0000ffffUL

// VPEC_HWE_SRC_DST_TABLE0
#define VPEC_HWE_SRC_DST_TABLE0__TABLE0_MASK               0xffffffffUL

// VPEC_HWE_SRC_DST_TABLE1
#define VPEC_HWE_SRC_DST_TABLE1__TABLE1_MASK               0xffffffffUL

// VPEC_WATCHDOG_CNTL
#define VPEC_WATCHDOG_CNTL__QUEUE_HANG_COUNT_MASK          0x000000ffUL
#define VPEC_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT_MASK         0x0000ff00UL

// VPEC_ATOMIC_CNTL
#define VPEC_ATOMIC_CNTL__LOOP_TIMER_MASK                  0x7fffffffUL
#define VPEC_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK       0x80000000UL

// VPEC_UCODE_VERSION
#define VPEC_UCODE_VERSION__T0_UCODE_VERSION_MASK          0x0000ffffUL
#define VPEC_UCODE_VERSION__T1_UCODE_VERSION_MASK          0xffff0000UL

// VPEC_MEMREQ_BURST_CNTL
#define VPEC_MEMREQ_BURST_CNTL__DATA_RD_BURST_MASK         0x00000003UL
#define VPEC_MEMREQ_BURST_CNTL__DATA_WR_BURST_MASK         0x0000000cUL
#define VPEC_MEMREQ_BURST_CNTL__RB_RD_BURST_MASK           0x00000030UL
#define VPEC_MEMREQ_BURST_CNTL__IB_RD_BURST_MASK           0x000000c0UL
#define VPEC_MEMREQ_BURST_CNTL__WR_BURST_WAIT_CYCLE_MASK   0x00000700UL

// VPEC_TIMESTAMP_CNTL
#define VPEC_TIMESTAMP_CNTL__CAPTURE_MASK                  0x00000001UL

// VPEC_GLOBAL_TIMESTAMP_LO
#define VPEC_GLOBAL_TIMESTAMP_LO__DATA_MASK                0xffffffffUL

// VPEC_GLOBAL_TIMESTAMP_HI
#define VPEC_GLOBAL_TIMESTAMP_HI__DATA_MASK                0xffffffffUL

// VPEC_FREEZE
#define VPEC_FREEZE__PREEMPT_MASK                          0x00000001UL
#define VPEC_FREEZE__FREEZE_MASK                           0x00000010UL
#define VPEC_FREEZE__FROZEN_MASK                           0x00000020UL
#define VPEC_FREEZE__F32_FREEZE_MASK                       0x00000040UL

// VPEC_CE_CTRL
#define VPEC_CE_CTRL__RD_LUT_WATERMARK_MASK                0x00000007UL
#define VPEC_CE_CTRL__RD_LUT_DEPTH_MASK                    0x00000018UL
#define VPEC_CE_CTRL__WR_AFIFO_WATERMARK_MASK              0x000000e0UL
#define VPEC_CE_CTRL__RESERVED_MASK                        0xffffff00UL

// VPEC_RELAX_ORDERING_LUT
#define VPEC_RELAX_ORDERING_LUT__RESERVED0_MASK            0x00000001UL
#define VPEC_RELAX_ORDERING_LUT__VPE_MASK                  0x00000002UL
#define VPEC_RELAX_ORDERING_LUT__RESERVED_2_2_MASK         0x00000004UL
#define VPEC_RELAX_ORDERING_LUT__RESERVED3_MASK            0x00000008UL
#define VPEC_RELAX_ORDERING_LUT__RESERVED4_MASK            0x00000010UL
#define VPEC_RELAX_ORDERING_LUT__FENCE_MASK                0x00000020UL
#define VPEC_RELAX_ORDERING_LUT__RESERVED76_MASK           0x000000c0UL
#define VPEC_RELAX_ORDERING_LUT__POLL_MEM_MASK             0x00000100UL
#define VPEC_RELAX_ORDERING_LUT__COND_EXE_MASK             0x00000200UL
#define VPEC_RELAX_ORDERING_LUT__ATOMIC_MASK               0x00000400UL
#define VPEC_RELAX_ORDERING_LUT__RESERVED_11_11_MASK       0x00000800UL
#define VPEC_RELAX_ORDERING_LUT__RESERVED_12_12_MASK       0x00001000UL
#define VPEC_RELAX_ORDERING_LUT__TIMESTAMP_MASK            0x00002000UL
#define VPEC_RELAX_ORDERING_LUT__NATIVE_FENCE_MASK         0x00004000UL
#define VPEC_RELAX_ORDERING_LUT__RESERVED_MASK             0x07ff8000UL
#define VPEC_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK         0x08000000UL
#define VPEC_RELAX_ORDERING_LUT__RPTR_WRB_MASK             0x10000000UL
#define VPEC_RELAX_ORDERING_LUT__RESERVED_29_29_MASK       0x20000000UL
#define VPEC_RELAX_ORDERING_LUT__IB_FETCH_MASK             0x40000000UL
#define VPEC_RELAX_ORDERING_LUT__RB_FETCH_MASK             0x80000000UL

// VPEC_CREDIT_CNTL
#define VPEC_CREDIT_CNTL__DRM_CREDIT_MASK                  0x0000007fUL
#define VPEC_CREDIT_CNTL__MC_WRREQ_CREDIT_MASK             0x00001f80UL
#define VPEC_CREDIT_CNTL__MC_RDREQ_CREDIT_MASK             0x0007e000UL

// VPEC_SCRATCH_RAM_DATA
#define VPEC_SCRATCH_RAM_DATA__DATA_MASK                   0xffffffffUL

// VPEC_SCRATCH_RAM_ADDR
#define VPEC_SCRATCH_RAM_ADDR__ADDR_MASK                   0x000000ffUL

// VPEC_QUEUE_RESET_REQ
#define VPEC_QUEUE_RESET_REQ__QUEUE0_RESET_MASK            0x00000001UL
#define VPEC_QUEUE_RESET_REQ__QUEUE1_RESET_MASK            0x00000002UL
#define VPEC_QUEUE_RESET_REQ__QUEUE2_RESET_MASK            0x00000004UL
#define VPEC_QUEUE_RESET_REQ__QUEUE3_RESET_MASK            0x00000008UL
#define VPEC_QUEUE_RESET_REQ__QUEUE4_RESET_MASK            0x00000010UL
#define VPEC_QUEUE_RESET_REQ__QUEUE5_RESET_MASK            0x00000020UL
#define VPEC_QUEUE_RESET_REQ__QUEUE6_RESET_MASK            0x00000040UL
#define VPEC_QUEUE_RESET_REQ__QUEUE7_RESET_MASK            0x00000080UL
#define VPEC_QUEUE_RESET_REQ__RESERVED_MASK                0xffffff00UL

// VPEC_PERFCNT_PERFCOUNTER0_CFG
#define VPEC_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK       0x000000ffUL
#define VPEC_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK   0x0000ff00UL
#define VPEC_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK      0x0f000000UL
#define VPEC_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK         0x10000000UL
#define VPEC_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK          0x20000000UL

// VPEC_PERFCNT_PERFCOUNTER1_CFG
#define VPEC_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK       0x000000ffUL
#define VPEC_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK   0x0000ff00UL
#define VPEC_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK      0x0f000000UL
#define VPEC_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK         0x10000000UL
#define VPEC_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK          0x20000000UL

// VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL
#define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000fUL
#define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000ff00UL
#define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00ff0000UL
#define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000UL
#define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000UL
#define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000UL

// VPEC_PERFCNT_MISC_CNTL
#define VPEC_PERFCNT_MISC_CNTL__CMD_OP_MASK                0x0000ffffUL
#define VPEC_PERFCNT_MISC_CNTL__MMHUB_REQ_EVENT_SELECT_MASK 0x00010000UL

// VPEC_PERFCNT_PERFCOUNTER_LO
#define VPEC_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK       0xffffffffUL

// VPEC_PERFCNT_PERFCOUNTER_HI
#define VPEC_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK       0x0000ffffUL
#define VPEC_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK    0xffff0000UL

// VPEC_DEBUG_INDEX
#define VPEC_DEBUG_INDEX__INDEX_MASK                       0xffffffffUL

// VPEC_DEBUG_DATA
#define VPEC_DEBUG_DATA__DATA_MASK                         0xffffffffUL

// VPEC_CRC_CNTL
#define VPEC_CRC_CNTL__ENABLE_MASK                         0x00000001UL
#define VPEC_CRC_CNTL__CLEAR_MASK                          0x00000002UL

// VPEC_CRC_INDEX
#define VPEC_CRC_INDEX__PIPE_MASK                          0x0000000fUL
#define VPEC_CRC_INDEX__CRC_NODE_MASK                      0x00000030UL

// VPEC_CRC_DATA0
#define VPEC_CRC_DATA0__DATA_MASK                          0xffffffffUL

// VPEC_CRC_DATA1
#define VPEC_CRC_DATA1__DATA_MASK                          0xffffffffUL

// VPEC_CRC_DATA2
#define VPEC_CRC_DATA2__DATA_MASK                          0x00ffffffUL

// VPEC_MAILBOX0
#define VPEC_MAILBOX0__VALUE_MASK                          0xffffffffUL

// VPEC_MAILBOX1
#define VPEC_MAILBOX1__VALUE_MASK                          0xffffffffUL

// VPEC_MAILBOX2
#define VPEC_MAILBOX2__VALUE_MASK                          0xffffffffUL

// VPEC_MAILBOX3
#define VPEC_MAILBOX3__VALUE_MASK                          0xffffffffUL

// VPEC_MAILBOX4
#define VPEC_MAILBOX4__VALUE_MASK                          0xffffffffUL

// VPEC_MAILBOX5
#define VPEC_MAILBOX5__VALUE_MASK                          0xffffffffUL

// VPEC_MAILBOX6
#define VPEC_MAILBOX6__VALUE_MASK                          0xffffffffUL

// VPEC_MAILBOX7
#define VPEC_MAILBOX7__VALUE_MASK                          0xffffffffUL

// VPEC_MAILBOX8
#define VPEC_MAILBOX8__VALUE_MASK                          0xffffffffUL

// VPEC_MAILBOX9
#define VPEC_MAILBOX9__VALUE_MASK                          0xffffffffUL

// VPEC_MAILBOX10
#define VPEC_MAILBOX10__VALUE_MASK                         0xffffffffUL

// VPEC_MAILBOX11
#define VPEC_MAILBOX11__VALUE_MASK                         0xffffffffUL

// VPEC_MAILBOX12
#define VPEC_MAILBOX12__VALUE_MASK                         0xffffffffUL

// VPEC_MAILBOX13
#define VPEC_MAILBOX13__VALUE_MASK                         0xffffffffUL

// VPEC_MAILBOX14
#define VPEC_MAILBOX14__VALUE_MASK                         0xffffffffUL

// VPEC_MAILBOX15
#define VPEC_MAILBOX15__VALUE_MASK                         0xffffffffUL

// VPEC_PUB_DUMMY0
#define VPEC_PUB_DUMMY0__VALUE_MASK                        0xffffffffUL

// VPEC_PUB_DUMMY1
#define VPEC_PUB_DUMMY1__VALUE_MASK                        0xffffffffUL

// VPEC_PUB_DUMMY2
#define VPEC_PUB_DUMMY2__VALUE_MASK                        0xffffffffUL

// VPEC_PUB_DUMMY3
#define VPEC_PUB_DUMMY3__VALUE_MASK                        0xffffffffUL

// VPEC_PUB_DUMMY4
#define VPEC_PUB_DUMMY4__VALUE_MASK                        0xffffffffUL

// VPEC_PUB_DUMMY5
#define VPEC_PUB_DUMMY5__VALUE_MASK                        0xffffffffUL

// VPEC_PUB_DUMMY6
#define VPEC_PUB_DUMMY6__VALUE_MASK                        0xffffffffUL

// VPEC_PUB_DUMMY7
#define VPEC_PUB_DUMMY7__VALUE_MASK                        0xffffffffUL

// VPEC_PUB_DUMMY8
#define VPEC_PUB_DUMMY8__VALUE_MASK                        0xffffffffUL

// VPEC_PUB_DUMMY9
#define VPEC_PUB_DUMMY9__VALUE_MASK                        0xffffffffUL

// VPEC_PUB_DUMMY10
#define VPEC_PUB_DUMMY10__VALUE_MASK                       0xffffffffUL

// VPEC_PUB_DUMMY11
#define VPEC_PUB_DUMMY11__VALUE_MASK                       0xffffffffUL

// VPEC_UCODE1_CHECKSUM
#define VPEC_UCODE1_CHECKSUM__DATA_MASK                    0xffffffffUL

// VPEC_VERSION
#define VPEC_VERSION__MINVER_MASK                          0x0000007fUL
#define VPEC_VERSION__MAJVER_MASK                          0x00007f00UL
#define VPEC_VERSION__REV_MASK                             0x003f0000UL

// VPEC_UCODE_CHECKSUM
#define VPEC_UCODE_CHECKSUM__DATA_MASK                     0xffffffffUL

// VPEC_RB_RPTR_FETCH
#define VPEC_RB_RPTR_FETCH__OFFSET_MASK                    0xfffffffcUL

// VPEC_RB_RPTR_FETCH_HI
#define VPEC_RB_RPTR_FETCH_HI__OFFSET_MASK                 0xffffffffUL

// VPEC_IB_OFFSET_FETCH
#define VPEC_IB_OFFSET_FETCH__OFFSET_MASK                  0x003ffffcUL

// VPEC_CMDIB_OFFSET_FETCH
#define VPEC_CMDIB_OFFSET_FETCH__OFFSET_MASK               0x003ffffcUL

// VPEC_3DLUTIB_OFFSET_FETCH
#define VPEC_3DLUTIB_OFFSET_FETCH__OFFSET_MASK             0x003ffffcUL

// VPEC_ATOMIC_PREOP_LO
#define VPEC_ATOMIC_PREOP_LO__DATA_MASK                    0xffffffffUL

// VPEC_ATOMIC_PREOP_HI
#define VPEC_ATOMIC_PREOP_HI__DATA_MASK                    0xffffffffUL

// VPEC_CE_BUSY
#define VPEC_CE_BUSY__CE_IP_PIPE0_BUSY_MASK                0x00000001UL
#define VPEC_CE_BUSY__CE_IP_PIPE1_BUSY_MASK                0x00000002UL
#define VPEC_CE_BUSY__CE_IP_PIPE2_BUSY_MASK                0x00000004UL
#define VPEC_CE_BUSY__CE_IP_PIPE3_BUSY_MASK                0x00000008UL
#define VPEC_CE_BUSY__CE_IP_PIPE4_BUSY_MASK                0x00000010UL
#define VPEC_CE_BUSY__CE_IP_PIPE5_BUSY_MASK                0x00000020UL
#define VPEC_CE_BUSY__CE_OP_PIPE0_BUSY_MASK                0x00010000UL
#define VPEC_CE_BUSY__CE_OP_PIPE1_BUSY_MASK                0x00020000UL
#define VPEC_CE_BUSY__CE_OP_PIPE2_BUSY_MASK                0x00040000UL
#define VPEC_CE_BUSY__CE_OP_PIPE3_BUSY_MASK                0x00080000UL
#define VPEC_CE_BUSY__CE_OP_PIPE4_BUSY_MASK                0x00100000UL
#define VPEC_CE_BUSY__CE_OP_PIPE5_BUSY_MASK                0x00200000UL
#define VPEC_CE_BUSY__CE_OP_PIPE6_BUSY_MASK                0x00400000UL
#define VPEC_CE_BUSY__CE_OP_PIPE7_BUSY_MASK                0x00800000UL
#define VPEC_CE_BUSY__CE_OP_PIPE8_BUSY_MASK                0x01000000UL
#define VPEC_CE_BUSY__CE_OP_PIPE9_BUSY_MASK                0x02000000UL

// VPEC_F32_COUNTER
#define VPEC_F32_COUNTER__VALUE_MASK                       0xffffffffUL

// VPEC_HOLE_ADDR_LO
#define VPEC_HOLE_ADDR_LO__VALUE_MASK                      0xffffffffUL

// VPEC_HOLE_ADDR_HI
#define VPEC_HOLE_ADDR_HI__VALUE_MASK                      0xffffffffUL

// VPEC_ERROR_LOG
#define VPEC_ERROR_LOG__OVERRIDE_MASK                      0x0000ffffUL
#define VPEC_ERROR_LOG__STATUS_MASK                        0xffff0000UL

// VPEC_INT_STATUS
#define VPEC_INT_STATUS__DATA_MASK                         0xffffffffUL

// VPEC_STATUS
#define VPEC_STATUS__IDLE_MASK                             0x00000001UL
#define VPEC_STATUS__REG_IDLE_MASK                         0x00000002UL
#define VPEC_STATUS__RB_EMPTY_MASK                         0x00000004UL
#define VPEC_STATUS__RB_FULL_MASK                          0x00000008UL
#define VPEC_STATUS__RB_CMD_IDLE_MASK                      0x00000010UL
#define VPEC_STATUS__RB_CMD_FULL_MASK                      0x00000020UL
#define VPEC_STATUS__IB_CMD_IDLE_MASK                      0x00000040UL
#define VPEC_STATUS__IB_CMD_FULL_MASK                      0x00000080UL
#define VPEC_STATUS__BLOCK_IDLE_MASK                       0x00000100UL
#define VPEC_STATUS__INSIDE_VPEP_CONFIG_MASK               0x00000200UL
#define VPEC_STATUS__EX_IDLE_MASK                          0x00000400UL
#define VPEC_STATUS__INSIDE_VPEP_3DLUT_CONFIG_MASK         0x00000800UL
#define VPEC_STATUS__PACKET_READY_MASK                     0x00001000UL
#define VPEC_STATUS__MC_WR_IDLE_MASK                       0x00002000UL
#define VPEC_STATUS__SRBM_IDLE_MASK                        0x00004000UL
#define VPEC_STATUS__CONTEXT_EMPTY_MASK                    0x00008000UL
#define VPEC_STATUS__INSIDE_IB_MASK                        0x00010000UL
#define VPEC_STATUS__RB_MC_RREQ_IDLE_MASK                  0x00020000UL
#define VPEC_STATUS__IB_MC_RREQ_IDLE_MASK                  0x00040000UL
#define VPEC_STATUS__MC_RD_IDLE_MASK                       0x00080000UL
#define VPEC_STATUS__DELTA_RPTR_EMPTY_MASK                 0x00100000UL
#define VPEC_STATUS__MC_RD_RET_STALL_MASK                  0x00200000UL
#define VPEC_STATUS__LUTIB_CMD_IDLE_MASK                   0x00400000UL
#define VPEC_STATUS__LUTIB_CMD_FULL_MASK                   0x00800000UL
#define VPEC_STATUS__CMDIB_MC_RREQ_IDLE_MASK               0x01000000UL
#define VPEC_STATUS__PREV_CMD_IDLE_MASK                    0x02000000UL
#define VPEC_STATUS__CMDIB_CMD_IDLE_MASK                   0x04000000UL
#define VPEC_STATUS__CMDIB_CMD_FULL_MASK                   0x08000000UL
#define VPEC_STATUS__RESERVED_29_28_MASK                   0x30000000UL
#define VPEC_STATUS__INT_IDLE_MASK                         0x40000000UL
#define VPEC_STATUS__INT_REQ_STALL_MASK                    0x80000000UL

// VPEC_STATUS1
#define VPEC_STATUS1__EX_START_MASK                        0x00000001UL
#define VPEC_STATUS1__VPEC_IDLE_MASK                       0x00000002UL
#define VPEC_STATUS1__RESERVED_31_2_MASK                   0xfffffffcUL

// VPEC_STATUS2
#define VPEC_STATUS2__ID_MASK                              0x00000003UL
#define VPEC_STATUS2__TH0F32_INSTR_PTR_MASK                0x0000fffcUL
#define VPEC_STATUS2__CMD_OP_MASK                          0xffff0000UL

// VPEC_STATUS3
#define VPEC_STATUS3__RESERVED_15_0_MASK                   0x0000ffffUL
#define VPEC_STATUS3__RESERVED_19_16_MASK                  0x000f0000UL
#define VPEC_STATUS3__EXCEPTION_IDLE_MASK                  0x00100000UL
#define VPEC_STATUS3__RESERVED_21_21_MASK                  0x00200000UL
#define VPEC_STATUS3__RESERVED_22_22_MASK                  0x00400000UL
#define VPEC_STATUS3__RESERVED_23_23_MASK                  0x00800000UL
#define VPEC_STATUS3__RESERVED_24_24_MASK                  0x01000000UL
#define VPEC_STATUS3__RESERVED_25_25_MASK                  0x02000000UL
#define VPEC_STATUS3__INT_QUEUE_ID_MASK                    0x3c000000UL
#define VPEC_STATUS3__RESERVED_31_30_MASK                  0xc0000000UL

// VPEC_STATUS4
#define VPEC_STATUS4__IDLE_MASK                            0x00000001UL
#define VPEC_STATUS4__IH_OUTSTANDING_MASK                  0x00000004UL
#define VPEC_STATUS4__RESERVED_3_3_MASK                    0x00000008UL
#define VPEC_STATUS4__CH_RD_OUTSTANDING_MASK               0x00000010UL
#define VPEC_STATUS4__CH_WR_OUTSTANDING_MASK               0x00000020UL
#define VPEC_STATUS4__RESERVED_6_6_MASK                    0x00000040UL
#define VPEC_STATUS4__RESERVED_7_7_MASK                    0x00000080UL
#define VPEC_STATUS4__RESERVED_8_8_MASK                    0x00000100UL
#define VPEC_STATUS4__RESERVED_9_9_MASK                    0x00000200UL
#define VPEC_STATUS4__REG_POLLING_MASK                     0x00000400UL
#define VPEC_STATUS4__MEM_POLLING_MASK                     0x00000800UL
#define VPEC_STATUS4__VPEP_REG_RD_OUTSTANDING_MASK         0x00001000UL
#define VPEC_STATUS4__VPEP_REG_WR_OUTSTANDING_MASK         0x00002000UL
#define VPEC_STATUS4__RESERVED_15_14_MASK                  0x0000c000UL
#define VPEC_STATUS4__ACTIVE_QUEUE_ID_MASK                 0x000f0000UL
#define VPEC_STATUS4__RESERVED_27_20_MASK                  0x0ff00000UL

// VPEC_STATUS5
#define VPEC_STATUS5__QUEUE0_RB_ENABLE_STATUS_MASK         0x00000001UL
#define VPEC_STATUS5__QUEUE1_RB_ENABLE_STATUS_MASK         0x00000002UL
#define VPEC_STATUS5__QUEUE2_RB_ENABLE_STATUS_MASK         0x00000004UL
#define VPEC_STATUS5__QUEUE3_RB_ENABLE_STATUS_MASK         0x00000008UL
#define VPEC_STATUS5__QUEUE4_RB_ENABLE_STATUS_MASK         0x00000010UL
#define VPEC_STATUS5__QUEUE5_RB_ENABLE_STATUS_MASK         0x00000020UL
#define VPEC_STATUS5__QUEUE6_RB_ENABLE_STATUS_MASK         0x00000040UL
#define VPEC_STATUS5__QUEUE7_RB_ENABLE_STATUS_MASK         0x00000080UL
#define VPEC_STATUS5__RESERVED_27_16_MASK                  0x000f0000UL

// VPEC_STATUS6
#define VPEC_STATUS6__ID_MASK                              0x00000003UL
#define VPEC_STATUS6__TH1F32_INSTR_PTR_MASK                0x0000fffcUL
#define VPEC_STATUS6__TH1_EXCEPTION_MASK                   0xffff0000UL

// VPEC_STATUS7
#define VPEC_STATUS7__TH0_DBG_STATUS_MASK                  0xffffffffUL

// VPEC_STATUS8
#define VPEC_STATUS8__CE_IP0_WREQ_IDLE_MASK                0x00000001UL
#define VPEC_STATUS8__CE_IP0_WR_IDLE_MASK                  0x00000002UL
#define VPEC_STATUS8__CE_IP0_SPLIT_RD_IDLE_MASK            0x00000004UL
#define VPEC_STATUS8__CE_IP0_SPLIT_WR_IDLE_MASK            0x00000008UL
#define VPEC_STATUS8__CE_IP0_RREQ_IDLE_MASK                0x00000010UL
#define VPEC_STATUS8__CE_IP0_OUT_IDLE_MASK                 0x00000020UL
#define VPEC_STATUS8__CE_IP0_IN_IDLE_MASK                  0x00000040UL
#define VPEC_STATUS8__CE_IP0_DST_IDLE_MASK                 0x00000080UL
#define VPEC_STATUS8__CE_IP0_CMD_IDLE_MASK                 0x00000100UL
#define VPEC_STATUS8__CE_IP1_WREQ_IDLE_MASK                0x00000200UL
#define VPEC_STATUS8__CE_IP1_WR_IDLE_MASK                  0x00000400UL
#define VPEC_STATUS8__CE_IP1_SPLIT_RD_IDLE_MASK            0x00000800UL
#define VPEC_STATUS8__CE_IP1_SPLIT_WR_IDLE_MASK            0x00001000UL
#define VPEC_STATUS8__CE_IP1_RREQ_IDLE_MASK                0x00002000UL
#define VPEC_STATUS8__CE_IP1_OUT_IDLE_MASK                 0x00004000UL
#define VPEC_STATUS8__CE_IP1_IN_IDLE_MASK                  0x00008000UL
#define VPEC_STATUS8__CE_IP1_DST_IDLE_MASK                 0x00010000UL
#define VPEC_STATUS8__CE_IP1_CMD_IDLE_MASK                 0x00020000UL
#define VPEC_STATUS8__CE_IP0_AFIFO_FULL_MASK               0x00040000UL
#define VPEC_STATUS8__CE_IP0_CMD_INFO_FULL_MASK            0x00080000UL
#define VPEC_STATUS8__CE_IP0_CMD_INFO1_FULL_MASK           0x00100000UL
#define VPEC_STATUS8__CE_IP1_AFIFO_FULL_MASK               0x00200000UL
#define VPEC_STATUS8__CE_IP1_CMD_INFO_FULL_MASK            0x00400000UL
#define VPEC_STATUS8__CE_IP1_CMD_INFO1_FULL_MASK           0x00800000UL
#define VPEC_STATUS8__CE_IP0_WR_STALL_MASK                 0x01000000UL
#define VPEC_STATUS8__CE_IP1_WR_STALL_MASK                 0x02000000UL
#define VPEC_STATUS8__CE_IP0_RD_STALL_MASK                 0x04000000UL
#define VPEC_STATUS8__CE_IP1_RD_STALL_MASK                 0x08000000UL
#define VPEC_STATUS8__RESERVED_31_28_MASK                  0xf0000000UL

// VPEC_STATUS9
#define VPEC_STATUS9__CE_IP2_WREQ_IDLE_MASK                0x00000001UL
#define VPEC_STATUS9__CE_IP2_WR_IDLE_MASK                  0x00000002UL
#define VPEC_STATUS9__CE_IP2_SPLIT_RD_IDLE_MASK            0x00000004UL
#define VPEC_STATUS9__CE_IP2_SPLIT_WR_IDLE_MASK            0x00000008UL
#define VPEC_STATUS9__CE_IP2_RREQ_IDLE_MASK                0x00000010UL
#define VPEC_STATUS9__CE_IP2_OUT_IDLE_MASK                 0x00000020UL
#define VPEC_STATUS9__CE_IP2_IN_IDLE_MASK                  0x00000040UL
#define VPEC_STATUS9__CE_IP2_DST_IDLE_MASK                 0x00000080UL
#define VPEC_STATUS9__CE_IP2_CMD_IDLE_MASK                 0x00000100UL
#define VPEC_STATUS9__CE_IP3_WREQ_IDLE_MASK                0x00000200UL
#define VPEC_STATUS9__CE_IP3_WR_IDLE_MASK                  0x00000400UL
#define VPEC_STATUS9__CE_IP3_SPLIT_RD_IDLE_MASK            0x00000800UL
#define VPEC_STATUS9__CE_IP3_SPLIT_WR_IDLE_MASK            0x00001000UL
#define VPEC_STATUS9__CE_IP3_RREQ_IDLE_MASK                0x00002000UL
#define VPEC_STATUS9__CE_IP3_OUT_IDLE_MASK                 0x00004000UL
#define VPEC_STATUS9__CE_IP3_IN_IDLE_MASK                  0x00008000UL
#define VPEC_STATUS9__CE_IP3_DST_IDLE_MASK                 0x00010000UL
#define VPEC_STATUS9__CE_IP3_CMD_IDLE_MASK                 0x00020000UL
#define VPEC_STATUS9__CE_IP2_AFIFO_FULL_MASK               0x00040000UL
#define VPEC_STATUS9__CE_IP2_CMD_INFO_FULL_MASK            0x00080000UL
#define VPEC_STATUS9__CE_IP2_CMD_INFO1_FULL_MASK           0x00100000UL
#define VPEC_STATUS9__CE_IP3_AFIFO_FULL_MASK               0x00200000UL
#define VPEC_STATUS9__CE_IP3_CMD_INFO_FULL_MASK            0x00400000UL
#define VPEC_STATUS9__CE_IP3_CMD_INFO1_FULL_MASK           0x00800000UL
#define VPEC_STATUS9__CE_IP2_WR_STALL_MASK                 0x01000000UL
#define VPEC_STATUS9__CE_IP3_WR_STALL_MASK                 0x02000000UL
#define VPEC_STATUS9__CE_IP2_RD_STALL_MASK                 0x04000000UL
#define VPEC_STATUS9__CE_IP3_RD_STALL_MASK                 0x08000000UL
#define VPEC_STATUS9__RESERVED_31_28_MASK                  0xf0000000UL

// VPEC_STATUS10
#define VPEC_STATUS10__CE_OP0_WR_IDLE_MASK                 0x00000001UL
#define VPEC_STATUS10__CE_OP0_CMD_IDLE_MASK                0x00000002UL
#define VPEC_STATUS10__CE_OP1_WR_IDLE_MASK                 0x00000004UL
#define VPEC_STATUS10__CE_OP1_CMD_IDLE_MASK                0x00000008UL
#define VPEC_STATUS10__CE_OP2_WR_IDLE_MASK                 0x00000010UL
#define VPEC_STATUS10__CE_OP2_CMD_IDLE_MASK                0x00000020UL
#define VPEC_STATUS10__CE_OP3_WR_IDLE_MASK                 0x00000040UL
#define VPEC_STATUS10__CE_OP3_CMD_IDLE_MASK                0x00000080UL
#define VPEC_STATUS10__CE_OP4_WR_IDLE_MASK                 0x00000100UL
#define VPEC_STATUS10__CE_OP4_CMD_IDLE_MASK                0x00000200UL
#define VPEC_STATUS10__CE_OP5_WR_IDLE_MASK                 0x00000400UL
#define VPEC_STATUS10__CE_OP5_CMD_IDLE_MASK                0x00000800UL
#define VPEC_STATUS10__CE_OP6_WR_IDLE_MASK                 0x00001000UL
#define VPEC_STATUS10__CE_OP6_CMD_IDLE_MASK                0x00002000UL
#define VPEC_STATUS10__CE_OP7_WR_IDLE_MASK                 0x00004000UL
#define VPEC_STATUS10__CE_OP7_CMD_IDLE_MASK                0x00008000UL
#define VPEC_STATUS10__CE_OP8_WR_IDLE_MASK                 0x00010000UL
#define VPEC_STATUS10__CE_OP8_CMD_IDLE_MASK                0x00020000UL
#define VPEC_STATUS10__CE_OP9_WR_IDLE_MASK                 0x00040000UL
#define VPEC_STATUS10__CE_OP9_CMD_IDLE_MASK                0x00080000UL
#define VPEC_STATUS10__RESERVED_31_28_MASK                 0xf0000000UL

// VPEC_STATUS_DCC
#define VPEC_STATUS_DCC__CE_IP0_MRQ_IDLE_MASK              0x00000001UL
#define VPEC_STATUS_DCC__CE_IP0_DCCP_IDLE_MASK             0x00000002UL
#define VPEC_STATUS_DCC__CE_IP0_DCC_RET_IDLE_MASK          0x00000004UL
#define VPEC_STATUS_DCC__CE_IP1_MRQ_IDLE_MASK              0x00000008UL
#define VPEC_STATUS_DCC__CE_IP1_DCCP_IDLE_MASK             0x00000010UL
#define VPEC_STATUS_DCC__CE_IP1_DCC_RET_IDLE_MASK          0x00000020UL
#define VPEC_STATUS_DCC__CE_IP2_MRQ_IDLE_MASK              0x00000040UL
#define VPEC_STATUS_DCC__CE_IP2_DCCP_IDLE_MASK             0x00000080UL
#define VPEC_STATUS_DCC__CE_IP2_DCC_RET_IDLE_MASK          0x00000100UL
#define VPEC_STATUS_DCC__CE_IP3_MRQ_IDLE_MASK              0x00000200UL
#define VPEC_STATUS_DCC__CE_IP3_DCCP_IDLE_MASK             0x00000400UL
#define VPEC_STATUS_DCC__CE_IP3_DCC_RET_IDLE_MASK          0x00000800UL
#define VPEC_STATUS_DCC__CE_IP4_MRQ_IDLE_MASK              0x00001000UL
#define VPEC_STATUS_DCC__CE_IP4_DCCP_IDLE_MASK             0x00002000UL
#define VPEC_STATUS_DCC__CE_IP4_DCC_RET_IDLE_MASK          0x00004000UL
#define VPEC_STATUS_DCC__CE_IP5_MRQ_IDLE_MASK              0x00008000UL
#define VPEC_STATUS_DCC__CE_IP5_DCCP_IDLE_MASK             0x00010000UL
#define VPEC_STATUS_DCC__CE_IP5_DCC_RET_IDLE_MASK          0x00020000UL
#define VPEC_STATUS_DCC__RESERVED_31_18_MASK               0xfffc0000UL

// VPEC_STATUS11
#define VPEC_STATUS11__CE_IP4_WREQ_IDLE_MASK               0x00000001UL
#define VPEC_STATUS11__CE_IP4_WR_IDLE_MASK                 0x00000002UL
#define VPEC_STATUS11__CE_IP4_SPLIT_RD_IDLE_MASK           0x00000004UL
#define VPEC_STATUS11__CE_IP4_SPLIT_WR_IDLE_MASK           0x00000008UL
#define VPEC_STATUS11__CE_IP4_RREQ_IDLE_MASK               0x00000010UL
#define VPEC_STATUS11__CE_IP4_OUT_IDLE_MASK                0x00000020UL
#define VPEC_STATUS11__CE_IP4_IN_IDLE_MASK                 0x00000040UL
#define VPEC_STATUS11__CE_IP4_DST_IDLE_MASK                0x00000080UL
#define VPEC_STATUS11__CE_IP4_CMD_IDLE_MASK                0x00000100UL
#define VPEC_STATUS11__CE_IP5_WREQ_IDLE_MASK               0x00000200UL
#define VPEC_STATUS11__CE_IP5_WR_IDLE_MASK                 0x00000400UL
#define VPEC_STATUS11__CE_IP5_SPLIT_RD_IDLE_MASK           0x00000800UL
#define VPEC_STATUS11__CE_IP5_SPLIT_WR_IDLE_MASK           0x00001000UL
#define VPEC_STATUS11__CE_IP5_RREQ_IDLE_MASK               0x00002000UL
#define VPEC_STATUS11__CE_IP5_OUT_IDLE_MASK                0x00004000UL
#define VPEC_STATUS11__CE_IP5_IN_IDLE_MASK                 0x00008000UL
#define VPEC_STATUS11__CE_IP5_DST_IDLE_MASK                0x00010000UL
#define VPEC_STATUS11__CE_IP5_CMD_IDLE_MASK                0x00020000UL
#define VPEC_STATUS11__CE_IP4_AFIFO_FULL_MASK              0x00040000UL
#define VPEC_STATUS11__CE_IP4_CMD_INFO_FULL_MASK           0x00080000UL
#define VPEC_STATUS11__CE_IP4_CMD_INFO1_FULL_MASK          0x00100000UL
#define VPEC_STATUS11__CE_IP5_AFIFO_FULL_MASK              0x00200000UL
#define VPEC_STATUS11__CE_IP5_CMD_INFO_FULL_MASK           0x00400000UL
#define VPEC_STATUS11__CE_IP5_CMD_INFO1_FULL_MASK          0x00800000UL
#define VPEC_STATUS11__CE_IP4_WR_STALL_MASK                0x01000000UL
#define VPEC_STATUS11__CE_IP5_WR_STALL_MASK                0x02000000UL
#define VPEC_STATUS11__CE_IP4_RD_STALL_MASK                0x04000000UL
#define VPEC_STATUS11__CE_IP5_RD_STALL_MASK                0x08000000UL
#define VPEC_STATUS11__RESERVED_31_28_MASK                 0xf0000000UL

// VPEC_INST
#define VPEC_INST__ID_MASK                                 0x00000007UL
#define VPEC_INST__RESERVED_MASK                           0xfffffff8UL

// VPEC_QUEUE_STATUS0
#define VPEC_QUEUE_STATUS0__QUEUE0_STATUS_MASK             0x0000000fUL
#define VPEC_QUEUE_STATUS0__QUEUE1_STATUS_MASK             0x000000f0UL
#define VPEC_QUEUE_STATUS0__QUEUE2_STATUS_MASK             0x00000f00UL
#define VPEC_QUEUE_STATUS0__QUEUE3_STATUS_MASK             0x0000f000UL
#define VPEC_QUEUE_STATUS0__QUEUE4_STATUS_MASK             0x000f0000UL
#define VPEC_QUEUE_STATUS0__QUEUE5_STATUS_MASK             0x00f00000UL
#define VPEC_QUEUE_STATUS0__QUEUE6_STATUS_MASK             0x0f000000UL
#define VPEC_QUEUE_STATUS0__QUEUE7_STATUS_MASK             0xf0000000UL

// VPEC_QUEUE_HANG_STATUS
#define VPEC_QUEUE_HANG_STATUS__F30T0_HANG_MASK            0x00000001UL
#define VPEC_QUEUE_HANG_STATUS__CE_HANG_MASK               0x00000002UL
#define VPEC_QUEUE_HANG_STATUS__EOF_MISMATCH_MASK          0x00000004UL
#define VPEC_QUEUE_HANG_STATUS__INVALID_PKT_FIELD_MASK     0x00000008UL
#define VPEC_QUEUE_HANG_STATUS__INVALID_VPEP_CONFIG_ADDR_MASK 0x00000010UL
#define VPEC_QUEUE_HANG_STATUS__F32_ACCESS_OFF_VPDPP1_MASK 0x00000020UL
#define VPEC_QUEUE_HANG_STATUS__RSMU_ACCESS_OFF_VPDPP1_MASK 0x00000040UL
#define VPEC_QUEUE_HANG_STATUS__EOH_MISMATCH_MASK          0x00000080UL

// VPEC_DPM_IDLE_TIME
#define VPEC_DPM_IDLE_TIME__VALUE_MASK                     0xffffffffUL

// VPEC_DPM_BUSY_TIME
#define VPEC_DPM_BUSY_TIME__VALUE_MASK                     0xffffffffUL

// VPEC_DPM_IDLE_START_LO
#define VPEC_DPM_IDLE_START_LO__VALUE_MASK                 0xffffffffUL

// VPEC_DPM_IDLE_START_HI
#define VPEC_DPM_IDLE_START_HI__VALUE_MASK                 0xffffffffUL

// VPEC_DPM_BUSY_START_LO
#define VPEC_DPM_BUSY_START_LO__VALUE_MASK                 0xffffffffUL

// VPEC_DPM_BUSY_START_HI
#define VPEC_DPM_BUSY_START_HI__VALUE_MASK                 0xffffffffUL

// VPEC_DPM_LAST_REQ_TIMESTAMP
#define VPEC_DPM_LAST_REQ_TIMESTAMP__VALUE_MASK            0xffffffffUL

// VPEC_DPM_NEW_JOB_DUMMY3
#define VPEC_DPM_NEW_JOB_DUMMY3__VALUE_MASK                0xffffffffUL

// VPEC_DPM_STATE
#define VPEC_DPM_STATE__VALUE_MASK                         0xffffffffUL

// VPEC_DPM0_FREQ
#define VPEC_DPM0_FREQ__VALUE_MASK                         0xffffffffUL

// VPEC_DPM1_FREQ
#define VPEC_DPM1_FREQ__VALUE_MASK                         0xffffffffUL

// VPEC_DPM2_FREQ
#define VPEC_DPM2_FREQ__VALUE_MASK                         0xffffffffUL

// VPEC_DPM3_FREQ
#define VPEC_DPM3_FREQ__VALUE_MASK                         0xffffffffUL

// VPEC_DPM_THRESHOLD_SKIP
#define VPEC_DPM_THRESHOLD_SKIP__VALUE_MASK                0xffffffffUL

// VPEC_DPM_THRESHOLD_BUSY_OVERFLOW
#define VPEC_DPM_THRESHOLD_BUSY_OVERFLOW__VALUE_MASK       0xffffffffUL

// VPEC_DPM_CALC_BUSY_IN_POSTPROCESS
#define VPEC_DPM_CALC_BUSY_IN_POSTPROCESS__VALUE_MASK      0xffffffffUL

// VPEC_DPM_IN_CHECKIDLE_LOOP
#define VPEC_DPM_IN_CHECKIDLE_LOOP__VALUE_MASK             0xffffffffUL

// VPEC_DPM_THRESHOLD_IDLE_OVERFLOW
#define VPEC_DPM_THRESHOLD_IDLE_OVERFLOW__VALUE_MASK       0xffffffffUL

// VPEC_DPM_BUSY_CLAMP_COUNT
#define VPEC_DPM_BUSY_CLAMP_COUNT__VALUE_MASK              0xffffffffUL

// VPEC_DPM_IDLE_CLAMP_COUNT
#define VPEC_DPM_IDLE_CLAMP_COUNT__VALUE_MASK              0xffffffffUL

// VPEC_PG_CNTL
#define VPEC_PG_CNTL__PG_EN_MASK                           0x00000001UL
#define VPEC_PG_CNTL__PG_HYSTERESIS_MASK                   0x0000003eUL
#define VPEC_PG_CNTL__PG1_EN_MASK                          0x00000100UL
#define VPEC_PG_CNTL__PG1_HYSTERESIS_MASK                  0x00003e00UL
#define VPEC_PG_CNTL__ZSTATES_ENABLE_MASK                  0x00010000UL
#define VPEC_PG_CNTL__ZSTATES_HYSTERESIS_MASK              0x003e0000UL
#define VPEC_PG_CNTL__FENCE_HYSTERESIS_MASK                0x0f000000UL
#define VPEC_PG_CNTL__CHECK_RSMU_UPON_POWER_UP_MASK        0x10000000UL

// VPEC_PG_STATUS
#define VPEC_PG_STATUS__PG_STATUS_MASK                     0x00000003UL
#define VPEC_PG_STATUS__PG1_STATUS_MASK                    0x0000000cUL

// VPEC_CLOCK_GATING_STATUS
#define VPEC_CLOCK_GATING_STATUS__DYN_CLK_GATE_STATUS_MASK 0x00000001UL
#define VPEC_CLOCK_GATING_STATUS__IP_PIPE0_CLK_GATE_STATUS_MASK 0x00000004UL
#define VPEC_CLOCK_GATING_STATUS__IP_PIPE1_CLK_GATE_STATUS_MASK 0x00000008UL
#define VPEC_CLOCK_GATING_STATUS__IP_PIPE2_CLK_GATE_STATUS_MASK 0x00000010UL
#define VPEC_CLOCK_GATING_STATUS__IP_PIPE3_CLK_GATE_STATUS_MASK 0x00000020UL
#define VPEC_CLOCK_GATING_STATUS__OP_PIPE0_CLK_GATE_STATUS_MASK 0x00000040UL
#define VPEC_CLOCK_GATING_STATUS__OP_PIPE1_CLK_GATE_STATUS_MASK 0x00000080UL
#define VPEC_CLOCK_GATING_STATUS__OP_PIPE2_CLK_GATE_STATUS_MASK 0x00000100UL
#define VPEC_CLOCK_GATING_STATUS__OP_PIPE3_CLK_GATE_STATUS_MASK 0x00000200UL
#define VPEC_CLOCK_GATING_STATUS__REG_CLK_GATE_STATUS_MASK 0x00000400UL
#define VPEC_CLOCK_GATING_STATUS__F32_CLK_GATE_STATUS_MASK 0x00000800UL
#define VPEC_CLOCK_GATING_STATUS__USRAM_CLK_GATE_STATUS_MASK 0x00001000UL
#define VPEC_CLOCK_GATING_STATUS__OP_PIPE4_CLK_GATE_STATUS_MASK 0x00002000UL
#define VPEC_CLOCK_GATING_STATUS__OP_PIPE5_CLK_GATE_STATUS_MASK 0x00004000UL
#define VPEC_CLOCK_GATING_STATUS__OP_PIPE6_CLK_GATE_STATUS_MASK 0x00008000UL
#define VPEC_CLOCK_GATING_STATUS__OP_PIPE7_CLK_GATE_STATUS_MASK 0x00010000UL
#define VPEC_CLOCK_GATING_STATUS__IP_PIPE4_CLK_GATE_STATUS_MASK 0x00020000UL
#define VPEC_CLOCK_GATING_STATUS__IP_PIPE5_CLK_GATE_STATUS_MASK 0x00040000UL
#define VPEC_CLOCK_GATING_STATUS__OP_PIPE8_CLK_GATE_STATUS_MASK 0x00080000UL
#define VPEC_CLOCK_GATING_STATUS__OP_PIPE9_CLK_GATE_STATUS_MASK 0x00100000UL

// VPEC_QUEUE0_RB_CNTL
#define VPEC_QUEUE0_RB_CNTL__RB_ENABLE_MASK                0x00000001UL
#define VPEC_QUEUE0_RB_CNTL__RB_SIZE_MASK                  0x0000003eUL
#define VPEC_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE_MASK         0x00000100UL
#define VPEC_QUEUE0_RB_CNTL__RB_SWAP_ENABLE_MASK           0x00000200UL
#define VPEC_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK    0x00000400UL
#define VPEC_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK     0x00000800UL
#define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK    0x00001000UL
#define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000UL
#define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK     0x001f0000UL
#define VPEC_QUEUE0_RB_CNTL__RB_PRIV_MASK                  0x00800000UL
#define VPEC_QUEUE0_RB_CNTL__RB_VMID_MASK                  0x0f000000UL

// VPEC_QUEUE0_SCHEDULE_CNTL
#define VPEC_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID_MASK          0x00000003UL
#define VPEC_QUEUE0_SCHEDULE_CNTL__PROCESS_ID_MASK         0x0000001cUL
#define VPEC_QUEUE0_SCHEDULE_CNTL__LOCAL_ID_MASK           0x000000c0UL
#define VPEC_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK    0x0000ff00UL

// VPEC_QUEUE0_RB_BASE
#define VPEC_QUEUE0_RB_BASE__ADDR_MASK                     0xffffffffUL

// VPEC_QUEUE0_RB_BASE_HI
#define VPEC_QUEUE0_RB_BASE_HI__ADDR_MASK                  0x00ffffffUL

// VPEC_QUEUE0_RB_RPTR
#define VPEC_QUEUE0_RB_RPTR__OFFSET_MASK                   0xffffffffUL

// VPEC_QUEUE0_RB_RPTR_HI
#define VPEC_QUEUE0_RB_RPTR_HI__OFFSET_MASK                0xffffffffUL

// VPEC_QUEUE0_RB_WPTR
#define VPEC_QUEUE0_RB_WPTR__OFFSET_MASK                   0xffffffffUL

// VPEC_QUEUE0_RB_WPTR_HI
#define VPEC_QUEUE0_RB_WPTR_HI__OFFSET_MASK                0xffffffffUL

// VPEC_QUEUE0_RB_RPTR_ADDR_HI
#define VPEC_QUEUE0_RB_RPTR_ADDR_HI__ADDR_MASK             0xffffffffUL

// VPEC_QUEUE0_RB_RPTR_ADDR_LO
#define VPEC_QUEUE0_RB_RPTR_ADDR_LO__ADDR_MASK             0xfffffffcUL

// VPEC_QUEUE0_RB_AQL_CNTL
#define VPEC_QUEUE0_RB_AQL_CNTL__AQL_ENABLE_MASK           0x00000001UL
#define VPEC_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK      0x000000feUL
#define VPEC_QUEUE0_RB_AQL_CNTL__PACKET_STEP_MASK          0x0000ff00UL
#define VPEC_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000UL
#define VPEC_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000UL
#define VPEC_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE_MASK       0x00040000UL

// VPEC_QUEUE0_MINOR_PTR_UPDATE
#define VPEC_QUEUE0_MINOR_PTR_UPDATE__ENABLE_MASK          0x00000001UL

// VPEC_QUEUE0_CD_INFO
#define VPEC_QUEUE0_CD_INFO__CD_INFO_MASK                  0xffffffffUL

// VPEC_QUEUE0_RB_PREEMPT
#define VPEC_QUEUE0_RB_PREEMPT__PREEMPT_REQ_MASK           0x00000001UL

// VPEC_QUEUE0_SKIP_CNTL
#define VPEC_QUEUE0_SKIP_CNTL__SKIP_COUNT_MASK             0x000fffffUL

// VPEC_QUEUE0_DOORBELL
#define VPEC_QUEUE0_DOORBELL__ENABLE_MASK                  0x10000000UL
#define VPEC_QUEUE0_DOORBELL__CAPTURED_MASK                0x40000000UL

// VPEC_QUEUE0_DOORBELL_OFFSET
#define VPEC_QUEUE0_DOORBELL_OFFSET__OFFSET_MASK           0x0ffffffcUL

// VPEC_QUEUE0_DUMMY0
#define VPEC_QUEUE0_DUMMY0__DUMMY_MASK                     0xffffffffUL

// VPEC_QUEUE0_DUMMY1
#define VPEC_QUEUE0_DUMMY1__VALUE_MASK                     0xffffffffUL

// VPEC_QUEUE0_DUMMY2
#define VPEC_QUEUE0_DUMMY2__VALUE_MASK                     0xffffffffUL

// VPEC_QUEUE0_DUMMY3
#define VPEC_QUEUE0_DUMMY3__VALUE_MASK                     0xffffffffUL

// VPEC_QUEUE0_DUMMY4
#define VPEC_QUEUE0_DUMMY4__VALUE_MASK                     0xffffffffUL

// VPEC_QUEUE0_IB_CNTL
#define VPEC_QUEUE0_IB_CNTL__IB_ENABLE_MASK                0x00000001UL
#define VPEC_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB_MASK         0x00000100UL
#define VPEC_QUEUE0_IB_CNTL__CMD_VMID_MASK                 0x000f0000UL
#define VPEC_QUEUE0_IB_CNTL__IB_PRIV_MASK                  0x80000000UL

// VPEC_QUEUE0_IB_RPTR
#define VPEC_QUEUE0_IB_RPTR__OFFSET_MASK                   0x003ffffcUL

// VPEC_QUEUE0_IB_OFFSET
#define VPEC_QUEUE0_IB_OFFSET__OFFSET_MASK                 0x003ffffcUL

// VPEC_QUEUE0_IB_BASE_LO
#define VPEC_QUEUE0_IB_BASE_LO__ADDR_MASK                  0xffffffe0UL

// VPEC_QUEUE0_IB_BASE_HI
#define VPEC_QUEUE0_IB_BASE_HI__ADDR_MASK                  0xffffffffUL

// VPEC_QUEUE0_IB_SIZE
#define VPEC_QUEUE0_IB_SIZE__SIZE_MASK                     0x000fffffUL

// VPEC_QUEUE0_CMDIB_CNTL
#define VPEC_QUEUE0_CMDIB_CNTL__IB_ENABLE_MASK             0x00000001UL
#define VPEC_QUEUE0_CMDIB_CNTL__IB_SWAP_ENABLE_MASK        0x00000010UL
#define VPEC_QUEUE0_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK      0x00000100UL
#define VPEC_QUEUE0_CMDIB_CNTL__CMD_VMID_MASK              0x000f0000UL
#define VPEC_QUEUE0_CMDIB_CNTL__IB_PRIV_MASK               0x80000000UL

// VPEC_QUEUE0_CMDIB_RPTR
#define VPEC_QUEUE0_CMDIB_RPTR__OFFSET_MASK                0x003ffffcUL

// VPEC_QUEUE0_CMDIB_OFFSET
#define VPEC_QUEUE0_CMDIB_OFFSET__OFFSET_MASK              0x003ffffcUL

// VPEC_QUEUE0_CMDIB_BASE_LO
#define VPEC_QUEUE0_CMDIB_BASE_LO__ADDR_MASK               0xffffffe0UL

// VPEC_QUEUE0_CMDIB_BASE_HI
#define VPEC_QUEUE0_CMDIB_BASE_HI__ADDR_MASK               0xffffffffUL

// VPEC_QUEUE0_CMDIB_SIZE
#define VPEC_QUEUE0_CMDIB_SIZE__SIZE_MASK                  0x000fffffUL

// VPEC_QUEUE0_3DLUTIB_CNTL
#define VPEC_QUEUE0_3DLUTIB_CNTL__IB_ENABLE_MASK           0x00000001UL
#define VPEC_QUEUE0_3DLUTIB_CNTL__SWITCH_INSIDE_IB_MASK    0x00000100UL
#define VPEC_QUEUE0_3DLUTIB_CNTL__CMD_VMID_MASK            0x000f0000UL
#define VPEC_QUEUE0_3DLUTIB_CNTL__IB_PRIV_MASK             0x80000000UL

// VPEC_QUEUE0_3DLUTIB_RPTR
#define VPEC_QUEUE0_3DLUTIB_RPTR__OFFSET_MASK              0x003ffffcUL

// VPEC_QUEUE0_3DLUTIB_OFFSET
#define VPEC_QUEUE0_3DLUTIB_OFFSET__OFFSET_MASK            0x003ffffcUL

// VPEC_QUEUE0_3DLUTIB_BASE_LO
#define VPEC_QUEUE0_3DLUTIB_BASE_LO__ADDR_MASK             0xffffffe0UL

// VPEC_QUEUE0_3DLUTIB_BASE_HI
#define VPEC_QUEUE0_3DLUTIB_BASE_HI__ADDR_MASK             0xffffffffUL

// VPEC_QUEUE0_3DLUTIB_SIZE
#define VPEC_QUEUE0_3DLUTIB_SIZE__SIZE_MASK                0x000fffffUL

// VPEC_QUEUE0_CSA_ADDR_LO
#define VPEC_QUEUE0_CSA_ADDR_LO__ADDR_MASK                 0xffffffffUL

// VPEC_QUEUE0_CSA_ADDR_HI
#define VPEC_QUEUE0_CSA_ADDR_HI__ADDR_MASK                 0xffffffffUL

// VPEC_QUEUE0_CONTEXT_STATUS
#define VPEC_QUEUE0_CONTEXT_STATUS__SELECTED_MASK          0x00000001UL
#define VPEC_QUEUE0_CONTEXT_STATUS__USE_IB_MASK            0x00000002UL
#define VPEC_QUEUE0_CONTEXT_STATUS__IDLE_MASK              0x00000004UL
#define VPEC_QUEUE0_CONTEXT_STATUS__EXPIRED_MASK           0x00000008UL
#define VPEC_QUEUE0_CONTEXT_STATUS__EXCEPTION_MASK         0x00000070UL
#define VPEC_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE_MASK        0x00000080UL
#define VPEC_QUEUE0_CONTEXT_STATUS__USE_3DLUTIB_MASK       0x00000100UL
#define VPEC_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK   0x00000400UL
#define VPEC_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE_MASK      0x00000800UL
#define VPEC_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000UL
#define VPEC_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00ff0000UL

// VPEC_QUEUE0_DOORBELL_LOG
#define VPEC_QUEUE0_DOORBELL_LOG__BE_ERROR_MASK            0x00000001UL
#define VPEC_QUEUE0_DOORBELL_LOG__DATA_MASK                0xfffffffcUL

// VPEC_QUEUE0_IB_SUB_REMAIN
#define VPEC_QUEUE0_IB_SUB_REMAIN__SIZE_MASK               0x00003fffUL

// VPEC_QUEUE0_PREEMPT
#define VPEC_QUEUE0_PREEMPT__IB_PREEMPT_MASK               0x00000001UL

// VPEC_QUEUE0_LOG0BUFFER_CFG
#define VPEC_QUEUE0_LOG0BUFFER_CFG__ENABLE_MASK            0x00000001UL
#define VPEC_QUEUE0_LOG0BUFFER_CFG__FIRST_FREE_ENTRY_MASK  0x00000ff0UL
#define VPEC_QUEUE0_LOG0BUFFER_CFG__LAST_FREE_ENTRY_MASK   0x000ff000UL
#define VPEC_QUEUE0_LOG0BUFFER_CFG__RESERVED_MASK          0xfff00000UL

// VPEC_QUEUE0_LOG1BUFFER_CFG
#define VPEC_QUEUE0_LOG1BUFFER_CFG__ENABLE_MASK            0x00000001UL
#define VPEC_QUEUE0_LOG1BUFFER_CFG__PARTIAL_ENTRY_MASK     0x00000002UL
#define VPEC_QUEUE0_LOG1BUFFER_CFG__FIRST_FREE_ENTRY_MASK  0x00000ff0UL
#define VPEC_QUEUE0_LOG1BUFFER_CFG__LAST_FREE_ENTRY_MASK   0x000ff000UL
#define VPEC_QUEUE0_LOG1BUFFER_CFG__RESERVED_MASK          0xfff00000UL

// VPEC_QUEUE1_RB_CNTL
#define VPEC_QUEUE1_RB_CNTL__RB_ENABLE_MASK                0x00000001UL
#define VPEC_QUEUE1_RB_CNTL__RB_SIZE_MASK                  0x0000003eUL
#define VPEC_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE_MASK         0x00000100UL
#define VPEC_QUEUE1_RB_CNTL__RB_SWAP_ENABLE_MASK           0x00000200UL
#define VPEC_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK    0x00000400UL
#define VPEC_QUEUE1_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK     0x00000800UL
#define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK    0x00001000UL
#define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000UL
#define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK     0x001f0000UL
#define VPEC_QUEUE1_RB_CNTL__RB_PRIV_MASK                  0x00800000UL
#define VPEC_QUEUE1_RB_CNTL__RB_VMID_MASK                  0x0f000000UL

// VPEC_QUEUE1_SCHEDULE_CNTL
#define VPEC_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID_MASK          0x00000003UL
#define VPEC_QUEUE1_SCHEDULE_CNTL__PROCESS_ID_MASK         0x0000001cUL
#define VPEC_QUEUE1_SCHEDULE_CNTL__LOCAL_ID_MASK           0x000000c0UL
#define VPEC_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK    0x0000ff00UL

// VPEC_QUEUE1_RB_BASE
#define VPEC_QUEUE1_RB_BASE__ADDR_MASK                     0xffffffffUL

// VPEC_QUEUE1_RB_BASE_HI
#define VPEC_QUEUE1_RB_BASE_HI__ADDR_MASK                  0x00ffffffUL

// VPEC_QUEUE1_RB_RPTR
#define VPEC_QUEUE1_RB_RPTR__OFFSET_MASK                   0xffffffffUL

// VPEC_QUEUE1_RB_RPTR_HI
#define VPEC_QUEUE1_RB_RPTR_HI__OFFSET_MASK                0xffffffffUL

// VPEC_QUEUE1_RB_WPTR
#define VPEC_QUEUE1_RB_WPTR__OFFSET_MASK                   0xffffffffUL

// VPEC_QUEUE1_RB_WPTR_HI
#define VPEC_QUEUE1_RB_WPTR_HI__OFFSET_MASK                0xffffffffUL

// VPEC_QUEUE1_RB_RPTR_ADDR_HI
#define VPEC_QUEUE1_RB_RPTR_ADDR_HI__ADDR_MASK             0xffffffffUL

// VPEC_QUEUE1_RB_RPTR_ADDR_LO
#define VPEC_QUEUE1_RB_RPTR_ADDR_LO__ADDR_MASK             0xfffffffcUL

// VPEC_QUEUE1_RB_AQL_CNTL
#define VPEC_QUEUE1_RB_AQL_CNTL__AQL_ENABLE_MASK           0x00000001UL
#define VPEC_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK      0x000000feUL
#define VPEC_QUEUE1_RB_AQL_CNTL__PACKET_STEP_MASK          0x0000ff00UL
#define VPEC_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000UL
#define VPEC_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000UL
#define VPEC_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE_MASK       0x00040000UL

// VPEC_QUEUE1_MINOR_PTR_UPDATE
#define VPEC_QUEUE1_MINOR_PTR_UPDATE__ENABLE_MASK          0x00000001UL

// VPEC_QUEUE1_CD_INFO
#define VPEC_QUEUE1_CD_INFO__CD_INFO_MASK                  0xffffffffUL

// VPEC_QUEUE1_RB_PREEMPT
#define VPEC_QUEUE1_RB_PREEMPT__PREEMPT_REQ_MASK           0x00000001UL

// VPEC_QUEUE1_SKIP_CNTL
#define VPEC_QUEUE1_SKIP_CNTL__SKIP_COUNT_MASK             0x000fffffUL

// VPEC_QUEUE1_DOORBELL
#define VPEC_QUEUE1_DOORBELL__ENABLE_MASK                  0x10000000UL
#define VPEC_QUEUE1_DOORBELL__CAPTURED_MASK                0x40000000UL

// VPEC_QUEUE1_DOORBELL_OFFSET
#define VPEC_QUEUE1_DOORBELL_OFFSET__OFFSET_MASK           0x0ffffffcUL

// VPEC_QUEUE1_DUMMY0
#define VPEC_QUEUE1_DUMMY0__DUMMY_MASK                     0xffffffffUL

// VPEC_QUEUE1_DUMMY1
#define VPEC_QUEUE1_DUMMY1__VALUE_MASK                     0xffffffffUL

// VPEC_QUEUE1_DUMMY2
#define VPEC_QUEUE1_DUMMY2__VALUE_MASK                     0xffffffffUL

// VPEC_QUEUE1_DUMMY3
#define VPEC_QUEUE1_DUMMY3__VALUE_MASK                     0xffffffffUL

// VPEC_QUEUE1_DUMMY4
#define VPEC_QUEUE1_DUMMY4__VALUE_MASK                     0xffffffffUL

// VPEC_QUEUE1_IB_CNTL
#define VPEC_QUEUE1_IB_CNTL__IB_ENABLE_MASK                0x00000001UL
#define VPEC_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB_MASK         0x00000100UL
#define VPEC_QUEUE1_IB_CNTL__CMD_VMID_MASK                 0x000f0000UL
#define VPEC_QUEUE1_IB_CNTL__IB_PRIV_MASK                  0x80000000UL

// VPEC_QUEUE1_IB_RPTR
#define VPEC_QUEUE1_IB_RPTR__OFFSET_MASK                   0x003ffffcUL

// VPEC_QUEUE1_IB_OFFSET
#define VPEC_QUEUE1_IB_OFFSET__OFFSET_MASK                 0x003ffffcUL

// VPEC_QUEUE1_IB_BASE_LO
#define VPEC_QUEUE1_IB_BASE_LO__ADDR_MASK                  0xffffffe0UL

// VPEC_QUEUE1_IB_BASE_HI
#define VPEC_QUEUE1_IB_BASE_HI__ADDR_MASK                  0xffffffffUL

// VPEC_QUEUE1_IB_SIZE
#define VPEC_QUEUE1_IB_SIZE__SIZE_MASK                     0x000fffffUL

// VPEC_QUEUE1_CMDIB_CNTL
#define VPEC_QUEUE1_CMDIB_CNTL__IB_ENABLE_MASK             0x00000001UL
#define VPEC_QUEUE1_CMDIB_CNTL__IB_SWAP_ENABLE_MASK        0x00000010UL
#define VPEC_QUEUE1_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK      0x00000100UL
#define VPEC_QUEUE1_CMDIB_CNTL__CMD_VMID_MASK              0x000f0000UL
#define VPEC_QUEUE1_CMDIB_CNTL__IB_PRIV_MASK               0x80000000UL

// VPEC_QUEUE1_CMDIB_RPTR
#define VPEC_QUEUE1_CMDIB_RPTR__OFFSET_MASK                0x003ffffcUL

// VPEC_QUEUE1_CMDIB_OFFSET
#define VPEC_QUEUE1_CMDIB_OFFSET__OFFSET_MASK              0x003ffffcUL

// VPEC_QUEUE1_CMDIB_BASE_LO
#define VPEC_QUEUE1_CMDIB_BASE_LO__ADDR_MASK               0xffffffe0UL

// VPEC_QUEUE1_CMDIB_BASE_HI
#define VPEC_QUEUE1_CMDIB_BASE_HI__ADDR_MASK               0xffffffffUL

// VPEC_QUEUE1_CMDIB_SIZE
#define VPEC_QUEUE1_CMDIB_SIZE__SIZE_MASK                  0x000fffffUL

// VPEC_QUEUE1_3DLUTIB_CNTL
#define VPEC_QUEUE1_3DLUTIB_CNTL__IB_ENABLE_MASK           0x00000001UL
#define VPEC_QUEUE1_3DLUTIB_CNTL__SWITCH_INSIDE_IB_MASK    0x00000100UL
#define VPEC_QUEUE1_3DLUTIB_CNTL__CMD_VMID_MASK            0x000f0000UL
#define VPEC_QUEUE1_3DLUTIB_CNTL__IB_PRIV_MASK             0x80000000UL

// VPEC_QUEUE1_3DLUTIB_RPTR
#define VPEC_QUEUE1_3DLUTIB_RPTR__OFFSET_MASK              0x003ffffcUL

// VPEC_QUEUE1_3DLUTIB_OFFSET
#define VPEC_QUEUE1_3DLUTIB_OFFSET__OFFSET_MASK            0x003ffffcUL

// VPEC_QUEUE1_3DLUTIB_BASE_LO
#define VPEC_QUEUE1_3DLUTIB_BASE_LO__ADDR_MASK             0xffffffe0UL

// VPEC_QUEUE1_3DLUTIB_BASE_HI
#define VPEC_QUEUE1_3DLUTIB_BASE_HI__ADDR_MASK             0xffffffffUL

// VPEC_QUEUE1_3DLUTIB_SIZE
#define VPEC_QUEUE1_3DLUTIB_SIZE__SIZE_MASK                0x000fffffUL

// VPEC_QUEUE1_CSA_ADDR_LO
#define VPEC_QUEUE1_CSA_ADDR_LO__ADDR_MASK                 0xffffffffUL

// VPEC_QUEUE1_CSA_ADDR_HI
#define VPEC_QUEUE1_CSA_ADDR_HI__ADDR_MASK                 0xffffffffUL

// VPEC_QUEUE1_CONTEXT_STATUS
#define VPEC_QUEUE1_CONTEXT_STATUS__SELECTED_MASK          0x00000001UL
#define VPEC_QUEUE1_CONTEXT_STATUS__USE_IB_MASK            0x00000002UL
#define VPEC_QUEUE1_CONTEXT_STATUS__IDLE_MASK              0x00000004UL
#define VPEC_QUEUE1_CONTEXT_STATUS__EXPIRED_MASK           0x00000008UL
#define VPEC_QUEUE1_CONTEXT_STATUS__EXCEPTION_MASK         0x00000070UL
#define VPEC_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE_MASK        0x00000080UL
#define VPEC_QUEUE1_CONTEXT_STATUS__USE_3DLUTIB_MASK       0x00000100UL
#define VPEC_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK   0x00000400UL
#define VPEC_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE_MASK      0x00000800UL
#define VPEC_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000UL
#define VPEC_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00ff0000UL

// VPEC_QUEUE1_DOORBELL_LOG
#define VPEC_QUEUE1_DOORBELL_LOG__BE_ERROR_MASK            0x00000001UL
#define VPEC_QUEUE1_DOORBELL_LOG__DATA_MASK                0xfffffffcUL

// VPEC_QUEUE1_IB_SUB_REMAIN
#define VPEC_QUEUE1_IB_SUB_REMAIN__SIZE_MASK               0x00003fffUL

// VPEC_QUEUE1_PREEMPT
#define VPEC_QUEUE1_PREEMPT__IB_PREEMPT_MASK               0x00000001UL

// VPEC_QUEUE1_LOG0BUFFER_CFG
#define VPEC_QUEUE1_LOG0BUFFER_CFG__ENABLE_MASK            0x00000001UL
#define VPEC_QUEUE1_LOG0BUFFER_CFG__FIRST_FREE_ENTRY_MASK  0x00000ff0UL
#define VPEC_QUEUE1_LOG0BUFFER_CFG__LAST_FREE_ENTRY_MASK   0x000ff000UL
#define VPEC_QUEUE1_LOG0BUFFER_CFG__RESERVED_MASK          0xfff00000UL

// VPEC_QUEUE1_LOG1BUFFER_CFG
#define VPEC_QUEUE1_LOG1BUFFER_CFG__ENABLE_MASK            0x00000001UL
#define VPEC_QUEUE1_LOG1BUFFER_CFG__PARTIAL_ENTRY_MASK     0x00000002UL
#define VPEC_QUEUE1_LOG1BUFFER_CFG__FIRST_FREE_ENTRY_MASK  0x00000ff0UL
#define VPEC_QUEUE1_LOG1BUFFER_CFG__LAST_FREE_ENTRY_MASK   0x000ff000UL
#define VPEC_QUEUE1_LOG1BUFFER_CFG__RESERVED_MASK          0xfff00000UL

// VPEC_QUEUE2_RB_CNTL
#define VPEC_QUEUE2_RB_CNTL__RB_ENABLE_MASK                0x00000001UL
#define VPEC_QUEUE2_RB_CNTL__RB_SIZE_MASK                  0x0000003eUL
#define VPEC_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE_MASK         0x00000100UL
#define VPEC_QUEUE2_RB_CNTL__RB_SWAP_ENABLE_MASK           0x00000200UL
#define VPEC_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK    0x00000400UL
#define VPEC_QUEUE2_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK     0x00000800UL
#define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK    0x00001000UL
#define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000UL
#define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK     0x001f0000UL
#define VPEC_QUEUE2_RB_CNTL__RB_PRIV_MASK                  0x00800000UL
#define VPEC_QUEUE2_RB_CNTL__RB_VMID_MASK                  0x0f000000UL

// VPEC_QUEUE2_SCHEDULE_CNTL
#define VPEC_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID_MASK          0x00000003UL
#define VPEC_QUEUE2_SCHEDULE_CNTL__PROCESS_ID_MASK         0x0000001cUL
#define VPEC_QUEUE2_SCHEDULE_CNTL__LOCAL_ID_MASK           0x000000c0UL
#define VPEC_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK    0x0000ff00UL

// VPEC_QUEUE2_RB_BASE
#define VPEC_QUEUE2_RB_BASE__ADDR_MASK                     0xffffffffUL

// VPEC_QUEUE2_RB_BASE_HI
#define VPEC_QUEUE2_RB_BASE_HI__ADDR_MASK                  0x00ffffffUL

// VPEC_QUEUE2_RB_RPTR
#define VPEC_QUEUE2_RB_RPTR__OFFSET_MASK                   0xffffffffUL

// VPEC_QUEUE2_RB_RPTR_HI
#define VPEC_QUEUE2_RB_RPTR_HI__OFFSET_MASK                0xffffffffUL

// VPEC_QUEUE2_RB_WPTR
#define VPEC_QUEUE2_RB_WPTR__OFFSET_MASK                   0xffffffffUL

// VPEC_QUEUE2_RB_WPTR_HI
#define VPEC_QUEUE2_RB_WPTR_HI__OFFSET_MASK                0xffffffffUL

// VPEC_QUEUE2_RB_RPTR_ADDR_HI
#define VPEC_QUEUE2_RB_RPTR_ADDR_HI__ADDR_MASK             0xffffffffUL

// VPEC_QUEUE2_RB_RPTR_ADDR_LO
#define VPEC_QUEUE2_RB_RPTR_ADDR_LO__ADDR_MASK             0xfffffffcUL

// VPEC_QUEUE2_RB_AQL_CNTL
#define VPEC_QUEUE2_RB_AQL_CNTL__AQL_ENABLE_MASK           0x00000001UL
#define VPEC_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK      0x000000feUL
#define VPEC_QUEUE2_RB_AQL_CNTL__PACKET_STEP_MASK          0x0000ff00UL
#define VPEC_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000UL
#define VPEC_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000UL
#define VPEC_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE_MASK       0x00040000UL

// VPEC_QUEUE2_MINOR_PTR_UPDATE
#define VPEC_QUEUE2_MINOR_PTR_UPDATE__ENABLE_MASK          0x00000001UL

// VPEC_QUEUE2_CD_INFO
#define VPEC_QUEUE2_CD_INFO__CD_INFO_MASK                  0xffffffffUL

// VPEC_QUEUE2_RB_PREEMPT
#define VPEC_QUEUE2_RB_PREEMPT__PREEMPT_REQ_MASK           0x00000001UL

// VPEC_QUEUE2_SKIP_CNTL
#define VPEC_QUEUE2_SKIP_CNTL__SKIP_COUNT_MASK             0x000fffffUL

// VPEC_QUEUE2_DOORBELL
#define VPEC_QUEUE2_DOORBELL__ENABLE_MASK                  0x10000000UL
#define VPEC_QUEUE2_DOORBELL__CAPTURED_MASK                0x40000000UL

// VPEC_QUEUE2_DOORBELL_OFFSET
#define VPEC_QUEUE2_DOORBELL_OFFSET__OFFSET_MASK           0x0ffffffcUL

// VPEC_QUEUE2_DUMMY0
#define VPEC_QUEUE2_DUMMY0__DUMMY_MASK                     0xffffffffUL

// VPEC_QUEUE2_DUMMY1
#define VPEC_QUEUE2_DUMMY1__VALUE_MASK                     0xffffffffUL

// VPEC_QUEUE2_DUMMY2
#define VPEC_QUEUE2_DUMMY2__VALUE_MASK                     0xffffffffUL

// VPEC_QUEUE2_DUMMY3
#define VPEC_QUEUE2_DUMMY3__VALUE_MASK                     0xffffffffUL

// VPEC_QUEUE2_DUMMY4
#define VPEC_QUEUE2_DUMMY4__VALUE_MASK                     0xffffffffUL

// VPEC_QUEUE2_IB_CNTL
#define VPEC_QUEUE2_IB_CNTL__IB_ENABLE_MASK                0x00000001UL
#define VPEC_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB_MASK         0x00000100UL
#define VPEC_QUEUE2_IB_CNTL__CMD_VMID_MASK                 0x000f0000UL
#define VPEC_QUEUE2_IB_CNTL__IB_PRIV_MASK                  0x80000000UL

// VPEC_QUEUE2_IB_RPTR
#define VPEC_QUEUE2_IB_RPTR__OFFSET_MASK                   0x003ffffcUL

// VPEC_QUEUE2_IB_OFFSET
#define VPEC_QUEUE2_IB_OFFSET__OFFSET_MASK                 0x003ffffcUL

// VPEC_QUEUE2_IB_BASE_LO
#define VPEC_QUEUE2_IB_BASE_LO__ADDR_MASK                  0xffffffe0UL

// VPEC_QUEUE2_IB_BASE_HI
#define VPEC_QUEUE2_IB_BASE_HI__ADDR_MASK                  0xffffffffUL

// VPEC_QUEUE2_IB_SIZE
#define VPEC_QUEUE2_IB_SIZE__SIZE_MASK                     0x000fffffUL

// VPEC_QUEUE2_CMDIB_CNTL
#define VPEC_QUEUE2_CMDIB_CNTL__IB_ENABLE_MASK             0x00000001UL
#define VPEC_QUEUE2_CMDIB_CNTL__IB_SWAP_ENABLE_MASK        0x00000010UL
#define VPEC_QUEUE2_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK      0x00000100UL
#define VPEC_QUEUE2_CMDIB_CNTL__CMD_VMID_MASK              0x000f0000UL
#define VPEC_QUEUE2_CMDIB_CNTL__IB_PRIV_MASK               0x80000000UL

// VPEC_QUEUE2_CMDIB_RPTR
#define VPEC_QUEUE2_CMDIB_RPTR__OFFSET_MASK                0x003ffffcUL

// VPEC_QUEUE2_CMDIB_OFFSET
#define VPEC_QUEUE2_CMDIB_OFFSET__OFFSET_MASK              0x003ffffcUL

// VPEC_QUEUE2_CMDIB_BASE_LO
#define VPEC_QUEUE2_CMDIB_BASE_LO__ADDR_MASK               0xffffffe0UL

// VPEC_QUEUE2_CMDIB_BASE_HI
#define VPEC_QUEUE2_CMDIB_BASE_HI__ADDR_MASK               0xffffffffUL

// VPEC_QUEUE2_CMDIB_SIZE
#define VPEC_QUEUE2_CMDIB_SIZE__SIZE_MASK                  0x000fffffUL

// VPEC_QUEUE2_3DLUTIB_CNTL
#define VPEC_QUEUE2_3DLUTIB_CNTL__IB_ENABLE_MASK           0x00000001UL
#define VPEC_QUEUE2_3DLUTIB_CNTL__SWITCH_INSIDE_IB_MASK    0x00000100UL
#define VPEC_QUEUE2_3DLUTIB_CNTL__CMD_VMID_MASK            0x000f0000UL
#define VPEC_QUEUE2_3DLUTIB_CNTL__IB_PRIV_MASK             0x80000000UL

// VPEC_QUEUE2_3DLUTIB_RPTR
#define VPEC_QUEUE2_3DLUTIB_RPTR__OFFSET_MASK              0x003ffffcUL

// VPEC_QUEUE2_3DLUTIB_OFFSET
#define VPEC_QUEUE2_3DLUTIB_OFFSET__OFFSET_MASK            0x003ffffcUL

// VPEC_QUEUE2_3DLUTIB_BASE_LO
#define VPEC_QUEUE2_3DLUTIB_BASE_LO__ADDR_MASK             0xffffffe0UL

// VPEC_QUEUE2_3DLUTIB_BASE_HI
#define VPEC_QUEUE2_3DLUTIB_BASE_HI__ADDR_MASK             0xffffffffUL

// VPEC_QUEUE2_3DLUTIB_SIZE
#define VPEC_QUEUE2_3DLUTIB_SIZE__SIZE_MASK                0x000fffffUL

// VPEC_QUEUE2_CSA_ADDR_LO
#define VPEC_QUEUE2_CSA_ADDR_LO__ADDR_MASK                 0xffffffffUL

// VPEC_QUEUE2_CSA_ADDR_HI
#define VPEC_QUEUE2_CSA_ADDR_HI__ADDR_MASK                 0xffffffffUL

// VPEC_QUEUE2_CONTEXT_STATUS
#define VPEC_QUEUE2_CONTEXT_STATUS__SELECTED_MASK          0x00000001UL
#define VPEC_QUEUE2_CONTEXT_STATUS__USE_IB_MASK            0x00000002UL
#define VPEC_QUEUE2_CONTEXT_STATUS__IDLE_MASK              0x00000004UL
#define VPEC_QUEUE2_CONTEXT_STATUS__EXPIRED_MASK           0x00000008UL
#define VPEC_QUEUE2_CONTEXT_STATUS__EXCEPTION_MASK         0x00000070UL
#define VPEC_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE_MASK        0x00000080UL
#define VPEC_QUEUE2_CONTEXT_STATUS__USE_3DLUTIB_MASK       0x00000100UL
#define VPEC_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK   0x00000400UL
#define VPEC_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE_MASK      0x00000800UL
#define VPEC_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000UL
#define VPEC_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00ff0000UL

// VPEC_QUEUE2_DOORBELL_LOG
#define VPEC_QUEUE2_DOORBELL_LOG__BE_ERROR_MASK            0x00000001UL
#define VPEC_QUEUE2_DOORBELL_LOG__DATA_MASK                0xfffffffcUL

// VPEC_QUEUE2_IB_SUB_REMAIN
#define VPEC_QUEUE2_IB_SUB_REMAIN__SIZE_MASK               0x00003fffUL

// VPEC_QUEUE2_PREEMPT
#define VPEC_QUEUE2_PREEMPT__IB_PREEMPT_MASK               0x00000001UL

// VPEC_QUEUE2_LOG0BUFFER_CFG
#define VPEC_QUEUE2_LOG0BUFFER_CFG__ENABLE_MASK            0x00000001UL
#define VPEC_QUEUE2_LOG0BUFFER_CFG__FIRST_FREE_ENTRY_MASK  0x00000ff0UL
#define VPEC_QUEUE2_LOG0BUFFER_CFG__LAST_FREE_ENTRY_MASK   0x000ff000UL
#define VPEC_QUEUE2_LOG0BUFFER_CFG__RESERVED_MASK          0xfff00000UL

// VPEC_QUEUE2_LOG1BUFFER_CFG
#define VPEC_QUEUE2_LOG1BUFFER_CFG__ENABLE_MASK            0x00000001UL
#define VPEC_QUEUE2_LOG1BUFFER_CFG__PARTIAL_ENTRY_MASK     0x00000002UL
#define VPEC_QUEUE2_LOG1BUFFER_CFG__FIRST_FREE_ENTRY_MASK  0x00000ff0UL
#define VPEC_QUEUE2_LOG1BUFFER_CFG__LAST_FREE_ENTRY_MASK   0x000ff000UL
#define VPEC_QUEUE2_LOG1BUFFER_CFG__RESERVED_MASK          0xfff00000UL

// VPEC_QUEUE3_RB_CNTL
#define VPEC_QUEUE3_RB_CNTL__RB_ENABLE_MASK                0x00000001UL
#define VPEC_QUEUE3_RB_CNTL__RB_SIZE_MASK                  0x0000003eUL
#define VPEC_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE_MASK         0x00000100UL
#define VPEC_QUEUE3_RB_CNTL__RB_SWAP_ENABLE_MASK           0x00000200UL
#define VPEC_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK    0x00000400UL
#define VPEC_QUEUE3_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK     0x00000800UL
#define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK    0x00001000UL
#define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000UL
#define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK     0x001f0000UL
#define VPEC_QUEUE3_RB_CNTL__RB_PRIV_MASK                  0x00800000UL
#define VPEC_QUEUE3_RB_CNTL__RB_VMID_MASK                  0x0f000000UL

// VPEC_QUEUE3_SCHEDULE_CNTL
#define VPEC_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID_MASK          0x00000003UL
#define VPEC_QUEUE3_SCHEDULE_CNTL__PROCESS_ID_MASK         0x0000001cUL
#define VPEC_QUEUE3_SCHEDULE_CNTL__LOCAL_ID_MASK           0x000000c0UL
#define VPEC_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK    0x0000ff00UL

// VPEC_QUEUE3_RB_BASE
#define VPEC_QUEUE3_RB_BASE__ADDR_MASK                     0xffffffffUL

// VPEC_QUEUE3_RB_BASE_HI
#define VPEC_QUEUE3_RB_BASE_HI__ADDR_MASK                  0x00ffffffUL

// VPEC_QUEUE3_RB_RPTR
#define VPEC_QUEUE3_RB_RPTR__OFFSET_MASK                   0xffffffffUL

// VPEC_QUEUE3_RB_RPTR_HI
#define VPEC_QUEUE3_RB_RPTR_HI__OFFSET_MASK                0xffffffffUL

// VPEC_QUEUE3_RB_WPTR
#define VPEC_QUEUE3_RB_WPTR__OFFSET_MASK                   0xffffffffUL

// VPEC_QUEUE3_RB_WPTR_HI
#define VPEC_QUEUE3_RB_WPTR_HI__OFFSET_MASK                0xffffffffUL

// VPEC_QUEUE3_RB_RPTR_ADDR_HI
#define VPEC_QUEUE3_RB_RPTR_ADDR_HI__ADDR_MASK             0xffffffffUL

// VPEC_QUEUE3_RB_RPTR_ADDR_LO
#define VPEC_QUEUE3_RB_RPTR_ADDR_LO__ADDR_MASK             0xfffffffcUL

// VPEC_QUEUE3_RB_AQL_CNTL
#define VPEC_QUEUE3_RB_AQL_CNTL__AQL_ENABLE_MASK           0x00000001UL
#define VPEC_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK      0x000000feUL
#define VPEC_QUEUE3_RB_AQL_CNTL__PACKET_STEP_MASK          0x0000ff00UL
#define VPEC_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000UL
#define VPEC_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000UL
#define VPEC_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE_MASK       0x00040000UL

// VPEC_QUEUE3_MINOR_PTR_UPDATE
#define VPEC_QUEUE3_MINOR_PTR_UPDATE__ENABLE_MASK          0x00000001UL

// VPEC_QUEUE3_CD_INFO
#define VPEC_QUEUE3_CD_INFO__CD_INFO_MASK                  0xffffffffUL

// VPEC_QUEUE3_RB_PREEMPT
#define VPEC_QUEUE3_RB_PREEMPT__PREEMPT_REQ_MASK           0x00000001UL

// VPEC_QUEUE3_SKIP_CNTL
#define VPEC_QUEUE3_SKIP_CNTL__SKIP_COUNT_MASK             0x000fffffUL

// VPEC_QUEUE3_DOORBELL
#define VPEC_QUEUE3_DOORBELL__ENABLE_MASK                  0x10000000UL
#define VPEC_QUEUE3_DOORBELL__CAPTURED_MASK                0x40000000UL

// VPEC_QUEUE3_DOORBELL_OFFSET
#define VPEC_QUEUE3_DOORBELL_OFFSET__OFFSET_MASK           0x0ffffffcUL

// VPEC_QUEUE3_DUMMY0
#define VPEC_QUEUE3_DUMMY0__DUMMY_MASK                     0xffffffffUL

// VPEC_QUEUE3_DUMMY1
#define VPEC_QUEUE3_DUMMY1__VALUE_MASK                     0xffffffffUL

// VPEC_QUEUE3_DUMMY2
#define VPEC_QUEUE3_DUMMY2__VALUE_MASK                     0xffffffffUL

// VPEC_QUEUE3_DUMMY3
#define VPEC_QUEUE3_DUMMY3__VALUE_MASK                     0xffffffffUL

// VPEC_QUEUE3_DUMMY4
#define VPEC_QUEUE3_DUMMY4__VALUE_MASK                     0xffffffffUL

// VPEC_QUEUE3_IB_CNTL
#define VPEC_QUEUE3_IB_CNTL__IB_ENABLE_MASK                0x00000001UL
#define VPEC_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB_MASK         0x00000100UL
#define VPEC_QUEUE3_IB_CNTL__CMD_VMID_MASK                 0x000f0000UL
#define VPEC_QUEUE3_IB_CNTL__IB_PRIV_MASK                  0x80000000UL

// VPEC_QUEUE3_IB_RPTR
#define VPEC_QUEUE3_IB_RPTR__OFFSET_MASK                   0x003ffffcUL

// VPEC_QUEUE3_IB_OFFSET
#define VPEC_QUEUE3_IB_OFFSET__OFFSET_MASK                 0x003ffffcUL

// VPEC_QUEUE3_IB_BASE_LO
#define VPEC_QUEUE3_IB_BASE_LO__ADDR_MASK                  0xffffffe0UL

// VPEC_QUEUE3_IB_BASE_HI
#define VPEC_QUEUE3_IB_BASE_HI__ADDR_MASK                  0xffffffffUL

// VPEC_QUEUE3_IB_SIZE
#define VPEC_QUEUE3_IB_SIZE__SIZE_MASK                     0x000fffffUL

// VPEC_QUEUE3_CMDIB_CNTL
#define VPEC_QUEUE3_CMDIB_CNTL__IB_ENABLE_MASK             0x00000001UL
#define VPEC_QUEUE3_CMDIB_CNTL__IB_SWAP_ENABLE_MASK        0x00000010UL
#define VPEC_QUEUE3_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK      0x00000100UL
#define VPEC_QUEUE3_CMDIB_CNTL__CMD_VMID_MASK              0x000f0000UL
#define VPEC_QUEUE3_CMDIB_CNTL__IB_PRIV_MASK               0x80000000UL

// VPEC_QUEUE3_CMDIB_RPTR
#define VPEC_QUEUE3_CMDIB_RPTR__OFFSET_MASK                0x003ffffcUL

// VPEC_QUEUE3_CMDIB_OFFSET
#define VPEC_QUEUE3_CMDIB_OFFSET__OFFSET_MASK              0x003ffffcUL

// VPEC_QUEUE3_CMDIB_BASE_LO
#define VPEC_QUEUE3_CMDIB_BASE_LO__ADDR_MASK               0xffffffe0UL

// VPEC_QUEUE3_CMDIB_BASE_HI
#define VPEC_QUEUE3_CMDIB_BASE_HI__ADDR_MASK               0xffffffffUL

// VPEC_QUEUE3_CMDIB_SIZE
#define VPEC_QUEUE3_CMDIB_SIZE__SIZE_MASK                  0x000fffffUL

// VPEC_QUEUE3_3DLUTIB_CNTL
#define VPEC_QUEUE3_3DLUTIB_CNTL__IB_ENABLE_MASK           0x00000001UL
#define VPEC_QUEUE3_3DLUTIB_CNTL__SWITCH_INSIDE_IB_MASK    0x00000100UL
#define VPEC_QUEUE3_3DLUTIB_CNTL__CMD_VMID_MASK            0x000f0000UL
#define VPEC_QUEUE3_3DLUTIB_CNTL__IB_PRIV_MASK             0x80000000UL

// VPEC_QUEUE3_3DLUTIB_RPTR
#define VPEC_QUEUE3_3DLUTIB_RPTR__OFFSET_MASK              0x003ffffcUL

// VPEC_QUEUE3_3DLUTIB_OFFSET
#define VPEC_QUEUE3_3DLUTIB_OFFSET__OFFSET_MASK            0x003ffffcUL

// VPEC_QUEUE3_3DLUTIB_BASE_LO
#define VPEC_QUEUE3_3DLUTIB_BASE_LO__ADDR_MASK             0xffffffe0UL

// VPEC_QUEUE3_3DLUTIB_BASE_HI
#define VPEC_QUEUE3_3DLUTIB_BASE_HI__ADDR_MASK             0xffffffffUL

// VPEC_QUEUE3_3DLUTIB_SIZE
#define VPEC_QUEUE3_3DLUTIB_SIZE__SIZE_MASK                0x000fffffUL

// VPEC_QUEUE3_CSA_ADDR_LO
#define VPEC_QUEUE3_CSA_ADDR_LO__ADDR_MASK                 0xffffffffUL

// VPEC_QUEUE3_CSA_ADDR_HI
#define VPEC_QUEUE3_CSA_ADDR_HI__ADDR_MASK                 0xffffffffUL

// VPEC_QUEUE3_CONTEXT_STATUS
#define VPEC_QUEUE3_CONTEXT_STATUS__SELECTED_MASK          0x00000001UL
#define VPEC_QUEUE3_CONTEXT_STATUS__USE_IB_MASK            0x00000002UL
#define VPEC_QUEUE3_CONTEXT_STATUS__IDLE_MASK              0x00000004UL
#define VPEC_QUEUE3_CONTEXT_STATUS__EXPIRED_MASK           0x00000008UL
#define VPEC_QUEUE3_CONTEXT_STATUS__EXCEPTION_MASK         0x00000070UL
#define VPEC_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE_MASK        0x00000080UL
#define VPEC_QUEUE3_CONTEXT_STATUS__USE_3DLUTIB_MASK       0x00000100UL
#define VPEC_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK   0x00000400UL
#define VPEC_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE_MASK      0x00000800UL
#define VPEC_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000UL
#define VPEC_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00ff0000UL

// VPEC_QUEUE3_DOORBELL_LOG
#define VPEC_QUEUE3_DOORBELL_LOG__BE_ERROR_MASK            0x00000001UL
#define VPEC_QUEUE3_DOORBELL_LOG__DATA_MASK                0xfffffffcUL

// VPEC_QUEUE3_IB_SUB_REMAIN
#define VPEC_QUEUE3_IB_SUB_REMAIN__SIZE_MASK               0x00003fffUL

// VPEC_QUEUE3_PREEMPT
#define VPEC_QUEUE3_PREEMPT__IB_PREEMPT_MASK               0x00000001UL

// VPEC_QUEUE3_LOG0BUFFER_CFG
#define VPEC_QUEUE3_LOG0BUFFER_CFG__ENABLE_MASK            0x00000001UL
#define VPEC_QUEUE3_LOG0BUFFER_CFG__FIRST_FREE_ENTRY_MASK  0x00000ff0UL
#define VPEC_QUEUE3_LOG0BUFFER_CFG__LAST_FREE_ENTRY_MASK   0x000ff000UL
#define VPEC_QUEUE3_LOG0BUFFER_CFG__RESERVED_MASK          0xfff00000UL

// VPEC_QUEUE3_LOG1BUFFER_CFG
#define VPEC_QUEUE3_LOG1BUFFER_CFG__ENABLE_MASK            0x00000001UL
#define VPEC_QUEUE3_LOG1BUFFER_CFG__PARTIAL_ENTRY_MASK     0x00000002UL
#define VPEC_QUEUE3_LOG1BUFFER_CFG__FIRST_FREE_ENTRY_MASK  0x00000ff0UL
#define VPEC_QUEUE3_LOG1BUFFER_CFG__LAST_FREE_ENTRY_MASK   0x000ff000UL
#define VPEC_QUEUE3_LOG1BUFFER_CFG__RESERVED_MASK          0xfff00000UL

// VPEC_QUEUE4_RB_CNTL
#define VPEC_QUEUE4_RB_CNTL__RB_ENABLE_MASK                0x00000001UL
#define VPEC_QUEUE4_RB_CNTL__RB_SIZE_MASK                  0x0000003eUL
#define VPEC_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE_MASK         0x00000100UL
#define VPEC_QUEUE4_RB_CNTL__RB_SWAP_ENABLE_MASK           0x00000200UL
#define VPEC_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK    0x00000400UL
#define VPEC_QUEUE4_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK     0x00000800UL
#define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK    0x00001000UL
#define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000UL
#define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK     0x001f0000UL
#define VPEC_QUEUE4_RB_CNTL__RB_PRIV_MASK                  0x00800000UL
#define VPEC_QUEUE4_RB_CNTL__RB_VMID_MASK                  0x0f000000UL

// VPEC_QUEUE4_SCHEDULE_CNTL
#define VPEC_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID_MASK          0x00000003UL
#define VPEC_QUEUE4_SCHEDULE_CNTL__PROCESS_ID_MASK         0x0000001cUL
#define VPEC_QUEUE4_SCHEDULE_CNTL__LOCAL_ID_MASK           0x000000c0UL
#define VPEC_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK    0x0000ff00UL

// VPEC_QUEUE4_RB_BASE
#define VPEC_QUEUE4_RB_BASE__ADDR_MASK                     0xffffffffUL

// VPEC_QUEUE4_RB_BASE_HI
#define VPEC_QUEUE4_RB_BASE_HI__ADDR_MASK                  0x00ffffffUL

// VPEC_QUEUE4_RB_RPTR
#define VPEC_QUEUE4_RB_RPTR__OFFSET_MASK                   0xffffffffUL

// VPEC_QUEUE4_RB_RPTR_HI
#define VPEC_QUEUE4_RB_RPTR_HI__OFFSET_MASK                0xffffffffUL

// VPEC_QUEUE4_RB_WPTR
#define VPEC_QUEUE4_RB_WPTR__OFFSET_MASK                   0xffffffffUL

// VPEC_QUEUE4_RB_WPTR_HI
#define VPEC_QUEUE4_RB_WPTR_HI__OFFSET_MASK                0xffffffffUL

// VPEC_QUEUE4_RB_RPTR_ADDR_HI
#define VPEC_QUEUE4_RB_RPTR_ADDR_HI__ADDR_MASK             0xffffffffUL

// VPEC_QUEUE4_RB_RPTR_ADDR_LO
#define VPEC_QUEUE4_RB_RPTR_ADDR_LO__ADDR_MASK             0xfffffffcUL

// VPEC_QUEUE4_RB_AQL_CNTL
#define VPEC_QUEUE4_RB_AQL_CNTL__AQL_ENABLE_MASK           0x00000001UL
#define VPEC_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK      0x000000feUL
#define VPEC_QUEUE4_RB_AQL_CNTL__PACKET_STEP_MASK          0x0000ff00UL
#define VPEC_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000UL
#define VPEC_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000UL
#define VPEC_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE_MASK       0x00040000UL

// VPEC_QUEUE4_MINOR_PTR_UPDATE
#define VPEC_QUEUE4_MINOR_PTR_UPDATE__ENABLE_MASK          0x00000001UL

// VPEC_QUEUE4_CD_INFO
#define VPEC_QUEUE4_CD_INFO__CD_INFO_MASK                  0xffffffffUL

// VPEC_QUEUE4_RB_PREEMPT
#define VPEC_QUEUE4_RB_PREEMPT__PREEMPT_REQ_MASK           0x00000001UL

// VPEC_QUEUE4_SKIP_CNTL
#define VPEC_QUEUE4_SKIP_CNTL__SKIP_COUNT_MASK             0x000fffffUL

// VPEC_QUEUE4_DOORBELL
#define VPEC_QUEUE4_DOORBELL__ENABLE_MASK                  0x10000000UL
#define VPEC_QUEUE4_DOORBELL__CAPTURED_MASK                0x40000000UL

// VPEC_QUEUE4_DOORBELL_OFFSET
#define VPEC_QUEUE4_DOORBELL_OFFSET__OFFSET_MASK           0x0ffffffcUL

// VPEC_QUEUE4_DUMMY0
#define VPEC_QUEUE4_DUMMY0__DUMMY_MASK                     0xffffffffUL

// VPEC_QUEUE4_DUMMY1
#define VPEC_QUEUE4_DUMMY1__VALUE_MASK                     0xffffffffUL

// VPEC_QUEUE4_DUMMY2
#define VPEC_QUEUE4_DUMMY2__VALUE_MASK                     0xffffffffUL

// VPEC_QUEUE4_DUMMY3
#define VPEC_QUEUE4_DUMMY3__VALUE_MASK                     0xffffffffUL

// VPEC_QUEUE4_DUMMY4
#define VPEC_QUEUE4_DUMMY4__VALUE_MASK                     0xffffffffUL

// VPEC_QUEUE4_IB_CNTL
#define VPEC_QUEUE4_IB_CNTL__IB_ENABLE_MASK                0x00000001UL
#define VPEC_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB_MASK         0x00000100UL
#define VPEC_QUEUE4_IB_CNTL__CMD_VMID_MASK                 0x000f0000UL
#define VPEC_QUEUE4_IB_CNTL__IB_PRIV_MASK                  0x80000000UL

// VPEC_QUEUE4_IB_RPTR
#define VPEC_QUEUE4_IB_RPTR__OFFSET_MASK                   0x003ffffcUL

// VPEC_QUEUE4_IB_OFFSET
#define VPEC_QUEUE4_IB_OFFSET__OFFSET_MASK                 0x003ffffcUL

// VPEC_QUEUE4_IB_BASE_LO
#define VPEC_QUEUE4_IB_BASE_LO__ADDR_MASK                  0xffffffe0UL

// VPEC_QUEUE4_IB_BASE_HI
#define VPEC_QUEUE4_IB_BASE_HI__ADDR_MASK                  0xffffffffUL

// VPEC_QUEUE4_IB_SIZE
#define VPEC_QUEUE4_IB_SIZE__SIZE_MASK                     0x000fffffUL

// VPEC_QUEUE4_CMDIB_CNTL
#define VPEC_QUEUE4_CMDIB_CNTL__IB_ENABLE_MASK             0x00000001UL
#define VPEC_QUEUE4_CMDIB_CNTL__IB_SWAP_ENABLE_MASK        0x00000010UL
#define VPEC_QUEUE4_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK      0x00000100UL
#define VPEC_QUEUE4_CMDIB_CNTL__CMD_VMID_MASK              0x000f0000UL
#define VPEC_QUEUE4_CMDIB_CNTL__IB_PRIV_MASK               0x80000000UL

// VPEC_QUEUE4_CMDIB_RPTR
#define VPEC_QUEUE4_CMDIB_RPTR__OFFSET_MASK                0x003ffffcUL

// VPEC_QUEUE4_CMDIB_OFFSET
#define VPEC_QUEUE4_CMDIB_OFFSET__OFFSET_MASK              0x003ffffcUL

// VPEC_QUEUE4_CMDIB_BASE_LO
#define VPEC_QUEUE4_CMDIB_BASE_LO__ADDR_MASK               0xffffffe0UL

// VPEC_QUEUE4_CMDIB_BASE_HI
#define VPEC_QUEUE4_CMDIB_BASE_HI__ADDR_MASK               0xffffffffUL

// VPEC_QUEUE4_CMDIB_SIZE
#define VPEC_QUEUE4_CMDIB_SIZE__SIZE_MASK                  0x000fffffUL

// VPEC_QUEUE4_3DLUTIB_CNTL
#define VPEC_QUEUE4_3DLUTIB_CNTL__IB_ENABLE_MASK           0x00000001UL
#define VPEC_QUEUE4_3DLUTIB_CNTL__SWITCH_INSIDE_IB_MASK    0x00000100UL
#define VPEC_QUEUE4_3DLUTIB_CNTL__CMD_VMID_MASK            0x000f0000UL
#define VPEC_QUEUE4_3DLUTIB_CNTL__IB_PRIV_MASK             0x80000000UL

// VPEC_QUEUE4_3DLUTIB_RPTR
#define VPEC_QUEUE4_3DLUTIB_RPTR__OFFSET_MASK              0x003ffffcUL

// VPEC_QUEUE4_3DLUTIB_OFFSET
#define VPEC_QUEUE4_3DLUTIB_OFFSET__OFFSET_MASK            0x003ffffcUL

// VPEC_QUEUE4_3DLUTIB_BASE_LO
#define VPEC_QUEUE4_3DLUTIB_BASE_LO__ADDR_MASK             0xffffffe0UL

// VPEC_QUEUE4_3DLUTIB_BASE_HI
#define VPEC_QUEUE4_3DLUTIB_BASE_HI__ADDR_MASK             0xffffffffUL

// VPEC_QUEUE4_3DLUTIB_SIZE
#define VPEC_QUEUE4_3DLUTIB_SIZE__SIZE_MASK                0x000fffffUL

// VPEC_QUEUE4_CSA_ADDR_LO
#define VPEC_QUEUE4_CSA_ADDR_LO__ADDR_MASK                 0xffffffffUL

// VPEC_QUEUE4_CSA_ADDR_HI
#define VPEC_QUEUE4_CSA_ADDR_HI__ADDR_MASK                 0xffffffffUL

// VPEC_QUEUE4_CONTEXT_STATUS
#define VPEC_QUEUE4_CONTEXT_STATUS__SELECTED_MASK          0x00000001UL
#define VPEC_QUEUE4_CONTEXT_STATUS__USE_IB_MASK            0x00000002UL
#define VPEC_QUEUE4_CONTEXT_STATUS__IDLE_MASK              0x00000004UL
#define VPEC_QUEUE4_CONTEXT_STATUS__EXPIRED_MASK           0x00000008UL
#define VPEC_QUEUE4_CONTEXT_STATUS__EXCEPTION_MASK         0x00000070UL
#define VPEC_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE_MASK        0x00000080UL
#define VPEC_QUEUE4_CONTEXT_STATUS__USE_3DLUTIB_MASK       0x00000100UL
#define VPEC_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK   0x00000400UL
#define VPEC_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE_MASK      0x00000800UL
#define VPEC_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000UL
#define VPEC_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00ff0000UL

// VPEC_QUEUE4_DOORBELL_LOG
#define VPEC_QUEUE4_DOORBELL_LOG__BE_ERROR_MASK            0x00000001UL
#define VPEC_QUEUE4_DOORBELL_LOG__DATA_MASK                0xfffffffcUL

// VPEC_QUEUE4_IB_SUB_REMAIN
#define VPEC_QUEUE4_IB_SUB_REMAIN__SIZE_MASK               0x00003fffUL

// VPEC_QUEUE4_PREEMPT
#define VPEC_QUEUE4_PREEMPT__IB_PREEMPT_MASK               0x00000001UL

// VPEC_QUEUE4_LOG0BUFFER_CFG
#define VPEC_QUEUE4_LOG0BUFFER_CFG__ENABLE_MASK            0x00000001UL
#define VPEC_QUEUE4_LOG0BUFFER_CFG__FIRST_FREE_ENTRY_MASK  0x00000ff0UL
#define VPEC_QUEUE4_LOG0BUFFER_CFG__LAST_FREE_ENTRY_MASK   0x000ff000UL
#define VPEC_QUEUE4_LOG0BUFFER_CFG__RESERVED_MASK          0xfff00000UL

// VPEC_QUEUE4_LOG1BUFFER_CFG
#define VPEC_QUEUE4_LOG1BUFFER_CFG__ENABLE_MASK            0x00000001UL
#define VPEC_QUEUE4_LOG1BUFFER_CFG__PARTIAL_ENTRY_MASK     0x00000002UL
#define VPEC_QUEUE4_LOG1BUFFER_CFG__FIRST_FREE_ENTRY_MASK  0x00000ff0UL
#define VPEC_QUEUE4_LOG1BUFFER_CFG__LAST_FREE_ENTRY_MASK   0x000ff000UL
#define VPEC_QUEUE4_LOG1BUFFER_CFG__RESERVED_MASK          0xfff00000UL

// VPEC_QUEUE5_RB_CNTL
#define VPEC_QUEUE5_RB_CNTL__RB_ENABLE_MASK                0x00000001UL
#define VPEC_QUEUE5_RB_CNTL__RB_SIZE_MASK                  0x0000003eUL
#define VPEC_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE_MASK         0x00000100UL
#define VPEC_QUEUE5_RB_CNTL__RB_SWAP_ENABLE_MASK           0x00000200UL
#define VPEC_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK    0x00000400UL
#define VPEC_QUEUE5_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK     0x00000800UL
#define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK    0x00001000UL
#define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000UL
#define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK     0x001f0000UL
#define VPEC_QUEUE5_RB_CNTL__RB_PRIV_MASK                  0x00800000UL
#define VPEC_QUEUE5_RB_CNTL__RB_VMID_MASK                  0x0f000000UL

// VPEC_QUEUE5_SCHEDULE_CNTL
#define VPEC_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID_MASK          0x00000003UL
#define VPEC_QUEUE5_SCHEDULE_CNTL__PROCESS_ID_MASK         0x0000001cUL
#define VPEC_QUEUE5_SCHEDULE_CNTL__LOCAL_ID_MASK           0x000000c0UL
#define VPEC_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK    0x0000ff00UL

// VPEC_QUEUE5_RB_BASE
#define VPEC_QUEUE5_RB_BASE__ADDR_MASK                     0xffffffffUL

// VPEC_QUEUE5_RB_BASE_HI
#define VPEC_QUEUE5_RB_BASE_HI__ADDR_MASK                  0x00ffffffUL

// VPEC_QUEUE5_RB_RPTR
#define VPEC_QUEUE5_RB_RPTR__OFFSET_MASK                   0xffffffffUL

// VPEC_QUEUE5_RB_RPTR_HI
#define VPEC_QUEUE5_RB_RPTR_HI__OFFSET_MASK                0xffffffffUL

// VPEC_QUEUE5_RB_WPTR
#define VPEC_QUEUE5_RB_WPTR__OFFSET_MASK                   0xffffffffUL

// VPEC_QUEUE5_RB_WPTR_HI
#define VPEC_QUEUE5_RB_WPTR_HI__OFFSET_MASK                0xffffffffUL

// VPEC_QUEUE5_RB_RPTR_ADDR_HI
#define VPEC_QUEUE5_RB_RPTR_ADDR_HI__ADDR_MASK             0xffffffffUL

// VPEC_QUEUE5_RB_RPTR_ADDR_LO
#define VPEC_QUEUE5_RB_RPTR_ADDR_LO__ADDR_MASK             0xfffffffcUL

// VPEC_QUEUE5_RB_AQL_CNTL
#define VPEC_QUEUE5_RB_AQL_CNTL__AQL_ENABLE_MASK           0x00000001UL
#define VPEC_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK      0x000000feUL
#define VPEC_QUEUE5_RB_AQL_CNTL__PACKET_STEP_MASK          0x0000ff00UL
#define VPEC_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000UL
#define VPEC_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000UL
#define VPEC_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE_MASK       0x00040000UL

// VPEC_QUEUE5_MINOR_PTR_UPDATE
#define VPEC_QUEUE5_MINOR_PTR_UPDATE__ENABLE_MASK          0x00000001UL

// VPEC_QUEUE5_CD_INFO
#define VPEC_QUEUE5_CD_INFO__CD_INFO_MASK                  0xffffffffUL

// VPEC_QUEUE5_RB_PREEMPT
#define VPEC_QUEUE5_RB_PREEMPT__PREEMPT_REQ_MASK           0x00000001UL

// VPEC_QUEUE5_SKIP_CNTL
#define VPEC_QUEUE5_SKIP_CNTL__SKIP_COUNT_MASK             0x000fffffUL

// VPEC_QUEUE5_DOORBELL
#define VPEC_QUEUE5_DOORBELL__ENABLE_MASK                  0x10000000UL
#define VPEC_QUEUE5_DOORBELL__CAPTURED_MASK                0x40000000UL

// VPEC_QUEUE5_DOORBELL_OFFSET
#define VPEC_QUEUE5_DOORBELL_OFFSET__OFFSET_MASK           0x0ffffffcUL

// VPEC_QUEUE5_DUMMY0
#define VPEC_QUEUE5_DUMMY0__DUMMY_MASK                     0xffffffffUL

// VPEC_QUEUE5_DUMMY1
#define VPEC_QUEUE5_DUMMY1__VALUE_MASK                     0xffffffffUL

// VPEC_QUEUE5_DUMMY2
#define VPEC_QUEUE5_DUMMY2__VALUE_MASK                     0xffffffffUL

// VPEC_QUEUE5_DUMMY3
#define VPEC_QUEUE5_DUMMY3__VALUE_MASK                     0xffffffffUL

// VPEC_QUEUE5_DUMMY4
#define VPEC_QUEUE5_DUMMY4__VALUE_MASK                     0xffffffffUL

// VPEC_QUEUE5_IB_CNTL
#define VPEC_QUEUE5_IB_CNTL__IB_ENABLE_MASK                0x00000001UL
#define VPEC_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB_MASK         0x00000100UL
#define VPEC_QUEUE5_IB_CNTL__CMD_VMID_MASK                 0x000f0000UL
#define VPEC_QUEUE5_IB_CNTL__IB_PRIV_MASK                  0x80000000UL

// VPEC_QUEUE5_IB_RPTR
#define VPEC_QUEUE5_IB_RPTR__OFFSET_MASK                   0x003ffffcUL

// VPEC_QUEUE5_IB_OFFSET
#define VPEC_QUEUE5_IB_OFFSET__OFFSET_MASK                 0x003ffffcUL

// VPEC_QUEUE5_IB_BASE_LO
#define VPEC_QUEUE5_IB_BASE_LO__ADDR_MASK                  0xffffffe0UL

// VPEC_QUEUE5_IB_BASE_HI
#define VPEC_QUEUE5_IB_BASE_HI__ADDR_MASK                  0xffffffffUL

// VPEC_QUEUE5_IB_SIZE
#define VPEC_QUEUE5_IB_SIZE__SIZE_MASK                     0x000fffffUL

// VPEC_QUEUE5_CMDIB_CNTL
#define VPEC_QUEUE5_CMDIB_CNTL__IB_ENABLE_MASK             0x00000001UL
#define VPEC_QUEUE5_CMDIB_CNTL__IB_SWAP_ENABLE_MASK        0x00000010UL
#define VPEC_QUEUE5_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK      0x00000100UL
#define VPEC_QUEUE5_CMDIB_CNTL__CMD_VMID_MASK              0x000f0000UL
#define VPEC_QUEUE5_CMDIB_CNTL__IB_PRIV_MASK               0x80000000UL

// VPEC_QUEUE5_CMDIB_RPTR
#define VPEC_QUEUE5_CMDIB_RPTR__OFFSET_MASK                0x003ffffcUL

// VPEC_QUEUE5_CMDIB_OFFSET
#define VPEC_QUEUE5_CMDIB_OFFSET__OFFSET_MASK              0x003ffffcUL

// VPEC_QUEUE5_CMDIB_BASE_LO
#define VPEC_QUEUE5_CMDIB_BASE_LO__ADDR_MASK               0xffffffe0UL

// VPEC_QUEUE5_CMDIB_BASE_HI
#define VPEC_QUEUE5_CMDIB_BASE_HI__ADDR_MASK               0xffffffffUL

// VPEC_QUEUE5_CMDIB_SIZE
#define VPEC_QUEUE5_CMDIB_SIZE__SIZE_MASK                  0x000fffffUL

// VPEC_QUEUE5_3DLUTIB_CNTL
#define VPEC_QUEUE5_3DLUTIB_CNTL__IB_ENABLE_MASK           0x00000001UL
#define VPEC_QUEUE5_3DLUTIB_CNTL__SWITCH_INSIDE_IB_MASK    0x00000100UL
#define VPEC_QUEUE5_3DLUTIB_CNTL__CMD_VMID_MASK            0x000f0000UL
#define VPEC_QUEUE5_3DLUTIB_CNTL__IB_PRIV_MASK             0x80000000UL

// VPEC_QUEUE5_3DLUTIB_RPTR
#define VPEC_QUEUE5_3DLUTIB_RPTR__OFFSET_MASK              0x003ffffcUL

// VPEC_QUEUE5_3DLUTIB_OFFSET
#define VPEC_QUEUE5_3DLUTIB_OFFSET__OFFSET_MASK            0x003ffffcUL

// VPEC_QUEUE5_3DLUTIB_BASE_LO
#define VPEC_QUEUE5_3DLUTIB_BASE_LO__ADDR_MASK             0xffffffe0UL

// VPEC_QUEUE5_3DLUTIB_BASE_HI
#define VPEC_QUEUE5_3DLUTIB_BASE_HI__ADDR_MASK             0xffffffffUL

// VPEC_QUEUE5_3DLUTIB_SIZE
#define VPEC_QUEUE5_3DLUTIB_SIZE__SIZE_MASK                0x000fffffUL

// VPEC_QUEUE5_CSA_ADDR_LO
#define VPEC_QUEUE5_CSA_ADDR_LO__ADDR_MASK                 0xffffffffUL

// VPEC_QUEUE5_CSA_ADDR_HI
#define VPEC_QUEUE5_CSA_ADDR_HI__ADDR_MASK                 0xffffffffUL

// VPEC_QUEUE5_CONTEXT_STATUS
#define VPEC_QUEUE5_CONTEXT_STATUS__SELECTED_MASK          0x00000001UL
#define VPEC_QUEUE5_CONTEXT_STATUS__USE_IB_MASK            0x00000002UL
#define VPEC_QUEUE5_CONTEXT_STATUS__IDLE_MASK              0x00000004UL
#define VPEC_QUEUE5_CONTEXT_STATUS__EXPIRED_MASK           0x00000008UL
#define VPEC_QUEUE5_CONTEXT_STATUS__EXCEPTION_MASK         0x00000070UL
#define VPEC_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE_MASK        0x00000080UL
#define VPEC_QUEUE5_CONTEXT_STATUS__USE_3DLUTIB_MASK       0x00000100UL
#define VPEC_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK   0x00000400UL
#define VPEC_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE_MASK      0x00000800UL
#define VPEC_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000UL
#define VPEC_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00ff0000UL

// VPEC_QUEUE5_DOORBELL_LOG
#define VPEC_QUEUE5_DOORBELL_LOG__BE_ERROR_MASK            0x00000001UL
#define VPEC_QUEUE5_DOORBELL_LOG__DATA_MASK                0xfffffffcUL

// VPEC_QUEUE5_IB_SUB_REMAIN
#define VPEC_QUEUE5_IB_SUB_REMAIN__SIZE_MASK               0x00003fffUL

// VPEC_QUEUE5_PREEMPT
#define VPEC_QUEUE5_PREEMPT__IB_PREEMPT_MASK               0x00000001UL

// VPEC_QUEUE5_LOG0BUFFER_CFG
#define VPEC_QUEUE5_LOG0BUFFER_CFG__ENABLE_MASK            0x00000001UL
#define VPEC_QUEUE5_LOG0BUFFER_CFG__FIRST_FREE_ENTRY_MASK  0x00000ff0UL
#define VPEC_QUEUE5_LOG0BUFFER_CFG__LAST_FREE_ENTRY_MASK   0x000ff000UL
#define VPEC_QUEUE5_LOG0BUFFER_CFG__RESERVED_MASK          0xfff00000UL

// VPEC_QUEUE5_LOG1BUFFER_CFG
#define VPEC_QUEUE5_LOG1BUFFER_CFG__ENABLE_MASK            0x00000001UL
#define VPEC_QUEUE5_LOG1BUFFER_CFG__PARTIAL_ENTRY_MASK     0x00000002UL
#define VPEC_QUEUE5_LOG1BUFFER_CFG__FIRST_FREE_ENTRY_MASK  0x00000ff0UL
#define VPEC_QUEUE5_LOG1BUFFER_CFG__LAST_FREE_ENTRY_MASK   0x000ff000UL
#define VPEC_QUEUE5_LOG1BUFFER_CFG__RESERVED_MASK          0xfff00000UL

// VPEC_QUEUE6_RB_CNTL
#define VPEC_QUEUE6_RB_CNTL__RB_ENABLE_MASK                0x00000001UL
#define VPEC_QUEUE6_RB_CNTL__RB_SIZE_MASK                  0x0000003eUL
#define VPEC_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE_MASK         0x00000100UL
#define VPEC_QUEUE6_RB_CNTL__RB_SWAP_ENABLE_MASK           0x00000200UL
#define VPEC_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK    0x00000400UL
#define VPEC_QUEUE6_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK     0x00000800UL
#define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK    0x00001000UL
#define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000UL
#define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK     0x001f0000UL
#define VPEC_QUEUE6_RB_CNTL__RB_PRIV_MASK                  0x00800000UL
#define VPEC_QUEUE6_RB_CNTL__RB_VMID_MASK                  0x0f000000UL

// VPEC_QUEUE6_SCHEDULE_CNTL
#define VPEC_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID_MASK          0x00000003UL
#define VPEC_QUEUE6_SCHEDULE_CNTL__PROCESS_ID_MASK         0x0000001cUL
#define VPEC_QUEUE6_SCHEDULE_CNTL__LOCAL_ID_MASK           0x000000c0UL
#define VPEC_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK    0x0000ff00UL

// VPEC_QUEUE6_RB_BASE
#define VPEC_QUEUE6_RB_BASE__ADDR_MASK                     0xffffffffUL

// VPEC_QUEUE6_RB_BASE_HI
#define VPEC_QUEUE6_RB_BASE_HI__ADDR_MASK                  0x00ffffffUL

// VPEC_QUEUE6_RB_RPTR
#define VPEC_QUEUE6_RB_RPTR__OFFSET_MASK                   0xffffffffUL

// VPEC_QUEUE6_RB_RPTR_HI
#define VPEC_QUEUE6_RB_RPTR_HI__OFFSET_MASK                0xffffffffUL

// VPEC_QUEUE6_RB_WPTR
#define VPEC_QUEUE6_RB_WPTR__OFFSET_MASK                   0xffffffffUL

// VPEC_QUEUE6_RB_WPTR_HI
#define VPEC_QUEUE6_RB_WPTR_HI__OFFSET_MASK                0xffffffffUL

// VPEC_QUEUE6_RB_RPTR_ADDR_HI
#define VPEC_QUEUE6_RB_RPTR_ADDR_HI__ADDR_MASK             0xffffffffUL

// VPEC_QUEUE6_RB_RPTR_ADDR_LO
#define VPEC_QUEUE6_RB_RPTR_ADDR_LO__ADDR_MASK             0xfffffffcUL

// VPEC_QUEUE6_RB_AQL_CNTL
#define VPEC_QUEUE6_RB_AQL_CNTL__AQL_ENABLE_MASK           0x00000001UL
#define VPEC_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK      0x000000feUL
#define VPEC_QUEUE6_RB_AQL_CNTL__PACKET_STEP_MASK          0x0000ff00UL
#define VPEC_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000UL
#define VPEC_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000UL
#define VPEC_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE_MASK       0x00040000UL

// VPEC_QUEUE6_MINOR_PTR_UPDATE
#define VPEC_QUEUE6_MINOR_PTR_UPDATE__ENABLE_MASK          0x00000001UL

// VPEC_QUEUE6_CD_INFO
#define VPEC_QUEUE6_CD_INFO__CD_INFO_MASK                  0xffffffffUL

// VPEC_QUEUE6_RB_PREEMPT
#define VPEC_QUEUE6_RB_PREEMPT__PREEMPT_REQ_MASK           0x00000001UL

// VPEC_QUEUE6_SKIP_CNTL
#define VPEC_QUEUE6_SKIP_CNTL__SKIP_COUNT_MASK             0x000fffffUL

// VPEC_QUEUE6_DOORBELL
#define VPEC_QUEUE6_DOORBELL__ENABLE_MASK                  0x10000000UL
#define VPEC_QUEUE6_DOORBELL__CAPTURED_MASK                0x40000000UL

// VPEC_QUEUE6_DOORBELL_OFFSET
#define VPEC_QUEUE6_DOORBELL_OFFSET__OFFSET_MASK           0x0ffffffcUL

// VPEC_QUEUE6_DUMMY0
#define VPEC_QUEUE6_DUMMY0__DUMMY_MASK                     0xffffffffUL

// VPEC_QUEUE6_DUMMY1
#define VPEC_QUEUE6_DUMMY1__VALUE_MASK                     0xffffffffUL

// VPEC_QUEUE6_DUMMY2
#define VPEC_QUEUE6_DUMMY2__VALUE_MASK                     0xffffffffUL

// VPEC_QUEUE6_DUMMY3
#define VPEC_QUEUE6_DUMMY3__VALUE_MASK                     0xffffffffUL

// VPEC_QUEUE6_DUMMY4
#define VPEC_QUEUE6_DUMMY4__VALUE_MASK                     0xffffffffUL

// VPEC_QUEUE6_IB_CNTL
#define VPEC_QUEUE6_IB_CNTL__IB_ENABLE_MASK                0x00000001UL
#define VPEC_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB_MASK         0x00000100UL
#define VPEC_QUEUE6_IB_CNTL__CMD_VMID_MASK                 0x000f0000UL
#define VPEC_QUEUE6_IB_CNTL__IB_PRIV_MASK                  0x80000000UL

// VPEC_QUEUE6_IB_RPTR
#define VPEC_QUEUE6_IB_RPTR__OFFSET_MASK                   0x003ffffcUL

// VPEC_QUEUE6_IB_OFFSET
#define VPEC_QUEUE6_IB_OFFSET__OFFSET_MASK                 0x003ffffcUL

// VPEC_QUEUE6_IB_BASE_LO
#define VPEC_QUEUE6_IB_BASE_LO__ADDR_MASK                  0xffffffe0UL

// VPEC_QUEUE6_IB_BASE_HI
#define VPEC_QUEUE6_IB_BASE_HI__ADDR_MASK                  0xffffffffUL

// VPEC_QUEUE6_IB_SIZE
#define VPEC_QUEUE6_IB_SIZE__SIZE_MASK                     0x000fffffUL

// VPEC_QUEUE6_CMDIB_CNTL
#define VPEC_QUEUE6_CMDIB_CNTL__IB_ENABLE_MASK             0x00000001UL
#define VPEC_QUEUE6_CMDIB_CNTL__IB_SWAP_ENABLE_MASK        0x00000010UL
#define VPEC_QUEUE6_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK      0x00000100UL
#define VPEC_QUEUE6_CMDIB_CNTL__CMD_VMID_MASK              0x000f0000UL
#define VPEC_QUEUE6_CMDIB_CNTL__IB_PRIV_MASK               0x80000000UL

// VPEC_QUEUE6_CMDIB_RPTR
#define VPEC_QUEUE6_CMDIB_RPTR__OFFSET_MASK                0x003ffffcUL

// VPEC_QUEUE6_CMDIB_OFFSET
#define VPEC_QUEUE6_CMDIB_OFFSET__OFFSET_MASK              0x003ffffcUL

// VPEC_QUEUE6_CMDIB_BASE_LO
#define VPEC_QUEUE6_CMDIB_BASE_LO__ADDR_MASK               0xffffffe0UL

// VPEC_QUEUE6_CMDIB_BASE_HI
#define VPEC_QUEUE6_CMDIB_BASE_HI__ADDR_MASK               0xffffffffUL

// VPEC_QUEUE6_CMDIB_SIZE
#define VPEC_QUEUE6_CMDIB_SIZE__SIZE_MASK                  0x000fffffUL

// VPEC_QUEUE6_3DLUTIB_CNTL
#define VPEC_QUEUE6_3DLUTIB_CNTL__IB_ENABLE_MASK           0x00000001UL
#define VPEC_QUEUE6_3DLUTIB_CNTL__SWITCH_INSIDE_IB_MASK    0x00000100UL
#define VPEC_QUEUE6_3DLUTIB_CNTL__CMD_VMID_MASK            0x000f0000UL
#define VPEC_QUEUE6_3DLUTIB_CNTL__IB_PRIV_MASK             0x80000000UL

// VPEC_QUEUE6_3DLUTIB_RPTR
#define VPEC_QUEUE6_3DLUTIB_RPTR__OFFSET_MASK              0x003ffffcUL

// VPEC_QUEUE6_3DLUTIB_OFFSET
#define VPEC_QUEUE6_3DLUTIB_OFFSET__OFFSET_MASK            0x003ffffcUL

// VPEC_QUEUE6_3DLUTIB_BASE_LO
#define VPEC_QUEUE6_3DLUTIB_BASE_LO__ADDR_MASK             0xffffffe0UL

// VPEC_QUEUE6_3DLUTIB_BASE_HI
#define VPEC_QUEUE6_3DLUTIB_BASE_HI__ADDR_MASK             0xffffffffUL

// VPEC_QUEUE6_3DLUTIB_SIZE
#define VPEC_QUEUE6_3DLUTIB_SIZE__SIZE_MASK                0x000fffffUL

// VPEC_QUEUE6_CSA_ADDR_LO
#define VPEC_QUEUE6_CSA_ADDR_LO__ADDR_MASK                 0xffffffffUL

// VPEC_QUEUE6_CSA_ADDR_HI
#define VPEC_QUEUE6_CSA_ADDR_HI__ADDR_MASK                 0xffffffffUL

// VPEC_QUEUE6_CONTEXT_STATUS
#define VPEC_QUEUE6_CONTEXT_STATUS__SELECTED_MASK          0x00000001UL
#define VPEC_QUEUE6_CONTEXT_STATUS__USE_IB_MASK            0x00000002UL
#define VPEC_QUEUE6_CONTEXT_STATUS__IDLE_MASK              0x00000004UL
#define VPEC_QUEUE6_CONTEXT_STATUS__EXPIRED_MASK           0x00000008UL
#define VPEC_QUEUE6_CONTEXT_STATUS__EXCEPTION_MASK         0x00000070UL
#define VPEC_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE_MASK        0x00000080UL
#define VPEC_QUEUE6_CONTEXT_STATUS__USE_3DLUTIB_MASK       0x00000100UL
#define VPEC_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK   0x00000400UL
#define VPEC_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE_MASK      0x00000800UL
#define VPEC_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000UL
#define VPEC_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00ff0000UL

// VPEC_QUEUE6_DOORBELL_LOG
#define VPEC_QUEUE6_DOORBELL_LOG__BE_ERROR_MASK            0x00000001UL
#define VPEC_QUEUE6_DOORBELL_LOG__DATA_MASK                0xfffffffcUL

// VPEC_QUEUE6_IB_SUB_REMAIN
#define VPEC_QUEUE6_IB_SUB_REMAIN__SIZE_MASK               0x00003fffUL

// VPEC_QUEUE6_PREEMPT
#define VPEC_QUEUE6_PREEMPT__IB_PREEMPT_MASK               0x00000001UL

// VPEC_QUEUE6_LOG0BUFFER_CFG
#define VPEC_QUEUE6_LOG0BUFFER_CFG__ENABLE_MASK            0x00000001UL
#define VPEC_QUEUE6_LOG0BUFFER_CFG__FIRST_FREE_ENTRY_MASK  0x00000ff0UL
#define VPEC_QUEUE6_LOG0BUFFER_CFG__LAST_FREE_ENTRY_MASK   0x000ff000UL
#define VPEC_QUEUE6_LOG0BUFFER_CFG__RESERVED_MASK          0xfff00000UL

// VPEC_QUEUE6_LOG1BUFFER_CFG
#define VPEC_QUEUE6_LOG1BUFFER_CFG__ENABLE_MASK            0x00000001UL
#define VPEC_QUEUE6_LOG1BUFFER_CFG__PARTIAL_ENTRY_MASK     0x00000002UL
#define VPEC_QUEUE6_LOG1BUFFER_CFG__FIRST_FREE_ENTRY_MASK  0x00000ff0UL
#define VPEC_QUEUE6_LOG1BUFFER_CFG__LAST_FREE_ENTRY_MASK   0x000ff000UL
#define VPEC_QUEUE6_LOG1BUFFER_CFG__RESERVED_MASK          0xfff00000UL

// VPEC_QUEUE7_RB_CNTL
#define VPEC_QUEUE7_RB_CNTL__RB_ENABLE_MASK                0x00000001UL
#define VPEC_QUEUE7_RB_CNTL__RB_SIZE_MASK                  0x0000003eUL
#define VPEC_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE_MASK         0x00000100UL
#define VPEC_QUEUE7_RB_CNTL__RB_SWAP_ENABLE_MASK           0x00000200UL
#define VPEC_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK    0x00000400UL
#define VPEC_QUEUE7_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK     0x00000800UL
#define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK    0x00001000UL
#define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000UL
#define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK     0x001f0000UL
#define VPEC_QUEUE7_RB_CNTL__RB_PRIV_MASK                  0x00800000UL
#define VPEC_QUEUE7_RB_CNTL__RB_VMID_MASK                  0x0f000000UL

// VPEC_QUEUE7_SCHEDULE_CNTL
#define VPEC_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID_MASK          0x00000003UL
#define VPEC_QUEUE7_SCHEDULE_CNTL__PROCESS_ID_MASK         0x0000001cUL
#define VPEC_QUEUE7_SCHEDULE_CNTL__LOCAL_ID_MASK           0x000000c0UL
#define VPEC_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK    0x0000ff00UL

// VPEC_QUEUE7_RB_BASE
#define VPEC_QUEUE7_RB_BASE__ADDR_MASK                     0xffffffffUL

// VPEC_QUEUE7_RB_BASE_HI
#define VPEC_QUEUE7_RB_BASE_HI__ADDR_MASK                  0x00ffffffUL

// VPEC_QUEUE7_RB_RPTR
#define VPEC_QUEUE7_RB_RPTR__OFFSET_MASK                   0xffffffffUL

// VPEC_QUEUE7_RB_RPTR_HI
#define VPEC_QUEUE7_RB_RPTR_HI__OFFSET_MASK                0xffffffffUL

// VPEC_QUEUE7_RB_WPTR
#define VPEC_QUEUE7_RB_WPTR__OFFSET_MASK                   0xffffffffUL

// VPEC_QUEUE7_RB_WPTR_HI
#define VPEC_QUEUE7_RB_WPTR_HI__OFFSET_MASK                0xffffffffUL

// VPEC_QUEUE7_RB_RPTR_ADDR_HI
#define VPEC_QUEUE7_RB_RPTR_ADDR_HI__ADDR_MASK             0xffffffffUL

// VPEC_QUEUE7_RB_RPTR_ADDR_LO
#define VPEC_QUEUE7_RB_RPTR_ADDR_LO__ADDR_MASK             0xfffffffcUL

// VPEC_QUEUE7_RB_AQL_CNTL
#define VPEC_QUEUE7_RB_AQL_CNTL__AQL_ENABLE_MASK           0x00000001UL
#define VPEC_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK      0x000000feUL
#define VPEC_QUEUE7_RB_AQL_CNTL__PACKET_STEP_MASK          0x0000ff00UL
#define VPEC_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000UL
#define VPEC_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000UL
#define VPEC_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE_MASK       0x00040000UL

// VPEC_QUEUE7_MINOR_PTR_UPDATE
#define VPEC_QUEUE7_MINOR_PTR_UPDATE__ENABLE_MASK          0x00000001UL

// VPEC_QUEUE7_CD_INFO
#define VPEC_QUEUE7_CD_INFO__CD_INFO_MASK                  0xffffffffUL

// VPEC_QUEUE7_RB_PREEMPT
#define VPEC_QUEUE7_RB_PREEMPT__PREEMPT_REQ_MASK           0x00000001UL

// VPEC_QUEUE7_SKIP_CNTL
#define VPEC_QUEUE7_SKIP_CNTL__SKIP_COUNT_MASK             0x000fffffUL

// VPEC_QUEUE7_DOORBELL
#define VPEC_QUEUE7_DOORBELL__ENABLE_MASK                  0x10000000UL
#define VPEC_QUEUE7_DOORBELL__CAPTURED_MASK                0x40000000UL

// VPEC_QUEUE7_DOORBELL_OFFSET
#define VPEC_QUEUE7_DOORBELL_OFFSET__OFFSET_MASK           0x0ffffffcUL

// VPEC_QUEUE7_DUMMY0
#define VPEC_QUEUE7_DUMMY0__DUMMY_MASK                     0xffffffffUL

// VPEC_QUEUE7_DUMMY1
#define VPEC_QUEUE7_DUMMY1__VALUE_MASK                     0xffffffffUL

// VPEC_QUEUE7_DUMMY2
#define VPEC_QUEUE7_DUMMY2__VALUE_MASK                     0xffffffffUL

// VPEC_QUEUE7_DUMMY3
#define VPEC_QUEUE7_DUMMY3__VALUE_MASK                     0xffffffffUL

// VPEC_QUEUE7_DUMMY4
#define VPEC_QUEUE7_DUMMY4__VALUE_MASK                     0xffffffffUL

// VPEC_QUEUE7_IB_CNTL
#define VPEC_QUEUE7_IB_CNTL__IB_ENABLE_MASK                0x00000001UL
#define VPEC_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB_MASK         0x00000100UL
#define VPEC_QUEUE7_IB_CNTL__CMD_VMID_MASK                 0x000f0000UL
#define VPEC_QUEUE7_IB_CNTL__IB_PRIV_MASK                  0x80000000UL

// VPEC_QUEUE7_IB_RPTR
#define VPEC_QUEUE7_IB_RPTR__OFFSET_MASK                   0x003ffffcUL

// VPEC_QUEUE7_IB_OFFSET
#define VPEC_QUEUE7_IB_OFFSET__OFFSET_MASK                 0x003ffffcUL

// VPEC_QUEUE7_IB_BASE_LO
#define VPEC_QUEUE7_IB_BASE_LO__ADDR_MASK                  0xffffffe0UL

// VPEC_QUEUE7_IB_BASE_HI
#define VPEC_QUEUE7_IB_BASE_HI__ADDR_MASK                  0xffffffffUL

// VPEC_QUEUE7_IB_SIZE
#define VPEC_QUEUE7_IB_SIZE__SIZE_MASK                     0x000fffffUL

// VPEC_QUEUE7_CMDIB_CNTL
#define VPEC_QUEUE7_CMDIB_CNTL__IB_ENABLE_MASK             0x00000001UL
#define VPEC_QUEUE7_CMDIB_CNTL__IB_SWAP_ENABLE_MASK        0x00000010UL
#define VPEC_QUEUE7_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK      0x00000100UL
#define VPEC_QUEUE7_CMDIB_CNTL__CMD_VMID_MASK              0x000f0000UL
#define VPEC_QUEUE7_CMDIB_CNTL__IB_PRIV_MASK               0x80000000UL

// VPEC_QUEUE7_CMDIB_RPTR
#define VPEC_QUEUE7_CMDIB_RPTR__OFFSET_MASK                0x003ffffcUL

// VPEC_QUEUE7_CMDIB_OFFSET
#define VPEC_QUEUE7_CMDIB_OFFSET__OFFSET_MASK              0x003ffffcUL

// VPEC_QUEUE7_CMDIB_BASE_LO
#define VPEC_QUEUE7_CMDIB_BASE_LO__ADDR_MASK               0xffffffe0UL

// VPEC_QUEUE7_CMDIB_BASE_HI
#define VPEC_QUEUE7_CMDIB_BASE_HI__ADDR_MASK               0xffffffffUL

// VPEC_QUEUE7_CMDIB_SIZE
#define VPEC_QUEUE7_CMDIB_SIZE__SIZE_MASK                  0x000fffffUL

// VPEC_QUEUE7_3DLUTIB_CNTL
#define VPEC_QUEUE7_3DLUTIB_CNTL__IB_ENABLE_MASK           0x00000001UL
#define VPEC_QUEUE7_3DLUTIB_CNTL__SWITCH_INSIDE_IB_MASK    0x00000100UL
#define VPEC_QUEUE7_3DLUTIB_CNTL__CMD_VMID_MASK            0x000f0000UL
#define VPEC_QUEUE7_3DLUTIB_CNTL__IB_PRIV_MASK             0x80000000UL

// VPEC_QUEUE7_3DLUTIB_RPTR
#define VPEC_QUEUE7_3DLUTIB_RPTR__OFFSET_MASK              0x003ffffcUL

// VPEC_QUEUE7_3DLUTIB_OFFSET
#define VPEC_QUEUE7_3DLUTIB_OFFSET__OFFSET_MASK            0x003ffffcUL

// VPEC_QUEUE7_3DLUTIB_BASE_LO
#define VPEC_QUEUE7_3DLUTIB_BASE_LO__ADDR_MASK             0xffffffe0UL

// VPEC_QUEUE7_3DLUTIB_BASE_HI
#define VPEC_QUEUE7_3DLUTIB_BASE_HI__ADDR_MASK             0xffffffffUL

// VPEC_QUEUE7_3DLUTIB_SIZE
#define VPEC_QUEUE7_3DLUTIB_SIZE__SIZE_MASK                0x000fffffUL

// VPEC_QUEUE7_CSA_ADDR_LO
#define VPEC_QUEUE7_CSA_ADDR_LO__ADDR_MASK                 0xffffffffUL

// VPEC_QUEUE7_CSA_ADDR_HI
#define VPEC_QUEUE7_CSA_ADDR_HI__ADDR_MASK                 0xffffffffUL

// VPEC_QUEUE7_CONTEXT_STATUS
#define VPEC_QUEUE7_CONTEXT_STATUS__SELECTED_MASK          0x00000001UL
#define VPEC_QUEUE7_CONTEXT_STATUS__USE_IB_MASK            0x00000002UL
#define VPEC_QUEUE7_CONTEXT_STATUS__IDLE_MASK              0x00000004UL
#define VPEC_QUEUE7_CONTEXT_STATUS__EXPIRED_MASK           0x00000008UL
#define VPEC_QUEUE7_CONTEXT_STATUS__EXCEPTION_MASK         0x00000070UL
#define VPEC_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE_MASK        0x00000080UL
#define VPEC_QUEUE7_CONTEXT_STATUS__USE_3DLUTIB_MASK       0x00000100UL
#define VPEC_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK   0x00000400UL
#define VPEC_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE_MASK      0x00000800UL
#define VPEC_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000UL
#define VPEC_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00ff0000UL

// VPEC_QUEUE7_DOORBELL_LOG
#define VPEC_QUEUE7_DOORBELL_LOG__BE_ERROR_MASK            0x00000001UL
#define VPEC_QUEUE7_DOORBELL_LOG__DATA_MASK                0xfffffffcUL

// VPEC_QUEUE7_IB_SUB_REMAIN
#define VPEC_QUEUE7_IB_SUB_REMAIN__SIZE_MASK               0x00003fffUL

// VPEC_QUEUE7_PREEMPT
#define VPEC_QUEUE7_PREEMPT__IB_PREEMPT_MASK               0x00000001UL

// VPEC_QUEUE7_LOG0BUFFER_CFG
#define VPEC_QUEUE7_LOG0BUFFER_CFG__ENABLE_MASK            0x00000001UL
#define VPEC_QUEUE7_LOG0BUFFER_CFG__FIRST_FREE_ENTRY_MASK  0x00000ff0UL
#define VPEC_QUEUE7_LOG0BUFFER_CFG__LAST_FREE_ENTRY_MASK   0x000ff000UL
#define VPEC_QUEUE7_LOG0BUFFER_CFG__RESERVED_MASK          0xfff00000UL

// VPEC_QUEUE7_LOG1BUFFER_CFG
#define VPEC_QUEUE7_LOG1BUFFER_CFG__ENABLE_MASK            0x00000001UL
#define VPEC_QUEUE7_LOG1BUFFER_CFG__PARTIAL_ENTRY_MASK     0x00000002UL
#define VPEC_QUEUE7_LOG1BUFFER_CFG__FIRST_FREE_ENTRY_MASK  0x00000ff0UL
#define VPEC_QUEUE7_LOG1BUFFER_CFG__LAST_FREE_ENTRY_MASK   0x000ff000UL
#define VPEC_QUEUE7_LOG1BUFFER_CFG__RESERVED_MASK          0xfff00000UL

// VPEP_MGCG_CNTL
#define VPEP_MGCG_CNTL__VPDPP0_CLK_GATE_DIS_MASK           0x00000007UL
#define VPEP_MGCG_CNTL__VPDPP1_CLK_GATE_DIS_MASK           0x00000038UL
#define VPEP_MGCG_CNTL__VPMPC_CLK_GATE_DIS_MASK            0x00003000UL
#define VPEP_MGCG_CNTL__VPOPP_CLK_GATE_DIS_MASK            0x000c0000UL
#define VPEP_MGCG_CNTL__VPCDC_SOCCLK_G_GATE_DIS_MASK       0x00100000UL
#define VPEP_MGCG_CNTL__VPCDC_SOCCLK_R_GATE_DIS_MASK       0x00200000UL
#define VPEP_MGCG_CNTL__VPCDC_VPECLK_G_GATE_DIS_MASK       0x00400000UL
#define VPEP_MGCG_CNTL__VPCDC_VPECLK_R_GATE_DIS_MASK       0x00800000UL
#define VPEP_MGCG_CNTL__VPCDC_FE1_CLK_G_GATE_DIS_MASK      0x01000000UL
#define VPEP_MGCG_CNTL__VPCDC_BE1_CLK_G_GATE_DIS_MASK      0x02000000UL
#define VPEP_MGCG_CNTL__VPCDC_FGCG_REP_DIS_MASK            0x40000000UL

// VPCDC_SOFT_RESET
#define VPCDC_SOFT_RESET__VPCDC_SOCCLK_SOFT_RESET_MASK     0x00000001UL
#define VPCDC_SOFT_RESET__VPCDC_VPECLK_SOFT_RESET_MASK     0x00000002UL

// VPCDC_FE0_SURFACE_CONFIG
#define VPCDC_FE0_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_FE0_MASK 0x000001ffUL
#define VPCDC_FE0_SURFACE_CONFIG__ROTATION_ANGLE_FE0_MASK  0x00000600UL
#define VPCDC_FE0_SURFACE_CONFIG__H_MIRROR_EN_FE0_MASK     0x00001000UL
#define VPCDC_FE0_SURFACE_CONFIG__PIX_SURFACE_LINEAR_FE0_MASK 0x00002000UL

// VPCDC_FE0_CROSSBAR_CONFIG
#define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_ALPHA_FE0_MASK 0x00000003UL
#define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_Y_G_FE0_MASK 0x0000000cUL
#define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_CB_B_FE0_MASK 0x00000030UL
#define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_CR_R_FE0_MASK 0x000000c0UL

// VPCDC_FE0_VIEWPORT_START_CONFIG
#define VPCDC_FE0_VIEWPORT_START_CONFIG__VIEWPORT_X_START_FE0_MASK 0x00003fffUL
#define VPCDC_FE0_VIEWPORT_START_CONFIG__VIEWPORT_Y_START_FE0_MASK 0x3fff0000UL

// VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG
#define VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG__VIEWPORT_WIDTH_FE0_MASK 0x00003fffUL
#define VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG__VIEWPORT_HEIGHT_FE0_MASK 0x3fff0000UL

// VPCDC_FE0_VIEWPORT_START_C_CONFIG
#define VPCDC_FE0_VIEWPORT_START_C_CONFIG__VIEWPORT_X_START_C_FE0_MASK 0x00003fffUL
#define VPCDC_FE0_VIEWPORT_START_C_CONFIG__VIEWPORT_Y_START_C_FE0_MASK 0x3fff0000UL

// VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG
#define VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG__VIEWPORT_WIDTH_C_FE0_MASK 0x00003fffUL
#define VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG__VIEWPORT_HEIGHT_C_FE0_MASK 0x3fff0000UL

// VPCDC_FE1_SURFACE_CONFIG
#define VPCDC_FE1_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_FE1_MASK 0x000001ffUL
#define VPCDC_FE1_SURFACE_CONFIG__ROTATION_ANGLE_FE1_MASK  0x00000600UL
#define VPCDC_FE1_SURFACE_CONFIG__H_MIRROR_EN_FE1_MASK     0x00001000UL
#define VPCDC_FE1_SURFACE_CONFIG__PIX_SURFACE_LINEAR_FE1_MASK 0x00002000UL

// VPCDC_FE1_CROSSBAR_CONFIG
#define VPCDC_FE1_CROSSBAR_CONFIG__CROSSBAR_SRC_ALPHA_FE1_MASK 0x00000003UL
#define VPCDC_FE1_CROSSBAR_CONFIG__CROSSBAR_SRC_Y_G_FE1_MASK 0x0000000cUL
#define VPCDC_FE1_CROSSBAR_CONFIG__CROSSBAR_SRC_CB_B_FE1_MASK 0x00000030UL
#define VPCDC_FE1_CROSSBAR_CONFIG__CROSSBAR_SRC_CR_R_FE1_MASK 0x000000c0UL

// VPCDC_FE1_VIEWPORT_START_CONFIG
#define VPCDC_FE1_VIEWPORT_START_CONFIG__VIEWPORT_X_START_FE1_MASK 0x00003fffUL
#define VPCDC_FE1_VIEWPORT_START_CONFIG__VIEWPORT_Y_START_FE1_MASK 0x3fff0000UL

// VPCDC_FE1_VIEWPORT_DIMENSION_CONFIG
#define VPCDC_FE1_VIEWPORT_DIMENSION_CONFIG__VIEWPORT_WIDTH_FE1_MASK 0x00003fffUL
#define VPCDC_FE1_VIEWPORT_DIMENSION_CONFIG__VIEWPORT_HEIGHT_FE1_MASK 0x3fff0000UL

// VPCDC_FE1_VIEWPORT_START_C_CONFIG
#define VPCDC_FE1_VIEWPORT_START_C_CONFIG__VIEWPORT_X_START_C_FE1_MASK 0x00003fffUL
#define VPCDC_FE1_VIEWPORT_START_C_CONFIG__VIEWPORT_Y_START_C_FE1_MASK 0x3fff0000UL

// VPCDC_FE1_VIEWPORT_DIMENSION_C_CONFIG
#define VPCDC_FE1_VIEWPORT_DIMENSION_C_CONFIG__VIEWPORT_WIDTH_C_FE1_MASK 0x00003fffUL
#define VPCDC_FE1_VIEWPORT_DIMENSION_C_CONFIG__VIEWPORT_HEIGHT_C_FE1_MASK 0x3fff0000UL

// VPCDC_BE0_P2B_CONFIG
#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL0_MASK 0x00000003UL
#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL1_MASK 0x0000000cUL
#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL2_MASK 0x00000030UL
#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL3_MASK 0x000000c0UL
#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_FORMAT_SEL_MASK 0x0001ff00UL
#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_TILED_MASK     0x00020000UL
#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_X_START_PLANE0_MASK 0x007c0000UL
#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_X_START_PLANE1_MASK 0x0f800000UL

// VPCDC_BE0_GLOBAL_SYNC_CONFIG
#define VPCDC_BE0_GLOBAL_SYNC_CONFIG__BE0_VUPDATE_OFFSET_MASK 0x000003ffUL
#define VPCDC_BE0_GLOBAL_SYNC_CONFIG__BE0_VUPDATE_WIDTH_MASK 0x000ffc00UL
#define VPCDC_BE0_GLOBAL_SYNC_CONFIG__BE0_VREADY_OFFSET_MASK 0x3ff00000UL

// VPCDC_BE1_P2B_CONFIG
#define VPCDC_BE1_P2B_CONFIG__VPCDC_BE1_P2B_XBAR_SEL0_MASK 0x00000003UL
#define VPCDC_BE1_P2B_CONFIG__VPCDC_BE1_P2B_XBAR_SEL1_MASK 0x0000000cUL
#define VPCDC_BE1_P2B_CONFIG__VPCDC_BE1_P2B_XBAR_SEL2_MASK 0x00000030UL
#define VPCDC_BE1_P2B_CONFIG__VPCDC_BE1_P2B_XBAR_SEL3_MASK 0x000000c0UL
#define VPCDC_BE1_P2B_CONFIG__VPCDC_BE1_P2B_FORMAT_SEL_MASK 0x0001ff00UL
#define VPCDC_BE1_P2B_CONFIG__VPCDC_BE1_P2B_TILED_MASK     0x00020000UL
#define VPCDC_BE1_P2B_CONFIG__VPCDC_BE1_P2B_X_START_PLANE0_MASK 0x007c0000UL
#define VPCDC_BE1_P2B_CONFIG__VPCDC_BE1_P2B_X_START_PLANE1_MASK 0x0f800000UL

// VPCDC_BE1_GLOBAL_SYNC_CONFIG
#define VPCDC_BE1_GLOBAL_SYNC_CONFIG__BE1_VUPDATE_OFFSET_MASK 0x000003ffUL
#define VPCDC_BE1_GLOBAL_SYNC_CONFIG__BE1_VUPDATE_WIDTH_MASK 0x000ffc00UL
#define VPCDC_BE1_GLOBAL_SYNC_CONFIG__BE1_VREADY_OFFSET_MASK 0x3ff00000UL

// VPCDC_BE2_P2B_CONFIG
#define VPCDC_BE2_P2B_CONFIG__VPCDC_BE2_P2B_XBAR_SEL0_MASK 0x00000003UL
#define VPCDC_BE2_P2B_CONFIG__VPCDC_BE2_P2B_XBAR_SEL1_MASK 0x0000000cUL
#define VPCDC_BE2_P2B_CONFIG__VPCDC_BE2_P2B_XBAR_SEL2_MASK 0x00000030UL
#define VPCDC_BE2_P2B_CONFIG__VPCDC_BE2_P2B_XBAR_SEL3_MASK 0x000000c0UL
#define VPCDC_BE2_P2B_CONFIG__VPCDC_BE2_P2B_FORMAT_SEL_MASK 0x0001ff00UL
#define VPCDC_BE2_P2B_CONFIG__VPCDC_BE2_P2B_TILED_MASK     0x00020000UL
#define VPCDC_BE2_P2B_CONFIG__VPCDC_BE2_P2B_X_START_PLANE0_MASK 0x007c0000UL
#define VPCDC_BE2_P2B_CONFIG__VPCDC_BE2_P2B_X_START_PLANE1_MASK 0x0f800000UL

// VPCDC_BE2_GLOBAL_SYNC_CONFIG
#define VPCDC_BE2_GLOBAL_SYNC_CONFIG__BE2_VUPDATE_OFFSET_MASK 0x000003ffUL
#define VPCDC_BE2_GLOBAL_SYNC_CONFIG__BE2_VUPDATE_WIDTH_MASK 0x000ffc00UL
#define VPCDC_BE2_GLOBAL_SYNC_CONFIG__BE2_VREADY_OFFSET_MASK 0x3ff00000UL

// VPCDC_BE3_P2B_CONFIG
#define VPCDC_BE3_P2B_CONFIG__VPCDC_BE3_P2B_XBAR_SEL0_MASK 0x00000003UL
#define VPCDC_BE3_P2B_CONFIG__VPCDC_BE3_P2B_XBAR_SEL1_MASK 0x0000000cUL
#define VPCDC_BE3_P2B_CONFIG__VPCDC_BE3_P2B_XBAR_SEL2_MASK 0x00000030UL
#define VPCDC_BE3_P2B_CONFIG__VPCDC_BE3_P2B_XBAR_SEL3_MASK 0x000000c0UL
#define VPCDC_BE3_P2B_CONFIG__VPCDC_BE3_P2B_FORMAT_SEL_MASK 0x0001ff00UL
#define VPCDC_BE3_P2B_CONFIG__VPCDC_BE3_P2B_TILED_MASK     0x00020000UL
#define VPCDC_BE3_P2B_CONFIG__VPCDC_BE3_P2B_X_START_PLANE0_MASK 0x007c0000UL
#define VPCDC_BE3_P2B_CONFIG__VPCDC_BE3_P2B_X_START_PLANE1_MASK 0x0f800000UL

// VPCDC_BE3_GLOBAL_SYNC_CONFIG
#define VPCDC_BE3_GLOBAL_SYNC_CONFIG__BE3_VUPDATE_OFFSET_MASK 0x000003ffUL
#define VPCDC_BE3_GLOBAL_SYNC_CONFIG__BE3_VUPDATE_WIDTH_MASK 0x000ffc00UL
#define VPCDC_BE3_GLOBAL_SYNC_CONFIG__BE3_VREADY_OFFSET_MASK 0x3ff00000UL

// VPCDC_GLOBAL_SYNC_TRIGGER
#define VPCDC_GLOBAL_SYNC_TRIGGER__VPBE_GS_TRIG_MASK       0x00000003UL

// VPCDC_VREADY_STATUS
#define VPCDC_VREADY_STATUS__VPFE_VR_STATUS_MASK           0x00000003UL

// VPEP_MEM_GLOBAL_PWR_REQ_CNTL
#define VPEP_MEM_GLOBAL_PWR_REQ_CNTL__MEM_GLOBAL_PWR_REQ_DIS_MASK 0x00000001UL

// VPFE0_MEM_PWR_CNTL
#define VPFE0_MEM_PWR_CNTL__VPFE0_MEM_PWR_FORCE_MASK       0x00000003UL
#define VPFE0_MEM_PWR_CNTL__VPFE0_MEM_PWR_MODE_MASK        0x0000000cUL
#define VPFE0_MEM_PWR_CNTL__VPFE0_MEM_PWR_STATE_MASK       0x00000030UL
#define VPFE0_MEM_PWR_CNTL__VPFE0_MEM_PWR_DIS_MASK         0x00000040UL

// VPFE1_MEM_PWR_CNTL
#define VPFE1_MEM_PWR_CNTL__VPFE1_MEM_PWR_FORCE_MASK       0x00000003UL
#define VPFE1_MEM_PWR_CNTL__VPFE1_MEM_PWR_MODE_MASK        0x0000000cUL
#define VPFE1_MEM_PWR_CNTL__VPFE1_MEM_PWR_STATE_MASK       0x00000030UL
#define VPFE1_MEM_PWR_CNTL__VPFE1_MEM_PWR_DIS_MASK         0x00000040UL

// VPBE0_MEM_PWR_CNTL
#define VPBE0_MEM_PWR_CNTL__VPBE0_MEM_PWR_FORCE_MASK       0x00000003UL
#define VPBE0_MEM_PWR_CNTL__VPBE0_MEM_PWR_MODE_MASK        0x0000000cUL
#define VPBE0_MEM_PWR_CNTL__VPBE0_MEM_PWR_STATE_MASK       0x00000030UL
#define VPBE0_MEM_PWR_CNTL__VPBE0_MEM_PWR_DIS_MASK         0x00000040UL

// VPBE1_MEM_PWR_CNTL
#define VPBE1_MEM_PWR_CNTL__VPBE1_MEM_PWR_FORCE_MASK       0x00000003UL
#define VPBE1_MEM_PWR_CNTL__VPBE1_MEM_PWR_MODE_MASK        0x0000000cUL
#define VPBE1_MEM_PWR_CNTL__VPBE1_MEM_PWR_STATE_MASK       0x00000030UL
#define VPBE1_MEM_PWR_CNTL__VPBE1_MEM_PWR_DIS_MASK         0x00000040UL

// VPBE2_MEM_PWR_CNTL
#define VPBE2_MEM_PWR_CNTL__VPBE2_MEM_PWR_FORCE_MASK       0x00000003UL
#define VPBE2_MEM_PWR_CNTL__VPBE2_MEM_PWR_MODE_MASK        0x0000000cUL
#define VPBE2_MEM_PWR_CNTL__VPBE2_MEM_PWR_STATE_MASK       0x00000030UL
#define VPBE2_MEM_PWR_CNTL__VPBE2_MEM_PWR_DIS_MASK         0x00000040UL

// VPBE3_MEM_PWR_CNTL
#define VPBE3_MEM_PWR_CNTL__VPBE3_MEM_PWR_FORCE_MASK       0x00000003UL
#define VPBE3_MEM_PWR_CNTL__VPBE3_MEM_PWR_MODE_MASK        0x0000000cUL
#define VPBE3_MEM_PWR_CNTL__VPBE3_MEM_PWR_STATE_MASK       0x00000030UL
#define VPBE3_MEM_PWR_CNTL__VPBE3_MEM_PWR_DIS_MASK         0x00000040UL

// VPEP_RBBMIF_TIMEOUT
#define VPEP_RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK     0x000fffffUL
#define VPEP_RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_HOLD_MASK      0xfff00000UL

// VPEP_RBBMIF_STATUS
#define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK 0x0000001fUL
#define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_OP_MASK         0x10000000UL
#define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK 0x20000000UL
#define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK_MASK        0x40000000UL
#define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK_MASK       0x80000000UL

// VPEP_RBBMIF_TIMEOUT_DIS
#define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK  0x00000001UL
#define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK  0x00000002UL
#define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK  0x00000004UL
#define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK  0x00000008UL
#define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK  0x00000010UL

// VPCDC_DEBUG_CTRL0
#define VPCDC_DEBUG_CTRL0__VPCDC_DBG_EN_MASK               0x00000001UL
#define VPCDC_DEBUG_CTRL0__VPCDC_DBGMUX_OUT_0_SEL_SOCCLK_MASK 0x00700000UL

// VPCDC_DEBUG_CTRL1
#define VPCDC_DEBUG_CTRL1__VPCDC_DBGMUX_OUT_0_SEL_VPECLK_MASK 0x0000003fUL
#define VPCDC_DEBUG_CTRL1__VPCDC_DBGMUX_OUT_1_SEL_VPECLK_MASK 0x00003f00UL
#define VPCDC_DEBUG_CTRL1__VPCDC_DBGMUX_OUT_2_SEL_VPECLK_MASK 0x003f0000UL
#define VPCDC_DEBUG_CTRL1__VPCDC_DBGMUX_OUT_3_SEL_VPECLK_MASK 0x3f000000UL

// VPCDC_TEST_DEBUG_INDEX
#define VPCDC_TEST_DEBUG_INDEX__VPCDC_TEST_DEBUG_INDEX_MASK 0x000000ffUL

// VPCDC_TEST_DEBUG_DATA
#define VPCDC_TEST_DEBUG_DATA__VPCDC_TEST_DEBUG_DATA_MASK  0xffffffffUL

// VPCDC_3DLUT_FL_CONFIG
#define VPCDC_3DLUT_FL_CONFIG__VPCDC_3DLUT_FL_MODE_MASK    0x00000003UL
#define VPCDC_3DLUT_FL_CONFIG__VPCDC_3DLUT_FL_CROSSBAR_SRC_G_MASK 0x0000000cUL
#define VPCDC_3DLUT_FL_CONFIG__VPCDC_3DLUT_FL_CROSSBAR_SRC_B_MASK 0x00000030UL
#define VPCDC_3DLUT_FL_CONFIG__VPCDC_3DLUT_FL_CROSSBAR_SRC_R_MASK 0x000000c0UL
#define VPCDC_3DLUT_FL_CONFIG__VPCDC_3DLUT_FL_SIZE_MASK    0x00000100UL

// VPCDC_CONTROL
#define VPCDC_CONTROL__VPCDC_HISTOGRAM0_EN_MASK            0x00000003UL
#define VPCDC_CONTROL__VPCDC_HISTOGRAM1_EN_MASK            0x0000000cUL
#define VPCDC_CONTROL__VPCDC_FROD_EN_MASK                  0x00000100UL

// PERFCOUNTER_CNTL
#define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK       0x000001ffUL
#define PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK      0x00000e00UL
#define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK        0x00007000UL
#define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK     0x00008000UL
#define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK      0x00010000UL
#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000UL
#define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK      0x00800000UL
#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK          0x01000000UL
#define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK        0x02000000UL
#define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK          0x04000000UL
#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK        0xe0000000UL

// PERFCOUNTER_CNTL2
#define PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003UL
#define PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK   0x00000004UL
#define PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK   0x00000008UL
#define PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK     0x00003f00UL
#define PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK      0xe0000000UL

// PERFCOUNTER_STATE
#define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK     0x00000003UL
#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK     0x00000004UL
#define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK     0x00000030UL
#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK     0x00000040UL
#define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK     0x00000300UL
#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK     0x00000400UL
#define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK     0x00003000UL
#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK     0x00004000UL
#define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK     0x00030000UL
#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK     0x00040000UL
#define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK     0x00300000UL
#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK     0x00400000UL
#define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK     0x03000000UL
#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK     0x04000000UL
#define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK     0x30000000UL
#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK     0x40000000UL

// VPCNVC_SURFACE_PIXEL_FORMAT
#define VPCNVC_SURFACE_PIXEL_FORMAT__VPCNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007fUL

// VPCNVC_FORMAT_CONTROL
#define VPCNVC_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK  0x00000001UL
#define VPCNVC_FORMAT_CONTROL__FORMAT_CNV16_MASK           0x00000010UL
#define VPCNVC_FORMAT_CONTROL__ALPHA_EN_MASK               0x00000100UL
#define VPCNVC_FORMAT_CONTROL__VPCNVC_BYPASS_MASK          0x00001000UL
#define VPCNVC_FORMAT_CONTROL__VPCNVC_BYPASS_MSB_ALIGN_MASK 0x00002000UL
#define VPCNVC_FORMAT_CONTROL__CLAMP_POSITIVE_MASK         0x00010000UL
#define VPCNVC_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK       0x00020000UL
#define VPCNVC_FORMAT_CONTROL__VPCNVC_UPDATE_PENDING_MASK  0x00100000UL

// VPCNVC_FCNV_FP_BIAS_R
#define VPCNVC_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK         0x0007ffffUL

// VPCNVC_FCNV_FP_BIAS_G
#define VPCNVC_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK         0x0007ffffUL

// VPCNVC_FCNV_FP_BIAS_B
#define VPCNVC_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK         0x0007ffffUL

// VPCNVC_FCNV_FP_SCALE_R
#define VPCNVC_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK       0x0007ffffUL

// VPCNVC_FCNV_FP_SCALE_G
#define VPCNVC_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK       0x0007ffffUL

// VPCNVC_FCNV_FP_SCALE_B
#define VPCNVC_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK       0x0007ffffUL

// VPCNVC_COLOR_KEYER_CONTROL
#define VPCNVC_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK    0x00000001UL
#define VPCNVC_COLOR_KEYER_CONTROL__LUMA_KEYER_EN_MASK     0x00000002UL
#define VPCNVC_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK  0x00000030UL

// VPCNVC_COLOR_KEYER_ALPHA
#define VPCNVC_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000ffffUL
#define VPCNVC_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xffff0000UL

// VPCNVC_COLOR_KEYER_RED
#define VPCNVC_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK   0x0000ffffUL
#define VPCNVC_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK  0xffff0000UL

// VPCNVC_COLOR_KEYER_GREEN
#define VPCNVC_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000ffffUL
#define VPCNVC_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xffff0000UL

// VPCNVC_COLOR_KEYER_BLUE
#define VPCNVC_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000ffffUL
#define VPCNVC_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xffff0000UL

// VPCNVC_ALPHA_2BIT_LUT01
#define VPCNVC_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT0_MASK      0x00000fffUL
#define VPCNVC_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT1_MASK      0x0fff0000UL

// VPCNVC_ALPHA_2BIT_LUT23
#define VPCNVC_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT2_MASK      0x00000fffUL
#define VPCNVC_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT3_MASK      0x0fff0000UL

// VPCNVC_PRE_DEALPHA
#define VPCNVC_PRE_DEALPHA__PRE_DEALPHA_EN_MASK            0x00000001UL
#define VPCNVC_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK      0x00000010UL

// VPCNVC_PRE_CSC_MODE
#define VPCNVC_PRE_CSC_MODE__PRE_CSC_MODE_MASK             0x00000001UL
#define VPCNVC_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK     0x00000004UL

// VPCNVC_PRE_CSC_C11_C12
#define VPCNVC_PRE_CSC_C11_C12__PRE_CSC_C11_MASK           0x0000ffffUL
#define VPCNVC_PRE_CSC_C11_C12__PRE_CSC_C12_MASK           0xffff0000UL

// VPCNVC_PRE_CSC_C13_C14
#define VPCNVC_PRE_CSC_C13_C14__PRE_CSC_C13_MASK           0x0000ffffUL
#define VPCNVC_PRE_CSC_C13_C14__PRE_CSC_C14_MASK           0xffff0000UL

// VPCNVC_PRE_CSC_C21_C22
#define VPCNVC_PRE_CSC_C21_C22__PRE_CSC_C21_MASK           0x0000ffffUL
#define VPCNVC_PRE_CSC_C21_C22__PRE_CSC_C22_MASK           0xffff0000UL

// VPCNVC_PRE_CSC_C23_C24
#define VPCNVC_PRE_CSC_C23_C24__PRE_CSC_C23_MASK           0x0000ffffUL
#define VPCNVC_PRE_CSC_C23_C24__PRE_CSC_C24_MASK           0xffff0000UL

// VPCNVC_PRE_CSC_C31_C32
#define VPCNVC_PRE_CSC_C31_C32__PRE_CSC_C31_MASK           0x0000ffffUL
#define VPCNVC_PRE_CSC_C31_C32__PRE_CSC_C32_MASK           0xffff0000UL

// VPCNVC_PRE_CSC_C33_C34
#define VPCNVC_PRE_CSC_C33_C34__PRE_CSC_C33_MASK           0x0000ffffUL
#define VPCNVC_PRE_CSC_C33_C34__PRE_CSC_C34_MASK           0xffff0000UL

// VPCNVC_COEF_FORMAT
#define VPCNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK       0x00000001UL

// VPCNVC_PRE_DEGAM
#define VPCNVC_PRE_DEGAM__PRE_DEGAM_MODE_MASK              0x00000003UL
#define VPCNVC_PRE_DEGAM__PRE_DEGAM_SELECT_MASK            0x00000070UL

// VPCNVC_PRE_REALPHA
#define VPCNVC_PRE_REALPHA__PRE_REALPHA_EN_MASK            0x00000001UL
#define VPCNVC_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK      0x00000010UL

// VPCNVC_CFG_TEST_DEBUG_INDEX
#define VPCNVC_CFG_TEST_DEBUG_INDEX__VPCNVC_CFG_TEST_DEBUG_INDEX_MASK 0x000000ffUL
#define VPCNVC_CFG_TEST_DEBUG_INDEX__VPCNVC_CFG_TEST_DEBUG_WRITE_EN_MASK 0x00000100UL

// VPCNVC_CFG_TEST_DEBUG_DATA
#define VPCNVC_CFG_TEST_DEBUG_DATA__VPCNVC_CFG_TEST_DEBUG_DATA_MASK 0xffffffffUL

// VPDSCL_COEF_RAM_TAP_SELECT
#define VPDSCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003UL
#define VPDSCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003f00UL
#define VPDSCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000UL

// VPDSCL_COEF_RAM_TAP_DATA
#define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003fffUL
#define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000UL
#define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3fff0000UL
#define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000UL

// VPDSCL_MODE
#define VPDSCL_MODE__VPDSCL_MODE_MASK                      0x00000007UL
#define VPDSCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK      0x00001000UL
#define VPDSCL_MODE__SCL_CHROMA_COEF_MODE_MASK             0x00010000UL
#define VPDSCL_MODE__SCL_ALPHA_COEF_MODE_MASK              0x00100000UL
#define VPDSCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK           0x01000000UL

// VPDSCL_TAP_CONTROL
#define VPDSCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK            0x00000007UL
#define VPDSCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK            0x00000070UL
#define VPDSCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK          0x00000700UL
#define VPDSCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK          0x00007000UL

// VPDSCL_CONTROL
#define VPDSCL_CONTROL__SCL_BOUNDARY_MODE_MASK             0x00000001UL

// VPDSCL_2TAP_CONTROL
#define VPDSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001UL
#define VPDSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK      0x00000010UL
#define VPDSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK  0x00000700UL
#define VPDSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000UL
#define VPDSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK      0x00100000UL
#define VPDSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK  0x07000000UL

// VPDSCL_MANUAL_REPLICATE_CONTROL
#define VPDSCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000fUL
#define VPDSCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000f00UL

// VPDSCL_HORZ_FILTER_SCALE_RATIO
#define VPDSCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x07ffffffUL

// VPDSCL_HORZ_FILTER_INIT
#define VPDSCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK      0x00ffffffUL
#define VPDSCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK       0x0f000000UL

// VPDSCL_HORZ_FILTER_SCALE_RATIO_C
#define VPDSCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x07ffffffUL

// VPDSCL_HORZ_FILTER_INIT_C
#define VPDSCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK  0x00ffffffUL
#define VPDSCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK   0x0f000000UL

// VPDSCL_VERT_FILTER_SCALE_RATIO
#define VPDSCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x07ffffffUL

// VPDSCL_VERT_FILTER_INIT
#define VPDSCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK      0x00ffffffUL
#define VPDSCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK       0x0f000000UL

// VPDSCL_VERT_FILTER_INIT_BOT
#define VPDSCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00ffffffUL
#define VPDSCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0f000000UL

// VPDSCL_VERT_FILTER_SCALE_RATIO_C
#define VPDSCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x07ffffffUL

// VPDSCL_VERT_FILTER_INIT_C
#define VPDSCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK  0x00ffffffUL
#define VPDSCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK   0x0f000000UL

// VPDSCL_VERT_FILTER_INIT_BOT_C
#define VPDSCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00ffffffUL
#define VPDSCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0f000000UL

// VPDSCL_BLACK_COLOR
#define VPDSCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK     0x0000ffffUL
#define VPDSCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK      0xffff0000UL

// VPDSCL_UPDATE
#define VPDSCL_UPDATE__SCL_UPDATE_PENDING_MASK             0x00000001UL

// VPDSCL_AUTOCAL
#define VPDSCL_AUTOCAL__AUTOCAL_MODE_MASK                  0x00000003UL

// VPDSCL_EXT_OVERSCAN_LEFT_RIGHT
#define VPDSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001fffUL
#define VPDSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1fff0000UL

// VPDSCL_EXT_OVERSCAN_TOP_BOTTOM
#define VPDSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001fffUL
#define VPDSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1fff0000UL

// VPOTG_H_BLANK
#define VPOTG_H_BLANK__OTG_H_BLANK_START_MASK              0x00003fffUL
#define VPOTG_H_BLANK__OTG_H_BLANK_END_MASK                0x3fff0000UL

// VPOTG_V_BLANK
#define VPOTG_V_BLANK__OTG_V_BLANK_START_MASK              0x00003fffUL
#define VPOTG_V_BLANK__OTG_V_BLANK_END_MASK                0x3fff0000UL

// VPDSCL_RECOUT_START
#define VPDSCL_RECOUT_START__RECOUT_START_X_MASK           0x00001fffUL
#define VPDSCL_RECOUT_START__RECOUT_START_Y_MASK           0x1fff0000UL

// VPDSCL_RECOUT_SIZE
#define VPDSCL_RECOUT_SIZE__RECOUT_WIDTH_MASK              0x00003fffUL
#define VPDSCL_RECOUT_SIZE__RECOUT_HEIGHT_MASK             0x3fff0000UL

// VPMPC_SIZE
#define VPMPC_SIZE__VPMPC_WIDTH_MASK                       0x00003fffUL
#define VPMPC_SIZE__VPMPC_HEIGHT_MASK                      0x3fff0000UL

// VPLB_DATA_FORMAT
#define VPLB_DATA_FORMAT__ALPHA_EN_MASK                    0x00000010UL

// VPLB_MEMORY_CTRL
#define VPLB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK           0x00003f00UL
#define VPLB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK           0x007f0000UL
#define VPLB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK         0x7f000000UL

// VPLB_V_COUNTER
#define VPLB_V_COUNTER__V_COUNTER_MASK                     0x00001fffUL
#define VPLB_V_COUNTER__V_COUNTER_C_MASK                   0x1fff0000UL

// VPDSCL_MEM_PWR_CTRL
#define VPDSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK        0x00000003UL
#define VPDSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK          0x00000004UL
#define VPDSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK      0x00000030UL
#define VPDSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK        0x00000040UL
#define VPDSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK      0x00000300UL
#define VPDSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK        0x00000400UL
#define VPDSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK          0x10000000UL

// VPDSCL_MEM_PWR_STATUS
#define VPDSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK      0x00000003UL
#define VPDSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK    0x0000000cUL
#define VPDSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK    0x00000030UL

// VPDSCL_EASF_H_MODE
#define VPDSCL_EASF_H_MODE__SCL_EASF_H_EN_MASK             0x00000001UL
#define VPDSCL_EASF_H_MODE__SCL_EASF_H_RINGEST_FORCE_EN_MASK 0x00000010UL
#define VPDSCL_EASF_H_MODE__SCL_EASF_H_2TAP_SHARP_FACTOR_MASK 0x00003f00UL

// VPDSCL_EASF_V_MODE
#define VPDSCL_EASF_V_MODE__SCL_EASF_V_EN_MASK             0x00000001UL
#define VPDSCL_EASF_V_MODE__SCL_EASF_V_RINGEST_FORCE_EN_MASK 0x00000010UL
#define VPDSCL_EASF_V_MODE__SCL_EASF_V_2TAP_SHARP_FACTOR_MASK 0x00003f00UL

// VPDSCL_SC_MODE
#define VPDSCL_SC_MODE__SCL_SC_MATRIX_MODE_MASK            0x00000001UL
#define VPDSCL_SC_MODE__SCL_SC_LTONL_EN_MASK               0x00000100UL

// VPDSCL_SC_MATRIX_C0C1
#define VPDSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C0_MASK       0x0000ffffUL
#define VPDSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C1_MASK       0xffff0000UL

// VPDSCL_SC_MATRIX_C2C3
#define VPDSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C2_MASK       0x0000ffffUL
#define VPDSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C3_MASK       0xffff0000UL

// VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN
#define VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN1_MASK 0x0000ffffUL
#define VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN2_MASK 0xffff0000UL

// VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE
#define VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1_MASK 0x0000ffffUL
#define VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2_MASK 0xffff0000UL

// VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN
#define VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN1_MASK 0x0000ffffUL
#define VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN2_MASK 0xffff0000UL

// VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE
#define VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1_MASK 0x0000ffffUL
#define VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2_MASK 0xffff0000UL

// VPDSCL_EASF_V_RINGEST_3TAP_CNTL1
#define VPDSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT_MASK 0x0000ffffUL
#define VPDSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL_MASK 0xffff0000UL

// VPDSCL_EASF_V_RINGEST_3TAP_CNTL2
#define VPDSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE_MASK 0x0000ffffUL
#define VPDSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE_MASK 0xffff0000UL

// VPDSCL_EASF_V_RINGEST_3TAP_CNTL3
#define VPDSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE_MASK 0x0000ffffUL
#define VPDSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET_MASK 0xffff0000UL

// VPDSCL_EASF_RINGEST_FORCE
#define VPDSCL_EASF_RINGEST_FORCE__SCL_EASF_H_RINGEST_FORCE_MASK 0x0000ffffUL
#define VPDSCL_EASF_RINGEST_FORCE__SCL_EASF_V_RINGEST_FORCE_MASK 0xffff0000UL

// VPDSCL_EASF_H_BF_CNTL
#define VPDSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF1_EN_MASK      0x00000001UL
#define VPDSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_MODE_MASK    0x00000f00UL
#define VPDSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF3_MODE_MASK    0x00030000UL
#define VPDSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT1_GAIN_MASK 0x00f00000UL
#define VPDSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT2_GAIN_MASK 0x0f000000UL
#define VPDSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_ROC_GAIN_MASK 0xf0000000UL

// VPDSCL_EASF_H_BF_FINAL_MAX_MIN
#define VPDSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXA_MASK 0x0000003fUL
#define VPDSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXB_MASK 0x00003f00UL
#define VPDSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINA_MASK 0x003f0000UL
#define VPDSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINB_MASK 0x3f000000UL

// VPDSCL_EASF_V_BF_CNTL
#define VPDSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF1_EN_MASK      0x00000001UL
#define VPDSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_MODE_MASK    0x00000f00UL
#define VPDSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF3_MODE_MASK    0x00030000UL
#define VPDSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT1_GAIN_MASK 0x00f00000UL
#define VPDSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT2_GAIN_MASK 0x0f000000UL
#define VPDSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_ROC_GAIN_MASK 0xf0000000UL

// VPDSCL_EASF_V_BF_FINAL_MAX_MIN
#define VPDSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXA_MASK 0x0000003fUL
#define VPDSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXB_MASK 0x00003f00UL
#define VPDSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINA_MASK 0x003f0000UL
#define VPDSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINB_MASK 0x3f000000UL

// VPDSCL_EASF_H_BF1_PWL_SEG0
#define VPDSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_IN_SEG0_MASK 0x000007ffUL
#define VPDSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_BASE_SEG0_MASK 0x0003f000UL
#define VPDSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_SLOPE_SEG0_MASK 0x7ff00000UL

// VPDSCL_EASF_H_BF1_PWL_SEG1
#define VPDSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_IN_SEG1_MASK 0x000007ffUL
#define VPDSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_BASE_SEG1_MASK 0x0003f000UL
#define VPDSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_SLOPE_SEG1_MASK 0x7ff00000UL

// VPDSCL_EASF_H_BF1_PWL_SEG2
#define VPDSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_IN_SEG2_MASK 0x000007ffUL
#define VPDSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_BASE_SEG2_MASK 0x0003f000UL
#define VPDSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_SLOPE_SEG2_MASK 0x7ff00000UL

// VPDSCL_EASF_H_BF1_PWL_SEG3
#define VPDSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_IN_SEG3_MASK 0x000007ffUL
#define VPDSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_BASE_SEG3_MASK 0x0003f000UL
#define VPDSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_SLOPE_SEG3_MASK 0x7ff00000UL

// VPDSCL_EASF_H_BF1_PWL_SEG4
#define VPDSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_IN_SEG4_MASK 0x000007ffUL
#define VPDSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_BASE_SEG4_MASK 0x0003f000UL
#define VPDSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_SLOPE_SEG4_MASK 0x7ff00000UL

// VPDSCL_EASF_H_BF1_PWL_SEG5
#define VPDSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_IN_SEG5_MASK 0x000007ffUL
#define VPDSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_BASE_SEG5_MASK 0x0003f000UL
#define VPDSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_SLOPE_SEG5_MASK 0x7ff00000UL

// VPDSCL_EASF_H_BF1_PWL_SEG6
#define VPDSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_IN_SEG6_MASK 0x000007ffUL
#define VPDSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_BASE_SEG6_MASK 0x0003f000UL
#define VPDSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_SLOPE_SEG6_MASK 0x7ff00000UL

// VPDSCL_EASF_H_BF1_PWL_SEG7
#define VPDSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_IN_SEG7_MASK 0x000007ffUL
#define VPDSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_BASE_SEG7_MASK 0x0003f000UL

// VPDSCL_EASF_V_BF1_PWL_SEG0
#define VPDSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_IN_SEG0_MASK 0x000007ffUL
#define VPDSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_BASE_SEG0_MASK 0x0003f000UL
#define VPDSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_SLOPE_SEG0_MASK 0x7ff00000UL

// VPDSCL_EASF_V_BF1_PWL_SEG1
#define VPDSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_IN_SEG1_MASK 0x000007ffUL
#define VPDSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_BASE_SEG1_MASK 0x0003f000UL
#define VPDSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_SLOPE_SEG1_MASK 0x7ff00000UL

// VPDSCL_EASF_V_BF1_PWL_SEG2
#define VPDSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_IN_SEG2_MASK 0x000007ffUL
#define VPDSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_BASE_SEG2_MASK 0x0003f000UL
#define VPDSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_SLOPE_SEG2_MASK 0x7ff00000UL

// VPDSCL_EASF_V_BF1_PWL_SEG3
#define VPDSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_IN_SEG3_MASK 0x000007ffUL
#define VPDSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_BASE_SEG3_MASK 0x0003f000UL
#define VPDSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_SLOPE_SEG3_MASK 0x7ff00000UL

// VPDSCL_EASF_V_BF1_PWL_SEG4
#define VPDSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_IN_SEG4_MASK 0x000007ffUL
#define VPDSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_BASE_SEG4_MASK 0x0003f000UL
#define VPDSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_SLOPE_SEG4_MASK 0x7ff00000UL

// VPDSCL_EASF_V_BF1_PWL_SEG5
#define VPDSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_IN_SEG5_MASK 0x000007ffUL
#define VPDSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_BASE_SEG5_MASK 0x0003f000UL
#define VPDSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_SLOPE_SEG5_MASK 0x7ff00000UL

// VPDSCL_EASF_V_BF1_PWL_SEG6
#define VPDSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_IN_SEG6_MASK 0x000007ffUL
#define VPDSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_BASE_SEG6_MASK 0x0003f000UL
#define VPDSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_SLOPE_SEG6_MASK 0x7ff00000UL

// VPDSCL_EASF_V_BF1_PWL_SEG7
#define VPDSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_IN_SEG7_MASK 0x000007ffUL
#define VPDSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_BASE_SEG7_MASK 0x0003f000UL

// VPDSCL_EASF_H_BF3_PWL_SEG0
#define VPDSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_IN_SEG0_MASK 0x00000fffUL
#define VPDSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_BASE_SEG0_MASK 0x0007f000UL
#define VPDSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_SLOPE_SEG0_MASK 0xfff80000UL

// VPDSCL_EASF_H_BF3_PWL_SEG1
#define VPDSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_IN_SEG1_MASK 0x00000fffUL
#define VPDSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_BASE_SEG1_MASK 0x0007f000UL
#define VPDSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_SLOPE_SEG1_MASK 0xfff80000UL

// VPDSCL_EASF_H_BF3_PWL_SEG2
#define VPDSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_IN_SEG2_MASK 0x00000fffUL
#define VPDSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_BASE_SEG2_MASK 0x0007f000UL
#define VPDSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_SLOPE_SEG2_MASK 0xfff80000UL

// VPDSCL_EASF_H_BF3_PWL_SEG3
#define VPDSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_IN_SEG3_MASK 0x00000fffUL
#define VPDSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_BASE_SEG3_MASK 0x0007f000UL
#define VPDSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_SLOPE_SEG3_MASK 0xfff80000UL

// VPDSCL_EASF_H_BF3_PWL_SEG4
#define VPDSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_IN_SEG4_MASK 0x00000fffUL
#define VPDSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_BASE_SEG4_MASK 0x0007f000UL
#define VPDSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_SLOPE_SEG4_MASK 0xfff80000UL

// VPDSCL_EASF_H_BF3_PWL_SEG5
#define VPDSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_IN_SEG5_MASK 0x00000fffUL
#define VPDSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_BASE_SEG5_MASK 0x0007f000UL

// VPDSCL_EASF_V_BF3_PWL_SEG0
#define VPDSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_IN_SEG0_MASK 0x00000fffUL
#define VPDSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_BASE_SEG0_MASK 0x0007f000UL
#define VPDSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_SLOPE_SEG0_MASK 0xfff80000UL

// VPDSCL_EASF_V_BF3_PWL_SEG1
#define VPDSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_IN_SEG1_MASK 0x00000fffUL
#define VPDSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_BASE_SEG1_MASK 0x0007f000UL
#define VPDSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_SLOPE_SEG1_MASK 0xfff80000UL

// VPDSCL_EASF_V_BF3_PWL_SEG2
#define VPDSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_IN_SEG2_MASK 0x00000fffUL
#define VPDSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_BASE_SEG2_MASK 0x0007f000UL
#define VPDSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_SLOPE_SEG2_MASK 0xfff80000UL

// VPDSCL_EASF_V_BF3_PWL_SEG3
#define VPDSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_IN_SEG3_MASK 0x00000fffUL
#define VPDSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_BASE_SEG3_MASK 0x0007f000UL
#define VPDSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_SLOPE_SEG3_MASK 0xfff80000UL

// VPDSCL_EASF_V_BF3_PWL_SEG4
#define VPDSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_IN_SEG4_MASK 0x00000fffUL
#define VPDSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_BASE_SEG4_MASK 0x0007f000UL
#define VPDSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_SLOPE_SEG4_MASK 0xfff80000UL

// VPDSCL_EASF_V_BF3_PWL_SEG5
#define VPDSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_IN_SEG5_MASK 0x00000fffUL
#define VPDSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_BASE_SEG5_MASK 0x0007f000UL

// VPISHARP_MODE
#define VPISHARP_MODE__ISHARP_EN_MASK                      0x00000001UL
#define VPISHARP_MODE__ISHARP_NOISEDET_EN_MASK             0x00000010UL
#define VPISHARP_MODE__ISHARP_NOISEDET_MODE_MASK           0x00000060UL
#define VPISHARP_MODE__ISHARP_LBA_MODE_MASK                0x00000200UL
#define VPISHARP_MODE__ISHARP_FMT_MODE_MASK                0x00000800UL
#define VPISHARP_MODE__ISHARP_FMT_NORM_MASK                0x0ffff000UL
#define VPISHARP_MODE__ISHARP_DELTA_LUT_SELECT_CURRENT_MASK 0x10000000UL

// VPISHARP_DELTA_CTRL
#define VPISHARP_DELTA_CTRL__ISHARP_DELTA_LUT_HOST_SELECT_MASK 0x00000001UL

// VPISHARP_DELTA_INDEX
#define VPISHARP_DELTA_INDEX__ISHARP_DELTA_INDEX_MASK      0x0000001fUL

// VPISHARP_DELTA_DATA
#define VPISHARP_DELTA_DATA__ISHARP_DELTA_DATA_MASK        0xffffffffUL

// VPISHARP_NLDELTA_SOFT_CLIP
#define VPISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_P_MASK 0x00000001UL
#define VPISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_P_MASK 0x000000feUL
#define VPISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_P_MASK 0x0000ff00UL
#define VPISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_N_MASK 0x00010000UL
#define VPISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_N_MASK 0x00fe0000UL
#define VPISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_N_MASK 0xff000000UL

// VPISHARP_NOISEDET_THRESHOLD
#define VPISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_UTHRE_MASK 0x000003ffUL
#define VPISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_DTHRE_MASK 0x03ff0000UL

// VPISHARP_NOISE_GAIN_PWL
#define VPISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_START_IN_MASK 0x0000001fUL
#define VPISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_END_IN_MASK 0x00001f00UL
#define VPISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_SLOPE_MASK 0x3fff0000UL

// VPISHARP_LBA_PWL_SEG0
#define VPISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_IN_SEG0_MASK 0x000003ffUL
#define VPISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_BASE_SEG0_MASK 0x0003f000UL
#define VPISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_SLOPE_SEG0_MASK 0x1ff00000UL

// VPISHARP_LBA_PWL_SEG1
#define VPISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_IN_SEG1_MASK 0x000003ffUL
#define VPISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_BASE_SEG1_MASK 0x0003f000UL
#define VPISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_SLOPE_SEG1_MASK 0x1ff00000UL

// VPISHARP_LBA_PWL_SEG2
#define VPISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_IN_SEG2_MASK 0x000003ffUL
#define VPISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_BASE_SEG2_MASK 0x0003f000UL
#define VPISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_SLOPE_SEG2_MASK 0x1ff00000UL

// VPISHARP_LBA_PWL_SEG3
#define VPISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_IN_SEG3_MASK 0x000003ffUL
#define VPISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_BASE_SEG3_MASK 0x0003f000UL
#define VPISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_SLOPE_SEG3_MASK 0x1ff00000UL

// VPISHARP_LBA_PWL_SEG4
#define VPISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_IN_SEG4_MASK 0x000003ffUL
#define VPISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_BASE_SEG4_MASK 0x0003f000UL
#define VPISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_SLOPE_SEG4_MASK 0x1ff00000UL

// VPISHARP_LBA_PWL_SEG5
#define VPISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_IN_SEG5_MASK 0x000003ffUL
#define VPISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_BASE_SEG5_MASK 0x0003f000UL

// VPISHARP_DELTA_LUT_MEM_PWR_CTRL
#define VPISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_FORCE_MASK 0x00000003UL
#define VPISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_DIS_MASK 0x00000004UL
#define VPISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_STATE_MASK 0x00000030UL

// VPDSCL_DEBUG
#define VPDSCL_DEBUG__SCL_DEBUG_MASK                       0xffffffffUL

// VPDSCL_TEST_DEBUG_INDEX
#define VPDSCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK 0x000000ffUL
#define VPDSCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK 0x00000100UL

// VPDSCL_TEST_DEBUG_DATA
#define VPDSCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK   0xffffffffUL

// VPCM_CONTROL
#define VPCM_CONTROL__VPCM_BYPASS_MASK                     0x00000001UL
#define VPCM_CONTROL__VPCM_UPDATE_PENDING_MASK             0x00000100UL

// VPCM_POST_CSC_CONTROL
#define VPCM_POST_CSC_CONTROL__VPCM_POST_CSC_MODE_MASK     0x00000001UL
#define VPCM_POST_CSC_CONTROL__VPCM_POST_CSC_MODE_CURRENT_MASK 0x00000004UL

// VPCM_POST_CSC_C11_C12
#define VPCM_POST_CSC_C11_C12__VPCM_POST_CSC_C11_MASK      0x0000ffffUL
#define VPCM_POST_CSC_C11_C12__VPCM_POST_CSC_C12_MASK      0xffff0000UL

// VPCM_POST_CSC_C13_C14
#define VPCM_POST_CSC_C13_C14__VPCM_POST_CSC_C13_MASK      0x0000ffffUL
#define VPCM_POST_CSC_C13_C14__VPCM_POST_CSC_C14_MASK      0xffff0000UL

// VPCM_POST_CSC_C21_C22
#define VPCM_POST_CSC_C21_C22__VPCM_POST_CSC_C21_MASK      0x0000ffffUL
#define VPCM_POST_CSC_C21_C22__VPCM_POST_CSC_C22_MASK      0xffff0000UL

// VPCM_POST_CSC_C23_C24
#define VPCM_POST_CSC_C23_C24__VPCM_POST_CSC_C23_MASK      0x0000ffffUL
#define VPCM_POST_CSC_C23_C24__VPCM_POST_CSC_C24_MASK      0xffff0000UL

// VPCM_POST_CSC_C31_C32
#define VPCM_POST_CSC_C31_C32__VPCM_POST_CSC_C31_MASK      0x0000ffffUL
#define VPCM_POST_CSC_C31_C32__VPCM_POST_CSC_C32_MASK      0xffff0000UL

// VPCM_POST_CSC_C33_C34
#define VPCM_POST_CSC_C33_C34__VPCM_POST_CSC_C33_MASK      0x0000ffffUL
#define VPCM_POST_CSC_C33_C34__VPCM_POST_CSC_C34_MASK      0xffff0000UL

// VPCM_BIAS_CR_R
#define VPCM_BIAS_CR_R__VPCM_BIAS_CR_R_MASK                0x0000ffffUL

// VPCM_BIAS_Y_G_CB_B
#define VPCM_BIAS_Y_G_CB_B__VPCM_BIAS_Y_G_MASK             0x0000ffffUL
#define VPCM_BIAS_Y_G_CB_B__VPCM_BIAS_CB_B_MASK            0xffff0000UL

// VPCM_GAMCOR_CONTROL
#define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_MODE_MASK         0x00000003UL
#define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_PWL_DISABLE_MASK  0x00000008UL
#define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_MODE_CURRENT_MASK 0x00000030UL
#define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_SELECT_CURRENT_MASK 0x00000040UL

// VPCM_GAMCOR_LUT_INDEX
#define VPCM_GAMCOR_LUT_INDEX__VPCM_GAMCOR_LUT_INDEX_MASK  0x000001ffUL

// VPCM_GAMCOR_LUT_DATA
#define VPCM_GAMCOR_LUT_DATA__VPCM_GAMCOR_LUT_DATA_MASK    0x0003ffffUL

// VPCM_GAMCOR_LUT_CONTROL
#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK 0x00000007UL
#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_READ_COLOR_SEL_MASK 0x00000018UL
#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_READ_DBG_MASK 0x00000020UL
#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_HOST_SEL_MASK 0x00000040UL
#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_CONFIG_MODE_MASK 0x00000080UL

// VPCM_GAMCOR_RAMA_START_CNTL_B
#define VPCM_GAMCOR_RAMA_START_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_B_MASK 0x0003ffffUL
#define VPCM_GAMCOR_RAMA_START_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07f00000UL

// VPCM_GAMCOR_RAMA_START_CNTL_G
#define VPCM_GAMCOR_RAMA_START_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_G_MASK 0x0003ffffUL
#define VPCM_GAMCOR_RAMA_START_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07f00000UL

// VPCM_GAMCOR_RAMA_START_CNTL_R
#define VPCM_GAMCOR_RAMA_START_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_R_MASK 0x0003ffffUL
#define VPCM_GAMCOR_RAMA_START_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07f00000UL

// VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B
#define VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003ffffUL

// VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G
#define VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003ffffUL

// VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R
#define VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003ffffUL

// VPCM_GAMCOR_RAMA_START_BASE_CNTL_B
#define VPCM_GAMCOR_RAMA_START_BASE_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003ffffUL

// VPCM_GAMCOR_RAMA_START_BASE_CNTL_G
#define VPCM_GAMCOR_RAMA_START_BASE_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003ffffUL

// VPCM_GAMCOR_RAMA_START_BASE_CNTL_R
#define VPCM_GAMCOR_RAMA_START_BASE_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003ffffUL

// VPCM_GAMCOR_RAMA_END_CNTL1_B
#define VPCM_GAMCOR_RAMA_END_CNTL1_B__VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003ffffUL

// VPCM_GAMCOR_RAMA_END_CNTL2_B
#define VPCM_GAMCOR_RAMA_END_CNTL2_B__VPCM_GAMCOR_RAMA_EXP_REGION_END_B_MASK 0x0000ffffUL
#define VPCM_GAMCOR_RAMA_END_CNTL2_B__VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xffff0000UL

// VPCM_GAMCOR_RAMA_END_CNTL1_G
#define VPCM_GAMCOR_RAMA_END_CNTL1_G__VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003ffffUL

// VPCM_GAMCOR_RAMA_END_CNTL2_G
#define VPCM_GAMCOR_RAMA_END_CNTL2_G__VPCM_GAMCOR_RAMA_EXP_REGION_END_G_MASK 0x0000ffffUL
#define VPCM_GAMCOR_RAMA_END_CNTL2_G__VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xffff0000UL

// VPCM_GAMCOR_RAMA_END_CNTL1_R
#define VPCM_GAMCOR_RAMA_END_CNTL1_R__VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003ffffUL

// VPCM_GAMCOR_RAMA_END_CNTL2_R
#define VPCM_GAMCOR_RAMA_END_CNTL2_R__VPCM_GAMCOR_RAMA_EXP_REGION_END_R_MASK 0x0000ffffUL
#define VPCM_GAMCOR_RAMA_END_CNTL2_R__VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xffff0000UL

// VPCM_GAMCOR_RAMA_OFFSET_B
#define VPCM_GAMCOR_RAMA_OFFSET_B__VPCM_GAMCOR_RAMA_OFFSET_B_MASK 0x0007ffffUL

// VPCM_GAMCOR_RAMA_OFFSET_G
#define VPCM_GAMCOR_RAMA_OFFSET_G__VPCM_GAMCOR_RAMA_OFFSET_G_MASK 0x0007ffffUL

// VPCM_GAMCOR_RAMA_OFFSET_R
#define VPCM_GAMCOR_RAMA_OFFSET_R__VPCM_GAMCOR_RAMA_OFFSET_R_MASK 0x0007ffffUL

// VPCM_GAMCOR_RAMA_REGION_0_1
#define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001ffUL
#define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000UL
#define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01ff0000UL
#define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000UL

// VPCM_GAMCOR_RAMA_REGION_2_3
#define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001ffUL
#define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000UL
#define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01ff0000UL
#define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000UL

// VPCM_GAMCOR_RAMA_REGION_4_5
#define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001ffUL
#define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000UL
#define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01ff0000UL
#define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000UL

// VPCM_GAMCOR_RAMA_REGION_6_7
#define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001ffUL
#define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000UL
#define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01ff0000UL
#define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000UL

// VPCM_GAMCOR_RAMA_REGION_8_9
#define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001ffUL
#define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000UL
#define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01ff0000UL
#define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000UL

// VPCM_GAMCOR_RAMA_REGION_10_11
#define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001ffUL
#define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000UL
#define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01ff0000UL
#define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000UL

// VPCM_GAMCOR_RAMA_REGION_12_13
#define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001ffUL
#define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000UL
#define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01ff0000UL
#define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000UL

// VPCM_GAMCOR_RAMA_REGION_14_15
#define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001ffUL
#define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000UL
#define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01ff0000UL
#define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000UL

// VPCM_GAMCOR_RAMA_REGION_16_17
#define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001ffUL
#define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000UL
#define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01ff0000UL
#define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000UL

// VPCM_GAMCOR_RAMA_REGION_18_19
#define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001ffUL
#define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000UL
#define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01ff0000UL
#define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000UL

// VPCM_GAMCOR_RAMA_REGION_20_21
#define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001ffUL
#define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000UL
#define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01ff0000UL
#define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000UL

// VPCM_GAMCOR_RAMA_REGION_22_23
#define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001ffUL
#define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000UL
#define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01ff0000UL
#define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000UL

// VPCM_GAMCOR_RAMA_REGION_24_25
#define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001ffUL
#define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000UL
#define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01ff0000UL
#define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000UL

// VPCM_GAMCOR_RAMA_REGION_26_27
#define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001ffUL
#define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000UL
#define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01ff0000UL
#define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000UL

// VPCM_GAMCOR_RAMA_REGION_28_29
#define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001ffUL
#define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000UL
#define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01ff0000UL
#define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000UL

// VPCM_GAMCOR_RAMA_REGION_30_31
#define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001ffUL
#define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000UL
#define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01ff0000UL
#define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000UL

// VPCM_GAMCOR_RAMA_REGION_32_33
#define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001ffUL
#define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000UL
#define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01ff0000UL
#define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000UL

// VPCM_HDR_MULT_COEF
#define VPCM_HDR_MULT_COEF__VPCM_HDR_MULT_COEF_MASK        0x0007ffffUL

// VPCM_MEM_PWR_CTRL
#define VPCM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK       0x00000003UL
#define VPCM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK         0x00000004UL
#define VPCM_MEM_PWR_CTRL__HIST_MEM_PWR_FORCE_MASK         0x00000100UL
#define VPCM_MEM_PWR_CTRL__HIST_MEM_PWR_DIS_MASK           0x00000200UL

// VPCM_MEM_PWR_STATUS
#define VPCM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK     0x00000003UL
#define VPCM_MEM_PWR_STATUS__HIST_MEM_PWR_STATE_MASK       0x00000100UL

// VPCM_DEALPHA
#define VPCM_DEALPHA__VPCM_DEALPHA_EN_MASK                 0x00000001UL
#define VPCM_DEALPHA__VPCM_DEALPHA_ABLND_MASK              0x00000002UL

// VPCM_COEF_FORMAT
#define VPCM_COEF_FORMAT__VPCM_BIAS_FORMAT_MASK            0x00000001UL
#define VPCM_COEF_FORMAT__VPCM_POST_CSC_COEF_FORMAT_MASK   0x00000010UL

// VPCM_TEST_DEBUG_INDEX
#define VPCM_TEST_DEBUG_INDEX__VPCM_TEST_DEBUG_INDEX_MASK  0x000000ffUL
#define VPCM_TEST_DEBUG_INDEX__VPCM_TEST_DEBUG_WRITE_EN_MASK 0x00000100UL

// VPCM_TEST_DEBUG_DATA
#define VPCM_TEST_DEBUG_DATA__VPCM_TEST_DEBUG_DATA_MASK    0xffffffffUL

// VPCM_HIST_CNTL
#define VPCM_HIST_CNTL__VPCM_HIST_SEL_MASK                 0x00000003UL
#define VPCM_HIST_CNTL__VPCM_HIST_CH_EN_MASK               0x0000000cUL
#define VPCM_HIST_CNTL__VPCM_HIST_SRC1_SEL_MASK            0x00000010UL
#define VPCM_HIST_CNTL__VPCM_HIST_SRC2_SEL_MASK            0x00000020UL
#define VPCM_HIST_CNTL__VPCM_HIST_SRC3_SEL_MASK            0x00000040UL
#define VPCM_HIST_CNTL__VPCM_HIST_CH1_XBAR_MASK            0x00000180UL
#define VPCM_HIST_CNTL__VPCM_HIST_CH2_XBAR_MASK            0x00000600UL
#define VPCM_HIST_CNTL__VPCM_HIST_CH3_XBAR_MASK            0x00001800UL
#define VPCM_HIST_CNTL__VPCM_HIST_FORMAT_MASK              0x00006000UL
#define VPCM_HIST_CNTL__VPCM_HIST_READ_CHANNEL_MASK_MASK   0x00038000UL

// VPCM_HIST_SCALE_SRC1
#define VPCM_HIST_SCALE_SRC1__VPCM_HIST_SCALE_SRC1_MASK    0x0007ffffUL

// VPCM_HIST_COEFA_SRC2
#define VPCM_HIST_COEFA_SRC2__VPCM_HIST_COEFA_SRC2_MASK    0x0007ffffUL

// VPCM_HIST_COEFB_SRC2
#define VPCM_HIST_COEFB_SRC2__VPCM_HIST_COEFB_SRC2_MASK    0x0007ffffUL

// VPCM_HIST_COEFC_SRC2
#define VPCM_HIST_COEFC_SRC2__VPCM_HIST_COEFC_SRC2_MASK    0x0007ffffUL

// VPCM_HIST_SCALE_SRC3
#define VPCM_HIST_SCALE_SRC3__VPCM_HIST_SCALE_SRC3_MASK    0x0007ffffUL

// VPCM_HIST_BIAS_SRC1
#define VPCM_HIST_BIAS_SRC1__VPCM_HIST_BIAS_SRC1_MASK      0x0007ffffUL

// VPCM_HIST_BIAS_SRC2
#define VPCM_HIST_BIAS_SRC2__VPCM_HIST_BIAS_SRC2_MASK      0x0007ffffUL

// VPCM_HIST_BIAS_SRC3
#define VPCM_HIST_BIAS_SRC3__VPCM_HIST_BIAS_SRC3_MASK      0x0007ffffUL

// VPCM_HIST_LOCK
#define VPCM_HIST_LOCK__VPCM_HIST_LOCK_MASK                0x00000001UL

// VPCM_HIST_INDEX
#define VPCM_HIST_INDEX__VPCM_HIST_INDEX_MASK              0x000000ffUL

// VPCM_HIST_DATA
#define VPCM_HIST_DATA__VPCM_HIST_DATA_MASK                0x01ffffffUL

// VPCM_HIST_STATUS
#define VPCM_HIST_STATUS__VPCM_HIST_RDY_STATUS_MASK        0x00000001UL
#define VPCM_HIST_STATUS__VPCM_HIST_FRAME_COLLECT_SKIPPED_MASK 0x00000010UL
#define VPCM_HIST_STATUS__VPCM_HIST_FRAME_COLLECT_SKIPPED_CURRENT_MASK 0x00000020UL
#define VPCM_HIST_STATUS__VPCM_HIST_FRAME_COLLECT_SKIPPED_CNT_MASK 0x000001c0UL
#define VPCM_HIST_STATUS__VPCM_HIST_TX_NOT_COMPLETED_MASK  0x00010000UL
#define VPCM_HIST_STATUS__VPCM_HIST_TX_NOT_COMPLETED_CURRENT_MASK 0x00020000UL
#define VPCM_HIST_STATUS__VPCM_HIST_TX_STATUS_MASK         0x000c0000UL
#define VPCM_HIST_STATUS__VPCM_HIST_COUNT_OVERFLOW_MASK    0x01000000UL
#define VPCM_HIST_STATUS__VPCM_HIST_COUNT_OVERFLOW_CURRENT_MASK 0x02000000UL
#define VPCM_HIST_STATUS__VPCM_HIST_COLLECT_INCOMPLETE_MASK 0x04000000UL
#define VPCM_HIST_STATUS__VPCM_HIST_COLLECT_INCOMPLETE_CURRENT_MASK 0x08000000UL

// VPDPP_CONTROL
#define VPDPP_CONTROL__VPECLK_G_GATE_DISABLE_MASK          0x00000100UL
#define VPDPP_CONTROL__VPECLK_G_VPDSCL_GATE_DISABLE_MASK   0x00001000UL
#define VPDPP_CONTROL__VPECLK_R_GATE_DISABLE_MASK          0x00004000UL
#define VPDPP_CONTROL__VPDPP_FGCG_REP_DIS_MASK             0x01000000UL

// VPDPP_SOFT_RESET
#define VPDPP_SOFT_RESET__VPCNVC_SOFT_RESET_MASK           0x00000001UL
#define VPDPP_SOFT_RESET__VPDSCL_SOFT_RESET_MASK           0x00000010UL
#define VPDPP_SOFT_RESET__VPCM_SOFT_RESET_MASK             0x00000100UL
#define VPDPP_SOFT_RESET__VPOBUF_SOFT_RESET_MASK           0x00001000UL
#define VPDPP_SOFT_RESET__VPHIST_SOFT_RESET_MASK           0x00010000UL

// VPDPP_CRC_VAL_R_G
#define VPDPP_CRC_VAL_R_G__VPDPP_CRC_R_CR_MASK             0x0000ffffUL
#define VPDPP_CRC_VAL_R_G__VPDPP_CRC_G_Y_MASK              0xffff0000UL

// VPDPP_CRC_VAL_B_A
#define VPDPP_CRC_VAL_B_A__VPDPP_CRC_B_CB_MASK             0x0000ffffUL
#define VPDPP_CRC_VAL_B_A__VPDPP_CRC_ALPHA_MASK            0xffff0000UL

// VPDPP_CRC_CTRL
#define VPDPP_CRC_CTRL__VPDPP_CRC_EN_MASK                  0x00000001UL
#define VPDPP_CRC_CTRL__VPDPP_CRC_CONT_EN_MASK             0x00000002UL
#define VPDPP_CRC_CTRL__VPDPP_CRC_ONE_SHOT_PENDING_MASK    0x00000004UL
#define VPDPP_CRC_CTRL__VPDPP_CRC_420_COMP_SEL_MASK        0x00000008UL
#define VPDPP_CRC_CTRL__VPDPP_CRC_SRC_SEL_MASK             0x00000030UL
#define VPDPP_CRC_CTRL__VPDPP_CRC_PIX_FORMAT_SEL_MASK      0x00003800UL
#define VPDPP_CRC_CTRL__VPDPP_CRC_MASK_MASK                0xffff0000UL

// VPHOST_READ_CONTROL
#define VPHOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK   0x000000ffUL

// VPDPP_DEBUG_SEL
#define VPDPP_DEBUG_SEL__VPDPP_VPECLK_DEBUG_BUS_SEL_MASK   0x00000007UL
#define VPDPP_DEBUG_SEL__VPDPP_DBG_EN_MASK                 0x80000000UL

// VPDPP_DEBUG_SPARE
#define VPDPP_DEBUG_SPARE__VPDPP_DEBUG_SPARE_MASK          0xffffffffUL

// VPDPP_TEST_DEBUG_INDEX
#define VPDPP_TEST_DEBUG_INDEX__VPDPP_TEST_DEBUG_INDEX_MASK 0x000000ffUL
#define VPDPP_TEST_DEBUG_INDEX__VPDPP_TEST_DEBUG_WRITE_EN_MASK 0x00000100UL

// VPDPP_TEST_DEBUG_DATA
#define VPDPP_TEST_DEBUG_DATA__VPDPP_TEST_DEBUG_DATA_MASK  0xffffffffUL

// VPMPC_CLOCK_CONTROL
#define VPMPC_CLOCK_CONTROL__VPECLK_G_GATE_DISABLE_MASK    0x00000001UL
#define VPMPC_CLOCK_CONTROL__VPECLK_R_GATE_DISABLE_MASK    0x00000002UL

// VPMPC_SOFT_RESET
#define VPMPC_SOFT_RESET__VPMPCC0_SOFT_RESET_MASK          0x00000001UL
#define VPMPC_SOFT_RESET__VPMPCC1_SOFT_RESET_MASK          0x00000002UL
#define VPMPC_SOFT_RESET__VPMPC_SFR0_SOFT_RESET_MASK       0x00000400UL
#define VPMPC_SOFT_RESET__VPMPC_SFR1_SOFT_RESET_MASK       0x00000800UL
#define VPMPC_SOFT_RESET__VPMPC_SFT0_SOFT_RESET_MASK       0x00100000UL
#define VPMPC_SOFT_RESET__VPMPC_SFT1_SOFT_RESET_MASK       0x00200000UL
#define VPMPC_SOFT_RESET__VPMPC_SOFT_RESET_MASK            0x80000000UL

// VPMPC_CRC_CTRL
#define VPMPC_CRC_CTRL__VPMPC_CRC_EN_MASK                  0x00000001UL
#define VPMPC_CRC_CTRL__VPMPC_CRC_CONT_EN_MASK             0x00000010UL
#define VPMPC_CRC_CTRL__VPMPC_CRC_SRC_SEL_MASK             0x03000000UL
#define VPMPC_CRC_CTRL__VPMPC_CRC_ONE_SHOT_PENDING_MASK    0x10000000UL
#define VPMPC_CRC_CTRL__VPMPC_CRC_UPDATE_ENABLED_MASK      0x40000000UL
#define VPMPC_CRC_CTRL__VPMPC_CRC_UPDATE_LOCK_MASK         0x80000000UL

// VPMPC_CRC_SEL_CONTROL
#define VPMPC_CRC_SEL_CONTROL__VPMPC_CRC_VPDPP_SEL_MASK    0x0000000fUL
#define VPMPC_CRC_SEL_CONTROL__VPMPC_CRC_VPOPP_SEL_MASK    0x000000f0UL
#define VPMPC_CRC_SEL_CONTROL__VPMPC_CRC_MASK_MASK         0xffff0000UL

// VPMPC_CRC_RESULT_AR
#define VPMPC_CRC_RESULT_AR__VPMPC_CRC_RESULT_A_MASK       0x0000ffffUL
#define VPMPC_CRC_RESULT_AR__VPMPC_CRC_RESULT_R_MASK       0xffff0000UL

// VPMPC_CRC_RESULT_GB
#define VPMPC_CRC_RESULT_GB__VPMPC_CRC_RESULT_G_MASK       0x0000ffffUL
#define VPMPC_CRC_RESULT_GB__VPMPC_CRC_RESULT_B_MASK       0xffff0000UL

// VPMPC_CRC_RESULT_C
#define VPMPC_CRC_RESULT_C__VPMPC_CRC_RESULT_C_MASK        0x0000ffffUL

// VPMPC_DEBUG_CONTROL
#define VPMPC_DEBUG_CONTROL__VPMPC_DEBUG_DATA_EN_MASK      0x00000001UL
#define VPMPC_DEBUG_CONTROL__VPMPC_DEBUG_TOP_DATA_SELECT_MASK 0x00000006UL
#define VPMPC_DEBUG_CONTROL__VPMPC_DEBUG_DATA_DIRECT_OUT_SELECT_MASK 0x00000070UL
#define VPMPC_DEBUG_CONTROL__VPMPC_DEBUG_DATA_DIRECT_OUT_SFR_SELECT_MASK 0x00000f00UL
#define VPMPC_DEBUG_CONTROL__VPMPC_DEBUG_DATA_DIRECT_OUT_SFT_SELECT_MASK 0x0000f000UL
#define VPMPC_DEBUG_CONTROL__VPMPC_RMCM_DEBUG_DATA_SELECT_MASK 0x00070000UL

// VPMPCC_DEBUG_DATA_SELECT
#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_SELECT0_MASK 0x0000000fUL
#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_BYTE_SELECT0_MASK 0x00000030UL
#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_OGAM_SELECT0_MASK 0x000000c0UL
#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_SELECT1_MASK 0x00000f00UL
#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_BYTE_SELECT1_MASK 0x00003000UL
#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_OGAM_SELECT1_MASK 0x0000c000UL
#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_SELECT2_MASK 0x000f0000UL
#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_BYTE_SELECT2_MASK 0x00300000UL
#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_OGAM_SELECT2_MASK 0x00c00000UL
#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_SELECT3_MASK 0x0f000000UL
#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_BYTE_SELECT3_MASK 0x30000000UL
#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_OGAM_SELECT3_MASK 0xc0000000UL

// VPMPC_BYPASS_BG_AR
#define VPMPC_BYPASS_BG_AR__VPMPC_BYPASS_BG_ALPHA_MASK     0x0000ffffUL
#define VPMPC_BYPASS_BG_AR__VPMPC_BYPASS_BG_R_CR_MASK      0xffff0000UL

// VPMPC_BYPASS_BG_GB
#define VPMPC_BYPASS_BG_GB__VPMPC_BYPASS_BG_G_Y_MASK       0x0000ffffUL
#define VPMPC_BYPASS_BG_GB__VPMPC_BYPASS_BG_B_CB_MASK      0xffff0000UL

// VPMPC_HOST_READ_CONTROL
#define VPMPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000ffUL

// VPMPC_PENDING_STATUS_MISC
#define VPMPC_PENDING_STATUS_MISC__VPMPCC0_CONFIG_UPDATE_PENDING_MASK 0x00000100UL
#define VPMPC_PENDING_STATUS_MISC__VPMPCC1_CONFIG_UPDATE_PENDING_MASK 0x00000200UL

// VPMPC_VPCDC0_3DLUT_FL_CONFIG
#define VPMPC_VPCDC0_3DLUT_FL_CONFIG__VPCDC0_3DLUT_FL_MODE_MASK 0x00000003UL
#define VPMPC_VPCDC0_3DLUT_FL_CONFIG__VPCDC0_3DLUT_FL_FORMAT_MASK 0x00000030UL

// VPMPC_VPCDC0_3DLUT_FL_BIAS_SCALE
#define VPMPC_VPCDC0_3DLUT_FL_BIAS_SCALE__VPCDC0_3DLUT_FL_BIAS_MASK 0x0000ffffUL
#define VPMPC_VPCDC0_3DLUT_FL_BIAS_SCALE__VPCDC0_3DLUT_FL_SCALE_MASK 0xffff0000UL

// VPMPC_CFG_TEST_DEBUG_INDEX
#define VPMPC_CFG_TEST_DEBUG_INDEX__VPMPC_CFG_TEST_DEBUG_INDEX_MASK 0x000000ffUL
#define VPMPC_CFG_TEST_DEBUG_INDEX__VPMPC_CFG_TEST_DEBUG_WRITE_EN_MASK 0x00000100UL

// VPMPC_CFG_TEST_DEBUG_DATA
#define VPMPC_CFG_TEST_DEBUG_DATA__VPMPC_CFG_TEST_DEBUG_DATA_MASK 0xffffffffUL

// VPMPC_OUT0_MUX
#define VPMPC_OUT0_MUX__VPMPC_OUT_MUX_MASK                 0x0000000fUL

// VPMPC_OUT0_FLOAT_CONTROL
#define VPMPC_OUT0_FLOAT_CONTROL__VPMPC_OUT_FLOAT_EN_MASK  0x00000001UL

// VPMPC_OUT0_DENORM_CONTROL
#define VPMPC_OUT0_DENORM_CONTROL__VPMPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000fffUL
#define VPMPC_OUT0_DENORM_CONTROL__VPMPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00fff000UL
#define VPMPC_OUT0_DENORM_CONTROL__VPMPC_OUT_DENORM_MODE_MASK 0x07000000UL

// VPMPC_OUT0_DENORM_CLAMP_G_Y
#define VPMPC_OUT0_DENORM_CLAMP_G_Y__VPMPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000fffUL
#define VPMPC_OUT0_DENORM_CLAMP_G_Y__VPMPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00fff000UL

// VPMPC_OUT0_DENORM_CLAMP_B_CB
#define VPMPC_OUT0_DENORM_CLAMP_B_CB__VPMPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000fffUL
#define VPMPC_OUT0_DENORM_CLAMP_B_CB__VPMPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00fff000UL

// VPMPC_OUT1_MUX
#define VPMPC_OUT1_MUX__VPMPC_OUT_MUX_MASK                 0x0000000fUL

// VPMPC_OUT1_FLOAT_CONTROL
#define VPMPC_OUT1_FLOAT_CONTROL__VPMPC_OUT_FLOAT_EN_MASK  0x00000001UL

// VPMPC_OUT1_DENORM_CONTROL
#define VPMPC_OUT1_DENORM_CONTROL__VPMPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000fffUL
#define VPMPC_OUT1_DENORM_CONTROL__VPMPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00fff000UL
#define VPMPC_OUT1_DENORM_CONTROL__VPMPC_OUT_DENORM_MODE_MASK 0x07000000UL

// VPMPC_OUT1_DENORM_CLAMP_G_Y
#define VPMPC_OUT1_DENORM_CLAMP_G_Y__VPMPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000fffUL
#define VPMPC_OUT1_DENORM_CLAMP_G_Y__VPMPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00fff000UL

// VPMPC_OUT1_DENORM_CLAMP_B_CB
#define VPMPC_OUT1_DENORM_CLAMP_B_CB__VPMPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000fffUL
#define VPMPC_OUT1_DENORM_CLAMP_B_CB__VPMPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00fff000UL

// VPMPC_OUT_CSC_COEF_FORMAT
#define VPMPC_OUT_CSC_COEF_FORMAT__VPMPC_OCSC0_COEF_FORMAT_MASK 0x00000001UL
#define VPMPC_OUT_CSC_COEF_FORMAT__VPMPC_OCSC1_COEF_FORMAT_MASK 0x00000002UL

// VPMPC_OUT0_CSC_MODE
#define VPMPC_OUT0_CSC_MODE__VPMPC_OCSC_MODE_MASK          0x00000001UL
#define VPMPC_OUT0_CSC_MODE__VPMPC_OCSC_MODE_CURRENT_MASK  0x00000080UL

// VPMPC_OUT0_CSC_C11_C12_A
#define VPMPC_OUT0_CSC_C11_C12_A__VPMPC_OCSC_C11_A_MASK    0x0000ffffUL
#define VPMPC_OUT0_CSC_C11_C12_A__VPMPC_OCSC_C12_A_MASK    0xffff0000UL

// VPMPC_OUT0_CSC_C13_C14_A
#define VPMPC_OUT0_CSC_C13_C14_A__VPMPC_OCSC_C13_A_MASK    0x0000ffffUL
#define VPMPC_OUT0_CSC_C13_C14_A__VPMPC_OCSC_C14_A_MASK    0xffff0000UL

// VPMPC_OUT0_CSC_C21_C22_A
#define VPMPC_OUT0_CSC_C21_C22_A__VPMPC_OCSC_C21_A_MASK    0x0000ffffUL
#define VPMPC_OUT0_CSC_C21_C22_A__VPMPC_OCSC_C22_A_MASK    0xffff0000UL

// VPMPC_OUT0_CSC_C23_C24_A
#define VPMPC_OUT0_CSC_C23_C24_A__VPMPC_OCSC_C23_A_MASK    0x0000ffffUL
#define VPMPC_OUT0_CSC_C23_C24_A__VPMPC_OCSC_C24_A_MASK    0xffff0000UL

// VPMPC_OUT0_CSC_C31_C32_A
#define VPMPC_OUT0_CSC_C31_C32_A__VPMPC_OCSC_C31_A_MASK    0x0000ffffUL
#define VPMPC_OUT0_CSC_C31_C32_A__VPMPC_OCSC_C32_A_MASK    0xffff0000UL

// VPMPC_OUT0_CSC_C33_C34_A
#define VPMPC_OUT0_CSC_C33_C34_A__VPMPC_OCSC_C33_A_MASK    0x0000ffffUL
#define VPMPC_OUT0_CSC_C33_C34_A__VPMPC_OCSC_C34_A_MASK    0xffff0000UL

// VPMPC_OUT1_CSC_MODE
#define VPMPC_OUT1_CSC_MODE__VPMPC_OCSC_MODE_MASK          0x00000001UL
#define VPMPC_OUT1_CSC_MODE__VPMPC_OCSC_MODE_CURRENT_MASK  0x00000080UL

// VPMPC_OUT1_CSC_C11_C12_A
#define VPMPC_OUT1_CSC_C11_C12_A__VPMPC_OCSC_C11_A_MASK    0x0000ffffUL
#define VPMPC_OUT1_CSC_C11_C12_A__VPMPC_OCSC_C12_A_MASK    0xffff0000UL

// VPMPC_OUT1_CSC_C13_C14_A
#define VPMPC_OUT1_CSC_C13_C14_A__VPMPC_OCSC_C13_A_MASK    0x0000ffffUL
#define VPMPC_OUT1_CSC_C13_C14_A__VPMPC_OCSC_C14_A_MASK    0xffff0000UL

// VPMPC_OUT1_CSC_C21_C22_A
#define VPMPC_OUT1_CSC_C21_C22_A__VPMPC_OCSC_C21_A_MASK    0x0000ffffUL
#define VPMPC_OUT1_CSC_C21_C22_A__VPMPC_OCSC_C22_A_MASK    0xffff0000UL

// VPMPC_OUT1_CSC_C23_C24_A
#define VPMPC_OUT1_CSC_C23_C24_A__VPMPC_OCSC_C23_A_MASK    0x0000ffffUL
#define VPMPC_OUT1_CSC_C23_C24_A__VPMPC_OCSC_C24_A_MASK    0xffff0000UL

// VPMPC_OUT1_CSC_C31_C32_A
#define VPMPC_OUT1_CSC_C31_C32_A__VPMPC_OCSC_C31_A_MASK    0x0000ffffUL
#define VPMPC_OUT1_CSC_C31_C32_A__VPMPC_OCSC_C32_A_MASK    0xffff0000UL

// VPMPC_OUT1_CSC_C33_C34_A
#define VPMPC_OUT1_CSC_C33_C34_A__VPMPC_OCSC_C33_A_MASK    0x0000ffffUL
#define VPMPC_OUT1_CSC_C33_C34_A__VPMPC_OCSC_C34_A_MASK    0xffff0000UL

// VPMPC_OCSC_TEST_DEBUG_INDEX
#define VPMPC_OCSC_TEST_DEBUG_INDEX__VPMPC_OCSC_TEST_DEBUG_INDEX_MASK 0x000000ffUL
#define VPMPC_OCSC_TEST_DEBUG_INDEX__VPMPC_OCSC_TEST_DEBUG_WRITE_EN_MASK 0x00000100UL

// VPMPC_OCSC_TEST_DEBUG_DATA
#define VPMPC_OCSC_TEST_DEBUG_DATA__VPMPC_OCSC_TEST_DEBUG_DATA_MASK 0xffffffffUL

// VPMPCC_TOP_SEL
#define VPMPCC_TOP_SEL__VPMPCC_TOP_SEL_MASK                0x0000000fUL

// VPMPCC_BOT_SEL
#define VPMPCC_BOT_SEL__VPMPCC_BOT_SEL_MASK                0x0000000fUL

// VPMPCC_VPOPP_ID
#define VPMPCC_VPOPP_ID__VPMPCC_VPOPP_ID_MASK              0x0000000fUL

// VPMPCC_CONTROL
#define VPMPCC_CONTROL__VPMPCC_MODE_MASK                   0x00000003UL
#define VPMPCC_CONTROL__VPMPCC_ALPHA_BLND_MODE_MASK        0x00000030UL
#define VPMPCC_CONTROL__VPMPCC_ALPHA_MULTIPLIED_MODE_MASK  0x00000040UL
#define VPMPCC_CONTROL__VPMPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080UL
#define VPMPCC_CONTROL__VPMPCC_BOT_GAIN_MODE_MASK          0x00000800UL

// VPMPCC_CONTROL2
#define VPMPCC_CONTROL2__VPMPCC_GLOBAL_ALPHA_MASK          0x00000fffUL
#define VPMPCC_CONTROL2__VPMPCC_GLOBAL_GAIN_MASK           0x0fff0000UL

// VPMPCC_TOP_GAIN
#define VPMPCC_TOP_GAIN__VPMPCC_TOP_GAIN_MASK              0x0007ffffUL

// VPMPCC_BOT_GAIN_INSIDE
#define VPMPCC_BOT_GAIN_INSIDE__VPMPCC_BOT_GAIN_INSIDE_MASK 0x0007ffffUL

// VPMPCC_BOT_GAIN_OUTSIDE
#define VPMPCC_BOT_GAIN_OUTSIDE__VPMPCC_BOT_GAIN_OUTSIDE_MASK 0x0007ffffUL

// VPMPCC_MOVABLE_CM_LOCATION_CONTROL
#define VPMPCC_MOVABLE_CM_LOCATION_CONTROL__VPMPCC_MOVABLE_CM_LOCATION_CNTL_MASK 0x00000001UL
#define VPMPCC_MOVABLE_CM_LOCATION_CONTROL__VPMPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK 0x00000010UL

// VPMPCC_BG_R_CR
#define VPMPCC_BG_R_CR__VPMPCC_BG_R_CR_MASK                0x0007ffffUL

// VPMPCC_BG_G_Y
#define VPMPCC_BG_G_Y__VPMPCC_BG_G_Y_MASK                  0x0007ffffUL

// VPMPCC_BG_B_CB
#define VPMPCC_BG_B_CB__VPMPCC_BG_B_CB_MASK                0x0007ffffUL

// VPMPCC_MEM_PWR_CTRL
#define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003UL
#define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_PWR_DIS_MASK  0x00000004UL
#define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_LOW_PWR_MODE_MASK 0x00000030UL
#define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_PWR_STATE_MASK 0x00000300UL

// VPMPCC_STATUS
#define VPMPCC_STATUS__VPMPCC_IDLE_MASK                    0x00000001UL
#define VPMPCC_STATUS__VPMPCC_BUSY_MASK                    0x00000002UL
#define VPMPCC_STATUS__VPMPCC_DISABLED_MASK                0x00000004UL

// VPMPCC_TEST_DEBUG_INDEX
#define VPMPCC_TEST_DEBUG_INDEX__VPMPCC_TEST_DEBUG_INDEX_MASK 0x000000ffUL
#define VPMPCC_TEST_DEBUG_INDEX__VPMPCC_TEST_DEBUG_WRITE_EN_MASK 0x00000100UL

// VPMPCC_TEST_DEBUG_DATA
#define VPMPCC_TEST_DEBUG_DATA__VPMPCC_TEST_DEBUG_DATA_MASK 0xffffffffUL

// VPMPCC_OGAM_CONTROL
#define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_MODE_MASK         0x00000003UL
#define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_PWL_DISABLE_MASK  0x00000008UL
#define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_MODE_CURRENT_MASK 0x00000180UL
#define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_SELECT_CURRENT_MASK 0x00000200UL

// VPMPCC_OGAM_LUT_INDEX
#define VPMPCC_OGAM_LUT_INDEX__VPMPCC_OGAM_LUT_INDEX_MASK  0x000001ffUL

// VPMPCC_OGAM_LUT_DATA
#define VPMPCC_OGAM_LUT_DATA__VPMPCC_OGAM_LUT_DATA_MASK    0x0003ffffUL

// VPMPCC_OGAM_LUT_CONTROL
#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007UL
#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_READ_COLOR_SEL_MASK 0x00000018UL
#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_READ_DBG_MASK 0x00000020UL
#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_HOST_SEL_MASK 0x00000040UL
#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_CONFIG_MODE_MASK 0x00000080UL

// VPMPCC_OGAM_RAMA_START_CNTL_B
#define VPMPCC_OGAM_RAMA_START_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003ffffUL
#define VPMPCC_OGAM_RAMA_START_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07f00000UL

// VPMPCC_OGAM_RAMA_START_CNTL_G
#define VPMPCC_OGAM_RAMA_START_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003ffffUL
#define VPMPCC_OGAM_RAMA_START_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07f00000UL

// VPMPCC_OGAM_RAMA_START_CNTL_R
#define VPMPCC_OGAM_RAMA_START_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003ffffUL
#define VPMPCC_OGAM_RAMA_START_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07f00000UL

// VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B
#define VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003ffffUL

// VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G
#define VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003ffffUL

// VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R
#define VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003ffffUL

// VPMPCC_OGAM_RAMA_START_BASE_CNTL_B
#define VPMPCC_OGAM_RAMA_START_BASE_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003ffffUL

// VPMPCC_OGAM_RAMA_START_BASE_CNTL_G
#define VPMPCC_OGAM_RAMA_START_BASE_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003ffffUL

// VPMPCC_OGAM_RAMA_START_BASE_CNTL_R
#define VPMPCC_OGAM_RAMA_START_BASE_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003ffffUL

// VPMPCC_OGAM_RAMA_END_CNTL1_B
#define VPMPCC_OGAM_RAMA_END_CNTL1_B__VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003ffffUL

// VPMPCC_OGAM_RAMA_END_CNTL2_B
#define VPMPCC_OGAM_RAMA_END_CNTL2_B__VPMPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000ffffUL
#define VPMPCC_OGAM_RAMA_END_CNTL2_B__VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xffff0000UL

// VPMPCC_OGAM_RAMA_END_CNTL1_G
#define VPMPCC_OGAM_RAMA_END_CNTL1_G__VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003ffffUL

// VPMPCC_OGAM_RAMA_END_CNTL2_G
#define VPMPCC_OGAM_RAMA_END_CNTL2_G__VPMPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000ffffUL
#define VPMPCC_OGAM_RAMA_END_CNTL2_G__VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xffff0000UL

// VPMPCC_OGAM_RAMA_END_CNTL1_R
#define VPMPCC_OGAM_RAMA_END_CNTL1_R__VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003ffffUL

// VPMPCC_OGAM_RAMA_END_CNTL2_R
#define VPMPCC_OGAM_RAMA_END_CNTL2_R__VPMPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000ffffUL
#define VPMPCC_OGAM_RAMA_END_CNTL2_R__VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xffff0000UL

// VPMPCC_OGAM_RAMA_OFFSET_B
#define VPMPCC_OGAM_RAMA_OFFSET_B__VPMPCC_OGAM_RAMA_OFFSET_B_MASK 0x0007ffffUL

// VPMPCC_OGAM_RAMA_OFFSET_G
#define VPMPCC_OGAM_RAMA_OFFSET_G__VPMPCC_OGAM_RAMA_OFFSET_G_MASK 0x0007ffffUL

// VPMPCC_OGAM_RAMA_OFFSET_R
#define VPMPCC_OGAM_RAMA_OFFSET_R__VPMPCC_OGAM_RAMA_OFFSET_R_MASK 0x0007ffffUL

// VPMPCC_OGAM_RAMA_REGION_0_1
#define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_OGAM_RAMA_REGION_2_3
#define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_OGAM_RAMA_REGION_4_5
#define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_OGAM_RAMA_REGION_6_7
#define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_OGAM_RAMA_REGION_8_9
#define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_OGAM_RAMA_REGION_10_11
#define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_OGAM_RAMA_REGION_12_13
#define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_OGAM_RAMA_REGION_14_15
#define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_OGAM_RAMA_REGION_16_17
#define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_OGAM_RAMA_REGION_18_19
#define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_OGAM_RAMA_REGION_20_21
#define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_OGAM_RAMA_REGION_22_23
#define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_OGAM_RAMA_REGION_24_25
#define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_OGAM_RAMA_REGION_26_27
#define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_OGAM_RAMA_REGION_28_29
#define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_OGAM_RAMA_REGION_30_31
#define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_OGAM_RAMA_REGION_32_33
#define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_GAMUT_REMAP_COEF_FORMAT
#define VPMPCC_GAMUT_REMAP_COEF_FORMAT__VPMPCC_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001UL

// VPMPCC_GAMUT_REMAP_MODE
#define VPMPCC_GAMUT_REMAP_MODE__VPMPCC_GAMUT_REMAP_MODE_MASK 0x00000001UL
#define VPMPCC_GAMUT_REMAP_MODE__VPMPCC_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000080UL

// VPMPC_GAMUT_REMAP_C11_C12_A
#define VPMPC_GAMUT_REMAP_C11_C12_A__VPMPCC_GAMUT_REMAP_C11_A_MASK 0x0000ffffUL
#define VPMPC_GAMUT_REMAP_C11_C12_A__VPMPCC_GAMUT_REMAP_C12_A_MASK 0xffff0000UL

// VPMPC_GAMUT_REMAP_C13_C14_A
#define VPMPC_GAMUT_REMAP_C13_C14_A__VPMPCC_GAMUT_REMAP_C13_A_MASK 0x0000ffffUL
#define VPMPC_GAMUT_REMAP_C13_C14_A__VPMPCC_GAMUT_REMAP_C14_A_MASK 0xffff0000UL

// VPMPC_GAMUT_REMAP_C21_C22_A
#define VPMPC_GAMUT_REMAP_C21_C22_A__VPMPCC_GAMUT_REMAP_C21_A_MASK 0x0000ffffUL
#define VPMPC_GAMUT_REMAP_C21_C22_A__VPMPCC_GAMUT_REMAP_C22_A_MASK 0xffff0000UL

// VPMPC_GAMUT_REMAP_C23_C24_A
#define VPMPC_GAMUT_REMAP_C23_C24_A__VPMPCC_GAMUT_REMAP_C23_A_MASK 0x0000ffffUL
#define VPMPC_GAMUT_REMAP_C23_C24_A__VPMPCC_GAMUT_REMAP_C24_A_MASK 0xffff0000UL

// VPMPC_GAMUT_REMAP_C31_C32_A
#define VPMPC_GAMUT_REMAP_C31_C32_A__VPMPCC_GAMUT_REMAP_C31_A_MASK 0x0000ffffUL
#define VPMPC_GAMUT_REMAP_C31_C32_A__VPMPCC_GAMUT_REMAP_C32_A_MASK 0xffff0000UL

// VPMPC_GAMUT_REMAP_C33_C34_A
#define VPMPC_GAMUT_REMAP_C33_C34_A__VPMPCC_GAMUT_REMAP_C33_A_MASK 0x0000ffffUL
#define VPMPC_GAMUT_REMAP_C33_C34_A__VPMPCC_GAMUT_REMAP_C34_A_MASK 0xffff0000UL

// VPMPCC_OGAM_TEST_DEBUG_INDEX
#define VPMPCC_OGAM_TEST_DEBUG_INDEX__VPMPCC_OGAM_TEST_DEBUG_INDEX_MASK 0x000000ffUL
#define VPMPCC_OGAM_TEST_DEBUG_INDEX__VPMPCC_OGAM_TEST_DEBUG_WRITE_EN_MASK 0x00000100UL

// VPMPCC_OGAM_TEST_DEBUG_DATA
#define VPMPCC_OGAM_TEST_DEBUG_DATA__VPMPCC_OGAM_TEST_DEBUG_DATA_MASK 0xffffffffUL

// VPMPCC_MCM_1DLUT_CONTROL
#define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_MODE_MASK 0x00000003UL
#define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_PWL_DISABLE_MASK 0x00000008UL
#define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_MODE_CURRENT_MASK 0x00000030UL
#define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_SELECT_CURRENT_MASK 0x00000040UL

// VPMPCC_MCM_1DLUT_LUT_INDEX
#define VPMPCC_MCM_1DLUT_LUT_INDEX__VPMPCC_MCM_1DLUT_LUT_INDEX_MASK 0x000001ffUL

// VPMPCC_MCM_1DLUT_LUT_DATA
#define VPMPCC_MCM_1DLUT_LUT_DATA__VPMPCC_MCM_1DLUT_LUT_DATA_MASK 0x0003ffffUL

// VPMPCC_MCM_1DLUT_LUT_CONTROL
#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK 0x00000007UL
#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK 0x00000018UL
#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_READ_DBG_MASK 0x00000020UL
#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_HOST_SEL_MASK 0x00000040UL
#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK 0x00000080UL

// VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B
#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK 0x0003ffffUL
#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07f00000UL

// VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G
#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK 0x0003ffffUL
#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07f00000UL

// VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R
#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK 0x0003ffffUL
#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07f00000UL

// VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B
#define VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003ffffUL

// VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G
#define VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003ffffUL

// VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R
#define VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003ffffUL

// VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B
#define VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003ffffUL

// VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G
#define VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003ffffUL

// VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R
#define VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003ffffUL

// VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B
#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003ffffUL

// VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B
#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK 0x0000ffffUL
#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xffff0000UL

// VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G
#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003ffffUL

// VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G
#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK 0x0000ffffUL
#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xffff0000UL

// VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R
#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003ffffUL

// VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R
#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK 0x0000ffffUL
#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xffff0000UL

// VPMPCC_MCM_1DLUT_RAMA_OFFSET_B
#define VPMPCC_MCM_1DLUT_RAMA_OFFSET_B__VPMPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK 0x0007ffffUL

// VPMPCC_MCM_1DLUT_RAMA_OFFSET_G
#define VPMPCC_MCM_1DLUT_RAMA_OFFSET_G__VPMPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK 0x0007ffffUL

// VPMPCC_MCM_1DLUT_RAMA_OFFSET_R
#define VPMPCC_MCM_1DLUT_RAMA_OFFSET_R__VPMPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK 0x0007ffffUL

// VPMPCC_MCM_1DLUT_RAMA_REGION_0_1
#define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_MCM_1DLUT_RAMA_REGION_2_3
#define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_MCM_1DLUT_RAMA_REGION_4_5
#define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_MCM_1DLUT_RAMA_REGION_6_7
#define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_MCM_1DLUT_RAMA_REGION_8_9
#define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_MCM_1DLUT_RAMA_REGION_10_11
#define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_MCM_1DLUT_RAMA_REGION_12_13
#define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_MCM_1DLUT_RAMA_REGION_14_15
#define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_MCM_1DLUT_RAMA_REGION_16_17
#define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_MCM_1DLUT_RAMA_REGION_18_19
#define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_MCM_1DLUT_RAMA_REGION_20_21
#define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_MCM_1DLUT_RAMA_REGION_22_23
#define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_MCM_1DLUT_RAMA_REGION_24_25
#define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_MCM_1DLUT_RAMA_REGION_26_27
#define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_MCM_1DLUT_RAMA_REGION_28_29
#define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_MCM_1DLUT_RAMA_REGION_30_31
#define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_MCM_1DLUT_RAMA_REGION_32_33
#define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT
#define VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001UL

// VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE
#define VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE__VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE_MASK 0x00000003UL
#define VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE__VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180UL

// VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA
#define VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C11_SETA_MASK 0x0000ffffUL
#define VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C12_SETA_MASK 0xffff0000UL

// VPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA
#define VPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C13_SETA_MASK 0x0000ffffUL
#define VPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C14_SETA_MASK 0xffff0000UL

// VPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA
#define VPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C21_SETA_MASK 0x0000ffffUL
#define VPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C22_SETA_MASK 0xffff0000UL

// VPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA
#define VPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C23_SETA_MASK 0x0000ffffUL
#define VPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C24_SETA_MASK 0xffff0000UL

// VPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA
#define VPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C31_SETA_MASK 0x0000ffffUL
#define VPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C32_SETA_MASK 0xffff0000UL

// VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA
#define VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C33_SETA_MASK 0x0000ffffUL
#define VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C34_SETA_MASK 0xffff0000UL

// VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT
#define VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001UL

// VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE
#define VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE__VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE_MASK 0x00000003UL
#define VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE__VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180UL

// VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA
#define VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C11_SETA_MASK 0x0000ffffUL
#define VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C12_SETA_MASK 0xffff0000UL

// VPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA
#define VPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C13_SETA_MASK 0x0000ffffUL
#define VPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C14_SETA_MASK 0xffff0000UL

// VPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA
#define VPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C21_SETA_MASK 0x0000ffffUL
#define VPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C22_SETA_MASK 0xffff0000UL

// VPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA
#define VPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C23_SETA_MASK 0x0000ffffUL
#define VPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C24_SETA_MASK 0xffff0000UL

// VPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA
#define VPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C31_SETA_MASK 0x0000ffffUL
#define VPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C32_SETA_MASK 0xffff0000UL

// VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA
#define VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C33_SETA_MASK 0x0000ffffUL
#define VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C34_SETA_MASK 0xffff0000UL

// VPMPCC_MCM_MEM_PWR_CTRL
#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK 0x00030000UL
#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_PWR_DIS_MASK 0x00040000UL
#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK 0x00300000UL
#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_PWR_STATE_MASK 0x30000000UL

// VPMPCC_MCM_TEST_DEBUG_INDEX
#define VPMPCC_MCM_TEST_DEBUG_INDEX__VPMPCC_MCM_TEST_DEBUG_INDEX_MASK 0x000000ffUL
#define VPMPCC_MCM_TEST_DEBUG_INDEX__VPMPCC_MCM_TEST_DEBUG_WRITE_EN_MASK 0x00000100UL

// VPMPCC_MCM_TEST_DEBUG_DATA
#define VPMPCC_MCM_TEST_DEBUG_DATA__VPMPCC_MCM_TEST_DEBUG_DATA_MASK 0xffffffffUL

// VPMPC_RMCM_SHAPER_CONTROL
#define VPMPC_RMCM_SHAPER_CONTROL__VPMPC_RMCM_SHAPER_LUT_MODE_MASK 0x00000003UL
#define VPMPC_RMCM_SHAPER_CONTROL__VPMPC_RMCM_SHAPER_MODE_CURRENT_MASK 0x0000000cUL
#define VPMPC_RMCM_SHAPER_CONTROL__VPMPC_RMCM_SHAPER_SELECT_CURRENT_MASK 0x00000010UL

// VPMPC_RMCM_SHAPER_OFFSET_R
#define VPMPC_RMCM_SHAPER_OFFSET_R__VPMPC_RMCM_SHAPER_OFFSET_R_MASK 0x0007ffffUL

// VPMPC_RMCM_SHAPER_OFFSET_G
#define VPMPC_RMCM_SHAPER_OFFSET_G__VPMPC_RMCM_SHAPER_OFFSET_G_MASK 0x0007ffffUL

// VPMPC_RMCM_SHAPER_OFFSET_B
#define VPMPC_RMCM_SHAPER_OFFSET_B__VPMPC_RMCM_SHAPER_OFFSET_B_MASK 0x0007ffffUL

// VPMPC_RMCM_SHAPER_SCALE_R
#define VPMPC_RMCM_SHAPER_SCALE_R__VPMPC_RMCM_SHAPER_SCALE_R_MASK 0x0000ffffUL

// VPMPC_RMCM_SHAPER_SCALE_G_B
#define VPMPC_RMCM_SHAPER_SCALE_G_B__VPMPC_RMCM_SHAPER_SCALE_G_MASK 0x0000ffffUL
#define VPMPC_RMCM_SHAPER_SCALE_G_B__VPMPC_RMCM_SHAPER_SCALE_B_MASK 0xffff0000UL

// VPMPC_RMCM_SHAPER_LUT_INDEX
#define VPMPC_RMCM_SHAPER_LUT_INDEX__VPMPC_RMCM_SHAPER_LUT_INDEX_MASK 0x000000ffUL

// VPMPC_RMCM_SHAPER_LUT_DATA
#define VPMPC_RMCM_SHAPER_LUT_DATA__VPMPC_RMCM_SHAPER_LUT_DATA_MASK 0x00ffffffUL

// VPMPC_RMCM_SHAPER_LUT_WRITE_EN_MASK
#define VPMPC_RMCM_SHAPER_LUT_WRITE_EN_MASK__VPMPC_RMCM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007UL
#define VPMPC_RMCM_SHAPER_LUT_WRITE_EN_MASK__VPMPC_RMCM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010UL

// VPMPC_RMCM_SHAPER_RAMA_START_CNTL_B
#define VPMPC_RMCM_SHAPER_RAMA_START_CNTL_B__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003ffffUL
#define VPMPC_RMCM_SHAPER_RAMA_START_CNTL_B__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07f00000UL

// VPMPC_RMCM_SHAPER_RAMA_START_CNTL_G
#define VPMPC_RMCM_SHAPER_RAMA_START_CNTL_G__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003ffffUL
#define VPMPC_RMCM_SHAPER_RAMA_START_CNTL_G__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07f00000UL

// VPMPC_RMCM_SHAPER_RAMA_START_CNTL_R
#define VPMPC_RMCM_SHAPER_RAMA_START_CNTL_R__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003ffffUL
#define VPMPC_RMCM_SHAPER_RAMA_START_CNTL_R__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07f00000UL

// VPMPC_RMCM_SHAPER_RAMA_END_CNTL_B
#define VPMPC_RMCM_SHAPER_RAMA_END_CNTL_B__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000ffffUL
#define VPMPC_RMCM_SHAPER_RAMA_END_CNTL_B__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3fff0000UL

// VPMPC_RMCM_SHAPER_RAMA_END_CNTL_G
#define VPMPC_RMCM_SHAPER_RAMA_END_CNTL_G__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000ffffUL
#define VPMPC_RMCM_SHAPER_RAMA_END_CNTL_G__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3fff0000UL

// VPMPC_RMCM_SHAPER_RAMA_END_CNTL_R
#define VPMPC_RMCM_SHAPER_RAMA_END_CNTL_R__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000ffffUL
#define VPMPC_RMCM_SHAPER_RAMA_END_CNTL_R__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3fff0000UL

// VPMPC_RMCM_SHAPER_RAMA_REGION_0_1
#define VPMPC_RMCM_SHAPER_RAMA_REGION_0_1__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_0_1__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_0_1__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_0_1__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPC_RMCM_SHAPER_RAMA_REGION_2_3
#define VPMPC_RMCM_SHAPER_RAMA_REGION_2_3__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_2_3__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_2_3__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_2_3__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPC_RMCM_SHAPER_RAMA_REGION_4_5
#define VPMPC_RMCM_SHAPER_RAMA_REGION_4_5__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_4_5__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_4_5__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_4_5__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPC_RMCM_SHAPER_RAMA_REGION_6_7
#define VPMPC_RMCM_SHAPER_RAMA_REGION_6_7__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_6_7__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_6_7__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_6_7__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPC_RMCM_SHAPER_RAMA_REGION_8_9
#define VPMPC_RMCM_SHAPER_RAMA_REGION_8_9__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_8_9__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_8_9__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_8_9__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPC_RMCM_SHAPER_RAMA_REGION_10_11
#define VPMPC_RMCM_SHAPER_RAMA_REGION_10_11__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_10_11__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_10_11__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_10_11__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPC_RMCM_SHAPER_RAMA_REGION_12_13
#define VPMPC_RMCM_SHAPER_RAMA_REGION_12_13__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_12_13__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_12_13__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_12_13__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPC_RMCM_SHAPER_RAMA_REGION_14_15
#define VPMPC_RMCM_SHAPER_RAMA_REGION_14_15__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_14_15__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_14_15__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_14_15__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPC_RMCM_SHAPER_RAMA_REGION_16_17
#define VPMPC_RMCM_SHAPER_RAMA_REGION_16_17__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_16_17__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_16_17__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_16_17__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPC_RMCM_SHAPER_RAMA_REGION_18_19
#define VPMPC_RMCM_SHAPER_RAMA_REGION_18_19__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_18_19__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_18_19__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_18_19__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPC_RMCM_SHAPER_RAMA_REGION_20_21
#define VPMPC_RMCM_SHAPER_RAMA_REGION_20_21__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_20_21__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_20_21__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_20_21__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPC_RMCM_SHAPER_RAMA_REGION_22_23
#define VPMPC_RMCM_SHAPER_RAMA_REGION_22_23__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_22_23__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_22_23__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_22_23__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPC_RMCM_SHAPER_RAMA_REGION_24_25
#define VPMPC_RMCM_SHAPER_RAMA_REGION_24_25__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_24_25__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_24_25__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_24_25__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPC_RMCM_SHAPER_RAMA_REGION_26_27
#define VPMPC_RMCM_SHAPER_RAMA_REGION_26_27__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_26_27__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_26_27__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_26_27__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPC_RMCM_SHAPER_RAMA_REGION_28_29
#define VPMPC_RMCM_SHAPER_RAMA_REGION_28_29__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_28_29__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_28_29__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_28_29__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPC_RMCM_SHAPER_RAMA_REGION_30_31
#define VPMPC_RMCM_SHAPER_RAMA_REGION_30_31__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_30_31__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_30_31__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_30_31__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPC_RMCM_SHAPER_RAMA_REGION_32_33
#define VPMPC_RMCM_SHAPER_RAMA_REGION_32_33__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001ffUL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_32_33__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_32_33__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01ff0000UL
#define VPMPC_RMCM_SHAPER_RAMA_REGION_32_33__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000UL

// VPMPC_RMCM_3DLUT_MODE
#define VPMPC_RMCM_3DLUT_MODE__VPMPC_RMCM_3DLUT_MODE_MASK  0x00000003UL
#define VPMPC_RMCM_3DLUT_MODE__VPMPC_RMCM_3DLUT_SIZE_MASK  0x00000030UL
#define VPMPC_RMCM_3DLUT_MODE__VPMPC_RMCM_3DLUT_MODE_CURRENT_MASK 0x00000300UL
#define VPMPC_RMCM_3DLUT_MODE__VPMPC_RMCM_3DLUT_SELECT_CURRENT_MASK 0x00000400UL

// VPMPC_RMCM_3DLUT_INDEX
#define VPMPC_RMCM_3DLUT_INDEX__VPMPC_RMCM_3DLUT_INDEX_MASK 0x00003fffUL

// VPMPC_RMCM_3DLUT_DATA
#define VPMPC_RMCM_3DLUT_DATA__VPMPC_RMCM_3DLUT_DATA0_MASK 0x0000ffffUL
#define VPMPC_RMCM_3DLUT_DATA__VPMPC_RMCM_3DLUT_DATA1_MASK 0xffff0000UL

// VPMPC_RMCM_3DLUT_DATA_30BIT
#define VPMPC_RMCM_3DLUT_DATA_30BIT__VPMPC_RMCM_3DLUT_DATA_30BIT_MASK 0xfffffffcUL

// VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL
#define VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL__VPMPC_RMCM_3DLUT_WRITE_EN_MASK_MASK 0x0000000fUL
#define VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL__VPMPC_RMCM_3DLUT_RAM_SEL_MASK 0x00000010UL
#define VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL__VPMPC_RMCM_3DLUT_30BIT_EN_MASK 0x00000100UL
#define VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL__VPMPC_RMCM_3DLUT_READ_SEL_MASK 0x00030000UL

// VPMPC_RMCM_3DLUT_OUT_NORM_FACTOR
#define VPMPC_RMCM_3DLUT_OUT_NORM_FACTOR__VPMPC_RMCM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000ffffUL

// VPMPC_RMCM_3DLUT_OUT_OFFSET_R
#define VPMPC_RMCM_3DLUT_OUT_OFFSET_R__VPMPC_RMCM_3DLUT_OUT_OFFSET_R_MASK 0x0000ffffUL
#define VPMPC_RMCM_3DLUT_OUT_OFFSET_R__VPMPC_RMCM_3DLUT_OUT_SCALE_R_MASK 0xffff0000UL

// VPMPC_RMCM_3DLUT_OUT_OFFSET_G
#define VPMPC_RMCM_3DLUT_OUT_OFFSET_G__VPMPC_RMCM_3DLUT_OUT_OFFSET_G_MASK 0x0000ffffUL
#define VPMPC_RMCM_3DLUT_OUT_OFFSET_G__VPMPC_RMCM_3DLUT_OUT_SCALE_G_MASK 0xffff0000UL

// VPMPC_RMCM_3DLUT_OUT_OFFSET_B
#define VPMPC_RMCM_3DLUT_OUT_OFFSET_B__VPMPC_RMCM_3DLUT_OUT_OFFSET_B_MASK 0x0000ffffUL
#define VPMPC_RMCM_3DLUT_OUT_OFFSET_B__VPMPC_RMCM_3DLUT_OUT_SCALE_B_MASK 0xffff0000UL

// VPMPC_RMCM_GAMUT_REMAP_COEF_FORMAT
#define VPMPC_RMCM_GAMUT_REMAP_COEF_FORMAT__VPMPC_RMCM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001UL

// VPMPC_RMCM_GAMUT_REMAP_MODE
#define VPMPC_RMCM_GAMUT_REMAP_MODE__VPMPC_RMCM_GAMUT_REMAP_MODE_MASK 0x00000003UL
#define VPMPC_RMCM_GAMUT_REMAP_MODE__VPMPC_RMCM_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180UL

// VPMPC_RMCM_GAMUT_REMAP_C11_C12_SETA
#define VPMPC_RMCM_GAMUT_REMAP_C11_C12_SETA__VPMPC_RMCM_GAMUT_REMAP_C11_SETA_MASK 0x0000ffffUL
#define VPMPC_RMCM_GAMUT_REMAP_C11_C12_SETA__VPMPC_RMCM_GAMUT_REMAP_C12_SETA_MASK 0xffff0000UL

// VPMPC_RMCM_GAMUT_REMAP_C13_C14_SETA
#define VPMPC_RMCM_GAMUT_REMAP_C13_C14_SETA__VPMPC_RMCM_GAMUT_REMAP_C13_SETA_MASK 0x0000ffffUL
#define VPMPC_RMCM_GAMUT_REMAP_C13_C14_SETA__VPMPC_RMCM_GAMUT_REMAP_C14_SETA_MASK 0xffff0000UL

// VPMPC_RMCM_GAMUT_REMAP_C21_C22_SETA
#define VPMPC_RMCM_GAMUT_REMAP_C21_C22_SETA__VPMPC_RMCM_GAMUT_REMAP_C21_SETA_MASK 0x0000ffffUL
#define VPMPC_RMCM_GAMUT_REMAP_C21_C22_SETA__VPMPC_RMCM_GAMUT_REMAP_C22_SETA_MASK 0xffff0000UL

// VPMPC_RMCM_GAMUT_REMAP_C23_C24_SETA
#define VPMPC_RMCM_GAMUT_REMAP_C23_C24_SETA__VPMPC_RMCM_GAMUT_REMAP_C23_SETA_MASK 0x0000ffffUL
#define VPMPC_RMCM_GAMUT_REMAP_C23_C24_SETA__VPMPC_RMCM_GAMUT_REMAP_C24_SETA_MASK 0xffff0000UL

// VPMPC_RMCM_GAMUT_REMAP_C31_C32_SETA
#define VPMPC_RMCM_GAMUT_REMAP_C31_C32_SETA__VPMPC_RMCM_GAMUT_REMAP_C31_SETA_MASK 0x0000ffffUL
#define VPMPC_RMCM_GAMUT_REMAP_C31_C32_SETA__VPMPC_RMCM_GAMUT_REMAP_C32_SETA_MASK 0xffff0000UL

// VPMPC_RMCM_GAMUT_REMAP_C33_C34_SETA
#define VPMPC_RMCM_GAMUT_REMAP_C33_C34_SETA__VPMPC_RMCM_GAMUT_REMAP_C33_SETA_MASK 0x0000ffffUL
#define VPMPC_RMCM_GAMUT_REMAP_C33_C34_SETA__VPMPC_RMCM_GAMUT_REMAP_C34_SETA_MASK 0xffff0000UL

// VPMPC_RMCM_MEM_PWR_CTRL
#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_SHAPER_MEM_PWR_FORCE_MASK 0x00000003UL
#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_SHAPER_MEM_PWR_DIS_MASK 0x00000004UL
#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_SHAPER_MEM_LOW_PWR_MODE_MASK 0x00000030UL
#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_3DLUT_MEM_PWR_FORCE_MASK 0x00000300UL
#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_3DLUT_MEM_PWR_DIS_MASK 0x00000400UL
#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_3DLUT_MEM_LOW_PWR_MODE_MASK 0x00003000UL
#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_SHAPER_MEM_PWR_STATE_MASK 0x03000000UL
#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_3DLUT_MEM_PWR_STATE_MASK 0x0c000000UL

// VPMPC_RMCM_3DLUT_FAST_LOAD_SELECT
#define VPMPC_RMCM_3DLUT_FAST_LOAD_SELECT__VPMPC_RMCM_3DLUT_FL_SEL_MASK 0x0000000fUL

// VPMPC_RMCM_3DLUT_FAST_LOAD_STATUS
#define VPMPC_RMCM_3DLUT_FAST_LOAD_STATUS__VPMPC_RMCM_3DLUT_FL_DONE_MASK 0x00000001UL

// VPMPC_RMCM_CNTL
#define VPMPC_RMCM_CNTL__VPMPC_RMCM_CNTL_MASK              0x0000000fUL

// VPMPC_RMCM_TEST_DEBUG_INDEX
#define VPMPC_RMCM_TEST_DEBUG_INDEX__VPMPC_RMCM_TEST_DEBUG_INDEX_MASK 0x000000ffUL
#define VPMPC_RMCM_TEST_DEBUG_INDEX__VPMPC_RMCM_TEST_DEBUG_WRITE_EN_MASK 0x00000100UL

// VPMPC_RMCM_TEST_DEBUG_DATA
#define VPMPC_RMCM_TEST_DEBUG_DATA__VPMPC_RMCM_TEST_DEBUG_DATA_MASK 0xffffffffUL

// VPFMT_CLAMP_COMPONENT_R
#define VPFMT_CLAMP_COMPONENT_R__VPFMT_CLAMP_LOWER_R_MASK  0x0000ffffUL
#define VPFMT_CLAMP_COMPONENT_R__VPFMT_CLAMP_UPPER_R_MASK  0xffff0000UL

// VPFMT_CLAMP_COMPONENT_G
#define VPFMT_CLAMP_COMPONENT_G__VPFMT_CLAMP_LOWER_G_MASK  0x0000ffffUL
#define VPFMT_CLAMP_COMPONENT_G__VPFMT_CLAMP_UPPER_G_MASK  0xffff0000UL

// VPFMT_CLAMP_COMPONENT_B
#define VPFMT_CLAMP_COMPONENT_B__VPFMT_CLAMP_LOWER_B_MASK  0x0000ffffUL
#define VPFMT_CLAMP_COMPONENT_B__VPFMT_CLAMP_UPPER_B_MASK  0xffff0000UL

// VPFMT_DYNAMIC_EXP_CNTL
#define VPFMT_DYNAMIC_EXP_CNTL__VPFMT_DYNAMIC_EXP_EN_MASK  0x00000001UL
#define VPFMT_DYNAMIC_EXP_CNTL__VPFMT_DYNAMIC_EXP_MODE_MASK 0x00000010UL

// VPFMT_CONTROL
#define VPFMT_CONTROL__VPFMT_PIXEL_ENCODING_MASK           0x00000003UL
#define VPFMT_CONTROL__VPFMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00000010UL
#define VPFMT_CONTROL__VPFMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000f00UL
#define VPFMT_CONTROL__VPFMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000UL
#define VPFMT_CONTROL__VPFMT_SUBSAMPLE_HTAPS_MASK          0x00030000UL
#define VPFMT_CONTROL__VPFMT_SUBSAMPLE_LEFT_EDGE_MASK      0x00040000UL
#define VPFMT_CONTROL__VPFMT_SUBSAMPLE_RIGHT_EDGE_MASK     0x00080000UL
#define VPFMT_CONTROL__VPFMT_SUBSAMPLE_VTAPS_MASK          0x00300000UL
#define VPFMT_CONTROL__VPFMT_SUBSAMPLE_TOP_EDGE_MASK       0x00400000UL
#define VPFMT_CONTROL__VPFMT_SUBSAMPLE_BOTTOM_EDGE_MASK    0x00800000UL
#define VPFMT_CONTROL__VPFMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000UL

// VPFMT_BIT_DEPTH_CONTROL
#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_TRUNCATE_EN_MASK    0x00000001UL
#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_TRUNCATE_MODE_MASK  0x00000002UL
#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_TRUNCATE_DEPTH_MASK 0x00000030UL
#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_SPATIAL_DITHER_EN_MASK 0x00000100UL
#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_SPATIAL_DITHER_MODE_MASK 0x00000600UL
#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800UL
#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_FRAME_RANDOM_ENABLE_MASK 0x00002000UL
#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_RGB_RANDOM_ENABLE_MASK 0x00004000UL
#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000UL

// VPFMT_DITHER_RAND_R_SEED
#define VPFMT_DITHER_RAND_R_SEED__VPFMT_RAND_R_SEED_MASK   0x000000ffUL
#define VPFMT_DITHER_RAND_R_SEED__VPFMT_OFFSET_R_CR_MASK   0xffff0000UL

// VPFMT_DITHER_RAND_G_SEED
#define VPFMT_DITHER_RAND_G_SEED__VPFMT_RAND_G_SEED_MASK   0x000000ffUL
#define VPFMT_DITHER_RAND_G_SEED__VPFMT_OFFSET_G_Y_MASK    0xffff0000UL

// VPFMT_DITHER_RAND_B_SEED
#define VPFMT_DITHER_RAND_B_SEED__VPFMT_RAND_B_SEED_MASK   0x000000ffUL
#define VPFMT_DITHER_RAND_B_SEED__VPFMT_OFFSET_B_CB_MASK   0xffff0000UL

// VPFMT_CLAMP_CNTL
#define VPFMT_CLAMP_CNTL__VPFMT_CLAMP_DATA_EN_MASK         0x00000001UL
#define VPFMT_CLAMP_CNTL__VPFMT_CLAMP_COLOR_FORMAT_MASK    0x00070000UL

// VPFMT_SUBSAMPLER_MEMORY_CONTROL
#define VPFMT_SUBSAMPLER_MEMORY_CONTROL__VPFMT_SUBSAMPLER_MEM_PWR_FORCE_MASK 0x00000003UL
#define VPFMT_SUBSAMPLER_MEMORY_CONTROL__VPFMT_SUBSAMPLER_MEM_PWR_DIS_MASK 0x00000010UL
#define VPFMT_SUBSAMPLER_MEMORY_CONTROL__VPFMT_SUBSAMPLER_MEM_PWR_STATE_MASK 0x00000300UL
#define VPFMT_SUBSAMPLER_MEMORY_CONTROL__VPFMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000UL

// VPFMT_DEBUG_CNTL
#define VPFMT_DEBUG_CNTL__VPFMT_DEBUG_COLOR_SELECT_MASK    0x00000003UL

// VPFMT_TEST_DEBUG_INDEX
#define VPFMT_TEST_DEBUG_INDEX__VPFMT_TEST_DEBUG_INDEX_MASK 0x000000ffUL
#define VPFMT_TEST_DEBUG_INDEX__VPFMT_TEST_DEBUG_WRITE_EN_MASK 0x00000100UL

// VPFMT_TEST_DEBUG_DATA
#define VPFMT_TEST_DEBUG_DATA__VPFMT_TEST_DEBUG_DATA_MASK  0xffffffffUL

// VPOPP_PIPE_CONTROL
#define VPOPP_PIPE_CONTROL__VPOPP_PIPE_CLOCK_ON_MASK       0x00000002UL
#define VPOPP_PIPE_CONTROL__VPOPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010UL
#define VPOPP_PIPE_CONTROL__VPOPP_PIPE_ALPHA_SEL_MASK      0x00000020UL
#define VPOPP_PIPE_CONTROL__VPOPP_PIPE_ALPHA_MASK          0xffff0000UL

// VPOPP_PIPE_OUTBG_EXT1
#define VPOPP_PIPE_OUTBG_EXT1__OUTBG_EXT_TOP_MASK          0x00003fffUL
#define VPOPP_PIPE_OUTBG_EXT1__OUTBG_EXT_BOT_MASK          0x0fffc000UL

// VPOPP_PIPE_OUTBG_EXT2
#define VPOPP_PIPE_OUTBG_EXT2__OUTBG_EXT_LEFT_MASK         0x000007ffUL
#define VPOPP_PIPE_OUTBG_EXT2__OUTBG_EXT_RIGHT_MASK        0x003ff800UL

// VPOPP_PIPE_OUTBG_COL1
#define VPOPP_PIPE_OUTBG_COL1__OUTBG_R_CR_MASK             0x0000ffffUL
#define VPOPP_PIPE_OUTBG_COL1__OUTBG_B_CB_MASK             0xffff0000UL

// VPOPP_PIPE_OUTBG_COL2
#define VPOPP_PIPE_OUTBG_COL2__OUTBG_Y_MASK                0x0000ffffUL

// VPOPP_PIPE_SPARE_DEBUG
#define VPOPP_PIPE_SPARE_DEBUG__VPOPP_PIPE_SPARE_DEBUG_MASK 0xffffffffUL

// VPOPP_PIPE_TEST_DEBUG_INDEX
#define VPOPP_PIPE_TEST_DEBUG_INDEX__VPOPP_PIPE_TEST_DEBUG_INDEX_MASK 0x000000ffUL

// VPOPP_PIPE_TEST_DEBUG_DATA
#define VPOPP_PIPE_TEST_DEBUG_DATA__VPOPP_PIPE_TEST_DEBUG_DATA_MASK 0xffffffffUL

// VPOPP_TOP_CLK_CONTROL
#define VPOPP_TOP_CLK_CONTROL__VPOPP_VPECLK_R_GATE_DIS_MASK 0x00000001UL
#define VPOPP_TOP_CLK_CONTROL__VPOPP_VPECLK_G_GATE_DIS_MASK 0x00000002UL

// VPOPP_DEBUG_CONTROL
#define VPOPP_DEBUG_CONTROL__VPOPP_DBG_EN_MASK             0x00000001UL
#define VPOPP_DEBUG_CONTROL__VPOPP_VPFMT_DEBUG_BUS_SELECT_MASK 0x000000f0UL
#define VPOPP_DEBUG_CONTROL__VPOPP_VPOPP_PIPE_DEBUG_BUS_SELECT_MASK 0x00070000UL

// VPOPP_CRC_CONTROL
#define VPOPP_CRC_CONTROL__VPOPP_CRC_EN_MASK               0x00000001UL
#define VPOPP_CRC_CONTROL__VPOPP_CRC_CONT_EN_MASK          0x00000002UL
#define VPOPP_CRC_CONTROL__VPOPP_CRC_PIXEL_SELECT_MASK     0x0000000cUL
#define VPOPP_CRC_CONTROL__VPOPP_CRC_SOURCE_SELECT_MASK    0x00000030UL
#define VPOPP_CRC_CONTROL__VPOPP_CRC_PIPE_SELECT_MASK      0x00000040UL
#define VPOPP_CRC_CONTROL__VPOPP_CRC_MASK_MASK             0x00ffff00UL
#define VPOPP_CRC_CONTROL__VPOPP_CRC_ONE_SHOT_PENDING_MASK 0x80000000UL

// VPOPP_CRC_RESULT_RG
#define VPOPP_CRC_RESULT_RG__VPOPP_CRC_RESULT_R_MASK       0x0000ffffUL
#define VPOPP_CRC_RESULT_RG__VPOPP_CRC_RESULT_G_MASK       0xffff0000UL

// VPOPP_CRC_RESULT_BC
#define VPOPP_CRC_RESULT_BC__VPOPP_CRC_RESULT_B_MASK       0x0000ffffUL
#define VPOPP_CRC_RESULT_BC__VPOPP_CRC_RESULT_C_MASK       0xffff0000UL

// VPOPP_FROD_CONTROL
#define VPOPP_FROD_CONTROL__FROD_EN_MASK                   0x00000001UL

// VPOPP_FROD_MEM_PWR_CONTROL
#define VPOPP_FROD_MEM_PWR_CONTROL__FROD_MEM_PWR_FORCE_MASK 0x00000003UL
#define VPOPP_FROD_MEM_PWR_CONTROL__FROD_MEM_PWR_DIS_MASK  0x00000010UL
#define VPOPP_FROD_MEM_PWR_CONTROL__FROD_MEM_PWR_STATE_MASK 0x00000300UL
#define VPOPP_FROD_MEM_PWR_CONTROL__FROD_MEM_DEFAULT_LOW_PWR_STATE_MASK 0x00003000UL

// VPOPP_TOP_SPARE_DEBUG
#define VPOPP_TOP_SPARE_DEBUG__VPOPP_TOP_SPARE_DEBUG_MASK  0xffffffffUL

// VPOPP_TOP_TEST_DEBUG_INDEX
#define VPOPP_TOP_TEST_DEBUG_INDEX__VPOPP_TOP_TEST_DEBUG_INDEX_MASK 0x000000ffUL

// VPOPP_TOP_TEST_DEBUG_DATA
#define VPOPP_TOP_TEST_DEBUG_DATA__VPOPP_TOP_TEST_DEBUG_DATA_MASK 0xffffffffUL

#endif
